JPH06509671A - - Google Patents

Info

Publication number
JPH06509671A
JPH06509671A JP50333193A JP50333193A JPH06509671A JP H06509671 A JPH06509671 A JP H06509671A JP 50333193 A JP50333193 A JP 50333193A JP 50333193 A JP50333193 A JP 50333193A JP H06509671 A JPH06509671 A JP H06509671A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50333193A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR9109649A priority Critical patent/FR2680026B1/fr
Application filed filed Critical
Priority to PCT/FR1992/000751 priority patent/WO1993003441A1/fr
Publication of JPH06509671A publication Critical patent/JPH06509671A/ja
Application status is Pending legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337Direct connection machines, e.g. completely connected computers, point to point communication networks
JP50333193A 1991-07-30 1992-07-30 Pending JPH06509671A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR9109649A FR2680026B1 (fr) 1991-07-30 1991-07-30 Architecture de systeme en tableau de processeurs a structure parallele.
PCT/FR1992/000751 WO1993003441A1 (fr) 1991-07-30 1992-07-30 Architecture de systeme en tableau de processeurs a structure parallele

Publications (1)

Publication Number Publication Date
JPH06509671A true JPH06509671A (ja) 1994-10-27

Family

ID=9415701

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50333193A Pending JPH06509671A (ja) 1991-07-30 1992-07-30

Country Status (7)

Country Link
US (1) US5504918A (ja)
EP (1) EP0597028B1 (ja)
JP (1) JPH06509671A (ja)
CA (1) CA2113435C (ja)
DE (2) DE69217663D1 (ja)
FR (1) FR2680026B1 (ja)
WO (1) WO1993003441A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002533813A (ja) * 1998-12-21 2002-10-08 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド メモリキャンセルメッセージを用いたシステムメモリ帯域幅の節約およびキャッシュコヒーレンシ維持
JP2006012133A (ja) * 2004-05-28 2006-01-12 Intel Corp 双方向性リング相互接続路を有する多重プロセッサチップ
WO2007099950A1 (ja) * 2006-03-03 2007-09-07 Nec Corporation 高速pe間データ再配置機能を有するプロセッサアレイシステム

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2710993B1 (fr) * 1993-10-04 1995-11-24 Commissariat Energie Atomique Procédé et système d'interconnexion pour la gestion de messages dans un réseau de processeurs à structure parallèle.
FR2742560B1 (fr) * 1995-12-19 1998-01-16 Commissariat Energie Atomique Architecture de systeme en tableau de processeurs a structures paralleles multiples
US5903771A (en) * 1996-01-16 1999-05-11 Alacron, Inc. Scalable multi-processor architecture for SIMD and MIMD operations
JPH10232788A (ja) * 1996-12-17 1998-09-02 Fujitsu Ltd 信号処理装置及びソフトウェア
US5911056A (en) * 1997-05-01 1999-06-08 Hewlett-Packard Co. High speed interconnect bus
GB2367732B (en) * 1997-05-01 2002-09-04 Hewlett Packard Co High speed interconnect bus
DE19816153B4 (de) * 1997-05-01 2005-06-23 Hewlett-Packard Development Co., L.P., Houston Busverbindungssystem
US5909562A (en) * 1997-05-01 1999-06-01 Hewlett-Packard Co. Backup FIFO in-line storage
US5907691A (en) * 1997-05-01 1999-05-25 Hewlett-Packard Co. Dual pipelined interconnect
ES2129004B1 (es) * 1997-09-12 2000-01-01 Consejo Superior Investigacion Sistema de ensayos no destructivos de arquitectura segmentada (sendas).
US6513108B1 (en) * 1998-06-29 2003-01-28 Cisco Technology, Inc. Programmable processing engine for efficiently processing transient data
AU2003228353A1 (en) * 2002-03-22 2003-10-13 Michael F. Deering Scalable high performance 3d graphics
US7447872B2 (en) * 2002-05-30 2008-11-04 Cisco Technology, Inc. Inter-chip processor control plane communication
KR100974361B1 (ko) * 2002-10-22 2010-08-05 제이슨 에이. 설리반 동적 모듈식 처리 유닛을 제공하기 위한 시스템 및 방법
AU2003284329A1 (en) * 2002-10-22 2004-05-13 Isys Technologies Robust customizable computer processing system
EP1557075A4 (en) * 2002-10-22 2010-01-13 Sullivan Jason Non-peripherals processing control module having improved heat dissipating properties
US7515156B2 (en) * 2003-01-08 2009-04-07 Hrl Laboratories, Llc Method and apparatus for parallel speculative rendering of synthetic images
US20050138324A1 (en) * 2003-12-19 2005-06-23 International Business Machines Corporation Processing unit having a dual channel bus architecture
US7308558B2 (en) * 2004-01-07 2007-12-11 International Business Machines Corporation Multiprocessor data processing system having scalable data interconnect and data routing mechanism
US7007128B2 (en) * 2004-01-07 2006-02-28 International Business Machines Corporation Multiprocessor data processing system having a data routing mechanism regulated through control communication
US20060026214A1 (en) * 2004-07-29 2006-02-02 International Business Machines Corporation Switching from synchronous to asynchronous processing
US7500043B2 (en) * 2005-04-22 2009-03-03 Altrix Logic, Inc. Array of data processing elements with variable precision interconnect
JP5460156B2 (ja) * 2009-07-14 2014-04-02 キヤノン株式会社 データ処理装置
JP5835942B2 (ja) * 2010-06-25 2015-12-24 キヤノン株式会社 画像処理装置、その制御方法及びプログラム

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4719622A (en) * 1985-03-15 1988-01-12 Wang Laboratories, Inc. System bus means for inter-processor communication
JP2781550B2 (ja) * 1985-05-10 1998-07-30 株式会社日立製作所 並列処理計算機
EP0367182A3 (en) * 1988-10-31 1992-07-22 Bts Broadcast Television Systems Gmbh High-speed digital computing system
US5218709A (en) * 1989-12-28 1993-06-08 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Special purpose parallel computer architecture for real-time control and simulation in robotic applications
US5208900A (en) * 1990-10-22 1993-05-04 Motorola, Inc. Digital neural network computation ring

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002533813A (ja) * 1998-12-21 2002-10-08 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド メモリキャンセルメッセージを用いたシステムメモリ帯域幅の節約およびキャッシュコヒーレンシ維持
JP2006012133A (ja) * 2004-05-28 2006-01-12 Intel Corp 双方向性リング相互接続路を有する多重プロセッサチップ
WO2007099950A1 (ja) * 2006-03-03 2007-09-07 Nec Corporation 高速pe間データ再配置機能を有するプロセッサアレイシステム
US7783861B2 (en) 2006-03-03 2010-08-24 Nec Corporation Data reallocation among PEs connected in both directions to respective PEs in adjacent blocks by selecting from inter-block and intra block transfers

Also Published As

Publication number Publication date
US5504918A (en) 1996-04-02
FR2680026B1 (fr) 1996-12-20
EP0597028B1 (fr) 1997-02-26
EP0597028A1 (fr) 1994-05-18
DE69217663D1 (de) 1997-04-03
DE69217663T2 (de) 1997-09-04
WO1993003441A1 (fr) 1993-02-18
CA2113435A1 (fr) 1993-02-18
FR2680026A1 (fr) 1993-02-05
CA2113435C (fr) 2003-01-14

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