JPH0650815B2 - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPH0650815B2
JPH0650815B2 JP61097271A JP9727186A JPH0650815B2 JP H0650815 B2 JPH0650815 B2 JP H0650815B2 JP 61097271 A JP61097271 A JP 61097271A JP 9727186 A JP9727186 A JP 9727186A JP H0650815 B2 JPH0650815 B2 JP H0650815B2
Authority
JP
Japan
Prior art keywords
logic circuit
power supply
mos transistor
input
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61097271A
Other languages
Japanese (ja)
Other versions
JPS62253221A (en
Inventor
要二 平野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61097271A priority Critical patent/JPH0650815B2/en
Publication of JPS62253221A publication Critical patent/JPS62253221A/en
Publication of JPH0650815B2 publication Critical patent/JPH0650815B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1731—Optimisation thereof
    • H03K19/1732—Optimisation thereof by limitation or reduction of the pin/gate ratio

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は論理回路に関し、特に相補型ＭＯＳ（ＣＭＯ
Ｓ）論理回路の入力端子のフローティング状態を回避す
る論理回路に関する。The present invention relates to a logic circuit, and more particularly to a complementary MOS (CMO).
S) A logic circuit for avoiding a floating state of an input terminal of the logic circuit.

〔従来の技術〕[Conventional technology]

従来、この種の論理回路には、第３図に示すような回路
が使用されていた。この論理回路は、通常の論理動作時
には、制御端子５に低レベル電位を印加し、高電位側電
源１にソースが接続されたＰチャンネル型ＭＯＳトラン
ジスタ（PMOST）Ｑ５を導通状態、低電位側電源２にソ
ースが接続されたＮチャンネル型ＭＯＳトランジスタ
（ＮＭＯＳＴ）Ｑ６をしゃ断状態にしておき、入力端子
３に入力信号を印加し出力端子４から論理出力を得るも
のであるが、入力端子３に入力信号を印加しない場合、
いわゆるフローティング状態にした場合には、制御端子
５に高レベル電位を印加してＰＭＯＳＴＱ５をしゃ断状
態，ＮＭＯＳＴＱ６を導通状態にし、ＰＭＯＳＴＱ５，
Ｑ１およびNMOSTＱ２を通して流れる貫通電流を阻止す
ると共に出力を低レベルに電位し、次段の論理回路の入
力フローティング状態を回避するよう構成されている。Conventionally, a circuit as shown in FIG. 3 has been used for this type of logic circuit. In a normal logic operation, this logic circuit applies a low-level potential to the control terminal 5 and turns on a P-channel MOS transistor (PMOST) Q 5 whose source is connected to the high-potential side power source 1 in a conductive state and a low-potential side. The N-channel type MOS transistor (NMOST) Q 6 whose source is connected to the power source 2 is cut off, and an input signal is applied to the input terminal 3 to obtain a logical output from the output terminal 4. If no input signal is applied to
In the case of a so-called floating state, a high level potential is applied to the control terminal 5 to turn off the PMOS TQ 5 and turn on the NMOS TQ 6 to turn on the PMOS TQ 5 ,
And the potential output to the low level while preventing a through current flowing through Q 1 and NMOSTQ 2, is configured to avoid an input floating state of the next-stage logic circuit.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

上述した従来の論理回路では、入力フローティングの防
止に２個のＭＯＳトランジスタを必要とするため、使用
素子数が増加するという欠点がある。The conventional logic circuit described above requires two MOS transistors to prevent input floating, and thus has the drawback of increasing the number of elements used.

また、入力端子がフローティング状態になった場合に、
貫通電流を阻止するための制御端子が必要であり、信号
端子数が増加するという欠点も有している。Also, when the input terminal is in the floating state,
A control terminal for blocking a through current is required, which has a drawback that the number of signal terminals increases.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の論理回路は、Ｐチャンネル型ＭＯＳトランジス
タとＮチャンネル型ＭＯＳトランジスタとからなる相補
型ＭＯＳ論理回路と、ゲートが第１の電源端子に接続さ
れソースが第２の電源端子に接続されドレインが前記相
補型ＭＯＳ論理回路の入力に接続された電位固定用ＭＯ
Ｓトランジスタとにより構成された論理回路であって、
前記電位固定用ＭＯＳトランジスタの閾値電圧は前記相
補型ＭＯＳ論理回路に入力信号を与えている動作期間の
前記第１及び第２電源端子間の動作電源電圧より高く設
定されていて前記電位固定用ＭＯＳトランジスタは前記
動作期間非導通状態となっており、前記入力信号が前記
相補型ＭＯＳ論理回路に入力されていない期間に前記第
１及び第２の電源端子間の電圧を前記動作期間のそれよ
りも大きくすることにより前記電位固定用ＭＯＳトラン
ジスタは導通状態とされて前記相補型論理回路への入力
を所定の電位に固定することを特徴とする。The logic circuit of the present invention includes a complementary MOS logic circuit including a P-channel MOS transistor and an N-channel MOS transistor, a gate connected to a first power supply terminal, a source connected to a second power supply terminal, and a drain connected to a drain. Potential fixing MO connected to the input of the complementary MOS logic circuit
A logic circuit including an S transistor,
The threshold voltage of the potential fixing MOS transistor is set higher than the operating power supply voltage between the first and second power supply terminals during the operation period in which the input signal is applied to the complementary MOS logic circuit, and the potential fixing MOS transistor is set. The transistor is non-conductive during the operation period, and the voltage between the first and second power supply terminals is set to be higher than that during the operation period while the input signal is not input to the complementary MOS logic circuit. By increasing the voltage, the potential fixing MOS transistor is rendered conductive, and the input to the complementary logic circuit is fixed at a predetermined potential.

本発明によれば、通常の電源電圧では、この電位固定用
ＭＯＳトランジスタはしゃ断状態になっており、論理動
作には全く影響しないためＣＭＯＳ論理回路の出力をそ
のまま出力することができ、一方、電源電圧をこの電位
固定用ＭＯＳトランジスタの閾値より高くするとこの電
位固定用ＭＯＳトランジスタが導通状態になるため、入
力端子に信号が印加されていない場合にも、入力レベル
を低レベルまたは高レベルに設定することができる。According to the present invention, at a normal power supply voltage, the potential fixing MOS transistor is in the cut-off state, and since it does not affect the logic operation at all, the output of the CMOS logic circuit can be output as it is. When the voltage is higher than the threshold value of the potential fixing MOS transistor, the potential fixing MOS transistor becomes conductive, so that the input level is set to the low level or the high level even when no signal is applied to the input terminal. be able to.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.

第１図は、本発明の第１の実施例を示す回路図である。
本実施例は、入力端子３への入力に対する反転出力を出
力端子４に出力するＣＭＯＳ論理回路に、ゲートが高電
位側電源１に接続されソースが低電位側電源（ＧＮＤ）
２に接続されドレインが入力端子３に接続されたＮチャ
ンネル型ＭＯＳトランジスタ（電位同定用ＭＯＳトラン
ジスタ）Ｑ３が付加された論理回路である。ここで、Ｎ
ＭＯＳＴＱ３の閾値は、通常の動作電源電圧すなわち高
電位側電源の電圧より高い値に設定されている。このた
め通常の電源電圧ではＮＭＯＳＴＱ３はしゃ断状態にな
っており、本回路は入力端子３への入力に対する反転回
路として動作する。一方、電源電圧をＮＭＯＳＴＱ３の
閾値より高くすると、ＮＭＯＳＴＱ３が導通状態にな
り、入力端子３に信号が印加されなくても入力を低レベ
ルにし、入力端子のフローティングによる貫通電流を阻
止することができる。FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
In this embodiment, in a CMOS logic circuit that outputs an inverted output for the input to the input terminal 3 to the output terminal 4, the gate is connected to the high potential side power source 1 and the source is the low potential side power source (GND).
2 is a logic circuit to which an N-channel type MOS transistor (potential identifying MOS transistor) Q 3 connected to 2 and having a drain connected to the input terminal 3 is added. Where N
The threshold value of the MOSTQ 3 is set to a value higher than the normal operating power supply voltage, that is, the voltage of the high potential side power supply. For this reason, the NMOS TQ 3 is in the cutoff state at the normal power supply voltage, and this circuit operates as an inverting circuit for the input to the input terminal 3. On the other hand, when the power supply voltage higher than the threshold value of NMOSTQ 3, that NMOSTQ 3 becomes conductive, even without a signal is applied to the input terminal 3 is input to the low level, to prevent a through current due to the floating of the input terminal it can.

第２図は、本発明の第２の実施例を示す回路図であり、
第１の実施例との違いは、通常の動作電源電圧より高い
閾値を持ったＮチャンネル型ＭＯＳトランジスタＱ３の
代りにＰチャンネル型ＭＯＳトランジスタＱ４を使用し
ていることであり、通常の動作電源電圧ではＰＭＯＳＴ
Ｑ４はしゃ断状態になっており、本回路は入力端子３へ
の入力に対する反転回路として動作する。一方、電源電
圧をＰＭＯＳＴＱ４の閾値より高くすると、ＰＭＯＳＴ
Ｑ４が導通状態になり、入力端子３に信号が印加されな
くても入力を高レベルにし、入力端子のフローティング
による貫通電流を阻止することができる。FIG. 2 is a circuit diagram showing a second embodiment of the present invention,
The difference from the first embodiment is that the P-channel type MOS transistor Q 4 is used instead of the N-channel type MOS transistor Q 3 having a threshold value higher than the normal operation power supply voltage, and the normal operation is performed. Power supply voltage is PMOST
Q 4 are have become cut off, the circuit operates as an inverting circuit for the input to the input terminal 3. On the other hand, if the power supply voltage is higher than the threshold value of PMOSTQ 4 ,
Even when Q 4 is in a conductive state and no signal is applied to the input terminal 3, the input can be set to a high level and a through current due to floating of the input terminal can be blocked.

〔発明の効果〕〔The invention's effect〕

本発明は、入力端子と電源との間に閾値電圧が通常の電
源電圧より高いＭＯＳトランジスタを設けることにより
電源電圧を高くするだけで入力端子のフローティングを
回避することができ、しかも従来回路のようなフローテ
ィングを回避するための制御端子を必要としないため、
スクリーニング用の治具および装置の簡略化が可能であ
るという効果がある。According to the present invention, by providing a MOS transistor having a threshold voltage higher than the normal power supply voltage between the input terminal and the power supply, it is possible to avoid the floating of the input terminal only by increasing the power supply voltage. Since it does not need a control terminal to avoid a simple floating,
The effect is that the screening jig and the device can be simplified.

また、余分な制御端子を必要としないことから、信号端
子を有効に利用できるため、効率の良いデバイス設計が
可能となるという効果もある。In addition, since an extra control terminal is not required, the signal terminal can be effectively used, which also has the effect of enabling efficient device design.

【図面の簡単な説明】[Brief description of drawings]

第１図は本発明の第１の実施例を示す回路図、第２図は
本発明の第２の実施例を示す回路図、第３図は従来の回
路例を示す回路図である。 １……高電位側電源、２……低電位側電源、３……入力
端子、４……出力端子、５……制御端子、Ｑ１，Ｑ４，
Ｑ５……Ｐチャンネル型電界効果トランジスタ、Ｑ２，
Ｑ３，Ｑ６……Ｎチャンネル型電界効果トランジスタ。FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a second embodiment of the present invention, and FIG. 3 is a circuit diagram showing a conventional circuit example. 1 ...... high potential side power supply, 2 ...... low potential side power supply, 3 ...... input terminal, 4 ...... output terminal, 5 ...... control terminals, Q 1, Q 4,
Q 5 ... P-channel field effect transistor, Q 2 ,
Q 3 , Q 6 ... N-channel field effect transistors.

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】Ｐチャンネル型ＭＯＳトランジスタとＮチ
ャンネル型ＭＯＳトランジスタとからなる相補型ＭＯＳ
論理回路と、ゲートが第１の電源端子に接続されソース
が第２の電源端子に接続されドレインが前記相補型ＭＯ
Ｓ論理回路の入力に接続された電位固定用ＭＯＳトラン
ジスタとにより構成された論理回路であって、前記電位
固定用ＭＯＳトランジスタの閾値電圧は前記相補型ＭＯ
Ｓ論理回路に入力信号を与えている動作期間の前記第１
及び第２電源端子間の動作電源電圧より高く設定されて
いて前記電位固定用ＭＯＳトランジスタは前記動作期間
非導通状態となっており、前記入力信号が前記相補型Ｍ
ＯＳ論理回路に入力されていない期間に前記第１及び第
２の電源端子間の電圧を前記動作期間のそれよりも大き
くすることにより前記電位固定用ＭＯＳトランジスタは
導通状態とされて前記相補型論理回路への入力を所定の
電位に固定することを特徴とする論理回路。1. A complementary MOS comprising a P-channel MOS transistor and an N-channel MOS transistor.
A logic circuit, a gate connected to the first power supply terminal, a source connected to the second power supply terminal, and a drain connected to the complementary MO.
A logic circuit constituted by a potential fixing MOS transistor connected to an input of an S logic circuit, wherein the threshold voltage of the potential fixing MOS transistor is the complementary MO transistor.
The first period of the operation period in which the input signal is applied to the S logic circuit
And the potential fixing MOS transistor is set to be higher than the operating power supply voltage between the second power supply terminal and the operating power supply voltage, and the input signal is in the non-conducting state during the operating period.
By setting the voltage between the first and second power supply terminals to be higher than that during the operation period during a period when the voltage is not input to the OS logic circuit, the potential fixing MOS transistor is rendered conductive and the complementary logic A logic circuit characterized in that an input to the circuit is fixed to a predetermined potential.
JP61097271A 1986-04-25 1986-04-25 Logic circuit Expired - Lifetime JPH0650815B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61097271A JPH0650815B2 (en) 1986-04-25 1986-04-25 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61097271A JPH0650815B2 (en) 1986-04-25 1986-04-25 Logic circuit

Publications (2)

Publication Number Publication Date
JPS62253221A JPS62253221A (en) 1987-11-05
JPH0650815B2 true JPH0650815B2 (en) 1994-06-29

Family

ID=14187864

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61097271A Expired - Lifetime JPH0650815B2 (en) 1986-04-25 1986-04-25 Logic circuit

Country Status (1)

Country Link
JP (1) JPH0650815B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2862591B2 (en) * 1989-09-29 1999-03-03 株式会社東芝 Inrush current prevention circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61208315A (en) * 1985-03-12 1986-09-16 Mitsubishi Electric Corp Semiconductor integrated circuit device

Also Published As

Publication number Publication date
JPS62253221A (en) 1987-11-05

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