JPH0650530B2 - Data detection circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pair data detection circuit of a non-Neumann type data flow computer.

<Prior art> With the recent rapid development of information processing technology, the demand for high-speed processing of a large amount of data such as image information is increasing, and in place of the conventional sequential control Neumann computer,
A non-Neumann-type data flow computer, which has a hardware configuration that can perform parallel computations when any of the multiple instructions in a program have input data, is being researched, developed, and put into practical use.

As the data flow computer, for example, the one shown in FIG. 5 is known. This computer is
A program storage unit 21 for storing a program composed of a large number of packets translated by a compiler, a pair data detection circuit 22, and an arithmetic processing unit 23 composed of a plurality of adders and multipliers are connected in a communication network 24 in a loop. It becomes. Each packet 25 stored in the program storage unit 21 has a structure as shown in FIG. 6, and when the operation result data from the operation processing unit 23 is written in its data fields 28 and 29, the pair data detection is performed. It is sent to the circuit 22 where it waits for data until all the data fields 28, 29 are aligned. When the data fields are complete, the packet is sent to a predetermined arithmetic unit of the arithmetic processing unit 23,
The calculation result data is processed according to the calculation command written in the command field 27, and the calculation result data is passed through the communication network 24 and the program storage unit 21 according to the packet number of the next process written in the destination field 26 of the packet.
Is supplied to the packet for the next processing of, and this packet is executed next. In other words, a number of packets having the data fields 28 and 29 arranged in the loop-shaped communication network 24 flow in a pipeline manner and are processed in parallel by the arithmetic processing unit 23.

By the way, in order to realize high-speed data matching in the pair data detection circuit 22, the applicant can densely access the matching memory in this circuit without expanding the bit width of the data line, as shown in FIG. Recently, a pair data detection circuit 22 has been proposed (Japanese Patent Application No. 62-265737).
issue). The paired data detection circuit 22 includes a matching memory 6 for storing the packet data at an address corresponding to the packet number and the matching memory 6 for the packet number of the packet input from the input ports A and B.
Memory reading units 2a and 2b for reading packet data from the address of the above, and comparison determination units 3a and 3b for comparing the read packet data with the data of the input packet to determine the relationship between the two data, Part 3a,
Data processing units 4a and 4b for processing the input packet data and the read packet data based on the comparison result of 3b, and the data processed by the data processing units 4a and 4b corresponding to the packet number. Write to address of matching memory 6 or output port A, B
And the memory writing units 5a and 5b for outputting via the data transmission lines 1a and 1b are connected in a loop shape, and the memory access control circuit 7 controls the competition of access to the matching memory 6 so that the input port A, The packet data input in parallel from B is subjected to pipeline processing and high-speed template matching is performed.

Therefore, for example, when a packet in which the operand is written in the data 1 field 28 of FIG. 6 enters from the input port A, the memory reading unit 2a retrieves the packet data from the address of the matching memory 6 corresponding to the packet number. read out. Then, when the operand of the data 2 field 29 forming a pair is read, this packet is output to the output port A by the memory writing unit 5a as a packet in which both operands are complete through the comparison / determination unit 3a and the data processing unit 4a. At the same time, the data of the address in the matching memory 6 is cleared. On the other hand, if the operand of the paired data 2 field 29 is not read, the packet data of the input packet is
The memory writing unit 5a waits for data to be written to the corresponding address of the matching memory 6 via a similar path and to be paired.

<Problems to be Solved by the Invention> The pair data detection circuit 22 is used for aligning pair data (pair operands) of packets necessary for the calculation in the calculation processing section 23 as described above. It is also used to confirm that both processes are completed. In this case, since the paired data detection circuit 22 detects the coincidence of the destination fields of the two data, when the processing of A and B shown in FIG. (See FIG. 6) is set to the same #i, a sync code SYNC is provided in the instruction field 27, and a sync instruction packet including data having no meaning in the data 1 and 2 fields 28 and 29 is output respectively, and the C and D When the processing is completed, the same synchronization command packet with the destination field 26 set to the same #j is output. Then, when A, B or C, D is synchronized by the paired data detection circuit 22, each synchronization command packet reaches the program storage unit 21 through the communication network 24, and then the destination field is transferred from the program storage unit 21. The i-th synchronization instruction packet or the j-th synchronization instruction packet having the same #k is transmitted. Furthermore, the synchronization of both synchronization command packets is #k in FIG.
When the paired data detection circuit 22 receives the synchronization instruction packet, the synchronization instruction packet goes around the communication network 24, and a packet SIG indicating that the four processes A, B, C and D have been completed is sent from the program storage unit 21. It

However, in the synchronization confirmation process by the paired data detection circuit 22, as shown in FIG. 7, four processes A, B, C, D are performed.
3 synchronization commands (SYNC) are required to synchronize the two, and at least twice, that is, two pipeline cycles are required around the communication network 24. Generalized,
To synchronize the n processes, n-1 synchronization instructions are required, and log ₂ n stages of pipeline cycles are required. Therefore, the larger the number of processes to be synchronized, the more the processing time is drastically increased due to the sending of a large number of synchronization instructions and the multi-stage pipeline cycle, and the processing speed cannot be increased.

Therefore, an object of the present invention is to use the previously unused data field portion of the synchronization command packet as a flag to synchronize three or more processes at a time,
An object of the present invention is to provide a pair-to-data detection circuit that can realize high-speed synchronization processing in a data flow computer.

<Means for Solving the Problems> In order to achieve the above-mentioned object, the paired data detection circuit of the present invention includes a matching memory, a memory reading unit, a comparison determination unit, a data processing unit, and a memory writing unit in a loop in a data transmission path. , Which controls the contention of access to the matching memory, pipelines the packet data input in parallel, and performs high-speed template matching, and has three instruction fields of the packet input from the input port. While determining whether or not it is a synchronization instruction for synchronizing the above processing, when it is determined to be affirmative, the normal processing of the data processing unit is stopped and a synchronization instruction signal is output, while it is determined to be no. At this time, the instruction determination unit that causes the data processing unit to continue normal processing, and the input packet and memory reading Each process described in a predetermined data field of the packet data read by the output unit and to be synchronized is indicated by a unique flag position in a flag consisting of a fixed number of bits.
A logical sum of the decimal numbers is calculated by receiving the synchronous command signal from the command determination unit, the calculated logical sum is written in a predetermined data field of the input packet, and all bits of the calculated logical sum are flagged. When the packet is output from the output port via the memory writing unit and the packet data of the address of the matching memory is erased, while any bit of the calculated logical sums is not flagged , And a data field logical sum section for writing the packet to the address of the matching memory via the memory writing section.

<Operation> When the packet input from the input port is a synchronization command, the command determination unit determines that the result is affirmative, stops the normal processing of the data processing unit, and outputs a synchronization command signal. The data field OR section receives the synchronization command signal, and is described in a predetermined data field of the input packet and the packet data read from the corresponding address of the matching memory by the memory reading section.
Calculates the logical sum of base numbers. Since the above binary number indicates each process to be synchronized by the unique flag position in the flag consisting of a fixed number of bits, the bit position corresponding to the completed process in the calculated logical sum is sequentially added. The flag stands. The data field logical sum unit writes this logical sum in a predetermined data field of the input packet. When all the bits of the calculated logical sum are flagged, it is determined that all the processes are synchronized, and the packet is output from the output port via the memory writing unit, and the packet data of the address of the matching memory is output. Erase. On the other hand, when any of the bits of the calculated logical sum is not flagged, it is determined that there is unsynchronized processing, and the packet data of the packet is written to the address of the matching memory via the memory writing unit.

On the other hand, when the packet input from the input port is not the synchronization instruction, the instruction determination unit determines NO and continues the normal processing of the data processing unit, and the input packet is paired as in the conventional example. Is output from the output port when all data (operands) are complete.

<Examples> Hereinafter, the present invention will be described in detail with reference to illustrated examples.

FIG. 1 is a block diagram showing an upper half of an embodiment of a paired data detection circuit of the present invention. 1a is a data transmission line, 2a is a memory reading section, 3a is a comparison / determination section, 4a is a data processing section, 5a. Is a memory writing unit, 6 is a matching memory, and 7 is a memory access control circuit. Since these units have the same configurations and operations as those of the conventional example described in FIG. 8, the same units are designated by the same reference numerals. And the description is omitted. Further, the lower half (not shown) of the pair data detection circuit 11 is
The matching memory 6 and the memory access control circuit 7 having an input port B and an output port B are symmetrical to the upper half.

In FIG. 1, the instruction determining unit 8a indicates that the instruction field 17 (see FIG. 3) of the packet input from the input port A through the memory reading unit 2a has a synchronous instruction (SYNC).
Or not. When it is determined that it is a synchronous command, the output of the normal command signal A to the data processing unit 4a is stopped to stop the normal processing, and the synchronous command signal A is output to the data field OR unit 9a described later. To do. On the other hand, when it is determined that it is not the synchronous command, the output of the synchronous command signal A is stopped, and the normal command signal A is output to the data processing unit 4a to continue the normal process similar to the conventional example.

On the other hand, the data field logical sum unit 9a includes a packet and memory reading unit 2 input from the input port A.
The instruction determination unit 8 calculates the logical sum of binary numbers representing the end processing display flags described in the data 1 field 18 (see FIG. 3) of the packet data read by a.
It is calculated by receiving the synchronization command signal A from a. 2 above
The radix indicates the completed process by the only flag position corresponding to that process in the flag consisting of the same number of bits as the number of processes to be synchronized. For example, the processes to be synchronized are A and B. , C, D (see FIG. 2), the lower 4 digits of the data 1 field 18 of the synchronization command packet 15 are set to “0” as shown in FIG. The flag "1" is set to the second lower digit and the remaining upper digits are masked with "1". The bit position where the flag "1" is set is shown in Fig. 4 (a).
As shown in (4), if the processing is A, the lower 4th digit, B, the lower 3rd digit, and D, the lower 1st digit. Therefore, the flag "1" is sequentially set at the bit position corresponding to the ending process of the calculated binary number that is the logical sum. The data field logical sum unit 9a writes the calculated logical sum in the data 1 field 18 of the input packet. When all the bits of the logical sum are flagged as shown in FIG. 4 (b), the packet is output from the output port A via the memory writing unit 5a, and the corresponding address of the matching memory 6 is output. Delete the packet data of. On the other hand, when no flag is set in any bit of the logical sum, the packet data of the packet is written to the address of the matching memory 6 via the memory writing unit 5a, and the packet disappearance signal A is sent to the packet disappearance unit 10a. Is output to eliminate the unsynchronized packet and not output from the output port A.

The operation of the paired data detection circuit 11 having the above configuration will be described below.

When the packet input from the input port A is a synchronization command as shown in FIG. 3, the command determination unit 8a determines that it is a synchronization command, stops the normal command signal A, and stops the normal processing of the data processing unit 4a. And the data field logical sum unit 9a
The sync command signal A is output to. Then, the data field logical sum unit 9a logically sums the input packet and the binary numbers described in the data 1 field 18 of the packet data read from the corresponding address of the matching memory 6 by the memory reading unit 2a. And the calculation result as the data 1 field 18 of the above packet.
Write in. When all the processes A, B, C and D to be synchronized are completed, the flag "1" is set in all the bits of the data 1 field 18, so that the data field OR unit 9
The a outputs the packet from the output port A via the memory writing unit 5a and erases the packet data of the address in the matching memory 6. On the other hand, if any of the processes A, B, C and D to be synchronized is not completed, "0" in which the flag is not set in the data 1 field 18 is set.
Data field OR section 9a
Writes the packet to the address of the matching memory 6 via the memory writing unit 5a and sends a packet disappearance signal A to the packet disappearance unit 10a to prevent the output port A from outputting the packet.

On the other hand, when the packet input from the input port A is a normal operation packet as shown in FIG. 6, the instruction determination unit 8a
Determines that it is not a synchronization command, sends a normal command signal A to continue the normal processing of the data processing unit 4a, and the input packet has a pair of data (operand) as in the conventional example. When the data 18 and the data 2 field 19 are complete, the data is output from the output port A.

As described above, in the above embodiment, the data 1 field portion of the synchronization command packet, which has not been used conventionally, is used as a flag to synchronize four packets (processing A, B, C, D) with each other as shown in FIG. ), The input port A,
The synchronization command packet input from B (not shown) can be confirmed at high speed whether or not the packet data portion of the matching memory 6 is used as a work area, and the synchronization processing can be significantly speeded up. As another synchronization process, a method of using the data 1 field 18 as a count and completing the synchronization when the waiting number of data arrives can be considered, but in this method, two or more data come from the same process. Sometimes there is a drawback that the synchronization is completed by mistake. In contrast,
In the method of the present invention, each process to be synchronized is distinguished by the bit position. Therefore, by adding a mechanism that causes an error when "1" comes to a bit that has already been flagged, the above malfunction is prevented. Can be eliminated. When a bit already flagged is "1", the packet is output from the output port without being processed as an error and the current set of synchronization is completed. It is also possible to synchronize the same data (A, B, C, D in this example) multiple times by circulating the program storage section → pair data detection circuit → arithmetic processing section until is erased. Is.

In the above embodiment, the case where the flag of the data 1 field 18 is 4 bits and four processes are synchronized has been described. However, if the entire bit width of the data 1 field is used as a flag, a larger number of processes are synchronized. be able to. In the embodiment, the flag is represented by "1" in "0", but it can be represented by "0" in "1". Further, it goes without saying that the present invention is not limited to the illustrated embodiment.

<Effects of the Invention> As is apparent from the above description, in the paired data detection circuit of the present invention, the matching memory, the memory reading unit, the comparison / determination unit, the data processing unit, and the memory writing unit are connected in a loop in the data transmission path. However, when performing pipeline processing on packet data input in parallel and performing high-speed template matching, it is instructed whether the instruction field of the input packet is a synchronization instruction for synchronizing three or more processings. If the judgment unit judges that it is affirmative, it outputs a synchronization command signal to the data field logical sum unit, and this data field logical sum unit reads the input packet and the corresponding address of the matching memory by the memory reading unit. A binary number representing the end processing display flag described in a predetermined data field of the issued packet data. When the logical sum is obtained, the result is written in a predetermined data field of the input packet, and when all the bits of the logical sum are flagged, the packet is output from the output port via the memory writing unit and matching is performed. When the packet data of the corresponding address of the memory is erased, and when any bit of the logical sum is not flagged, it is determined that the packet is written to the corresponding address of the matching memory through the memory writing unit Since the data processing unit is made to continue the same normal processing as the conventional one, a large number (three or more) of synchronous instruction packets can be synchronized at one time in one pipeline cycle, and reliable synchronous processing can be performed conventionally. It can be performed much faster than the example, and it greatly contributes to speeding up the operation of the data flow computer.

[Brief description of drawings]

FIG. 1 is a block diagram showing an upper half of an embodiment of a paired data detection circuit of the present invention, FIG. 2 is a diagram showing an execution method of a synchronization instruction of the above embodiment, and FIG. 3 is a synchronization instruction of the above embodiment. FIG. 4 is a diagram showing a packet configuration, FIGS. 4 (a) and 4 (b) are diagrams for explaining the end processing display flag of the synchronous command packet, and FIG. 5 is a diagram showing a general configuration of a data flow computer, FIG. Is a diagram showing the structure of a general packet, FIG. 7 is a diagram showing a conventional method of executing a synchronization instruction, and FIG. 8 is a block diagram showing a conventional paired data detection circuit. 1a ... Data transmission path, 2a ... Memory reading section, 3a ... Comparison determination section, 4a ... Data processing section, 5a ... Memory writing section, 6 ... Matching memory, 7 ... Memory access control circuit, 8a ... Instruction determination section, 9a ... Data field OR section, 10a ... Packet erasing section, 11 ... Pair data detection circuit.

Claims (1)

[Claims] 1. A matching memory for storing the packet data at an address corresponding to the packet number, and a memory reading section for reading the packet data from the address of the matching memory corresponding to the packet number of the packet input from the input port. A comparison determination unit that compares the read packet data and the input packet data to determine the relationship between the two data, and the input packet data that was read based on the comparison result of this comparison determination unit A data processing unit that processes packet data and a memory writing unit that writes the data processed by the data processing unit to the address of the matching memory corresponding to the packet number or outputs the data via an output port are looped in a data transmission line. In the same manner, and conflicting access to the above matching memory In the paired data detection circuit for performing pipeline processing on packet data input in parallel and performing high-speed template matching, the instruction field of the packet input from the input port is used to synchronize processing of three or more. While determining whether it is a synchronization command, when it is determined to be affirmative, the normal processing of the data processing unit is stopped and a synchronization command signal is output, while when it is determined to be absent, normal processing is performed to the data processing unit. The command determination unit for continuing the above, and the specified packet and the predetermined data field of the packet data read by the memory reading unit, respectively, describe each process to be synchronized. The logical sum of the binary numbers indicated by the flag positions is calculated by receiving the synchronization command signal from the command determination unit. While writing the calculated logical sum in a predetermined data field of the input packet, and when all bits of the calculated logical sum are flagged, the packet is output from the output port via the memory writing unit,
And, while the packet data of the address of the matching memory is erased, when any bit of the calculated logical sum is not flagged, the packet is written to the address of the matching memory via the memory writing unit. A pair data detection circuit comprising a data field logical sum unit.