JPH0650343B2 - Target maximum distance detection circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for detecting the maximum amplitude within a range resolution of radar video.

[0002]

2. Description of the Related Art If the range resolution of a radar is R and the unit of range quantization is r, and the natural number immediately below R / r is k, the maximum amplitude detection in the range of range of the conventional range resolution R is: This is performed by using k registers, k comparators, and k selectors.

FIG. 3 is a diagram showing the configuration of a conventional maximum amplitude detection circuit when k = 5. Since k = 5, the distance in which five distance quantization units are consecutive is the distance resolution. The circuit is roughly divided into three groups. The first is the register 11 to the register 15.
Is a shift register connected in cascade.

In this system, radar video in the resolution distance range is stored for each distance quantization unit, and is sequentially shifted to the right by a distance quantization clock at each time corresponding to the distance quantization unit. The video 1 input to the register 11 is the input radar video, the output of the register 11 is video 2, the output of the register 12 is video 3, the register 1
3 output is video 4, register 14 output is video 5,
The output of register 15 is video 6. The second group is a group including the selectors 21 to 25, and the third group is a group including the comparators 31 to 35.

Video 1 and video 2 are input to the comparator 31, the magnitudes of the amplitudes are compared, and a comparison signal S ₁ indicating which is larger is output. The comparison signal S ₁ is selected by the selector 21.
Added to. Video 1 and video 2 are also input to the selector 21, and the one with the larger amplitude is output according to the comparison signal S ₁ .

Video 3 and video 4 are added to the selector 22 and the comparator 32, and the selector 22 outputs the larger amplitude of video 3 and video 4 according to the comparison signal S ₂ from the comparator 32. . Video 5 for selector 23 and comparator 33
And the video 6 are input, and the selector 23 is the comparator 33.
Of the video 5 and the video 6 having the larger amplitude are output according to the comparison signal S ₃ from.

Video 7 which is the output of the selector 21 and video 8 which is the output of the selector 22 are sent to the selector 24 and the comparator 34.
, And the selector 24 outputs the larger amplitude of the video 7 and the video 8 according to the comparison signal S ₄ from the comparator 34. Selector 2 for selector 25 and comparator 35
The video 10 which is the output of 4 and the video 9 which is the output of the selector 23 are input, and the selector 25 outputs the larger one of the video 10 and the video 9 according to the comparison signal S ₅ from the comparator 35. . Thus, the output of the selector 25 is the maximum amplitude of the video 1 to video 6.

[0008]

However, as is apparent from the above configuration, in the conventional technique, the number of registers, selectors, and comparators required is k, which is determined by the ratio of the distance resolution and the distance quantization unit. Is large and complicated.

In view of the above-mentioned problems of the prior art, the object of the present invention is k determined by the distance resolution and the distance quantization unit.
SUMMARY OF THE INVENTION It is an object of the present invention to provide a distance direction maximum amplitude detection circuit having a simple configuration including one selector, one comparator, two registers, and one status update circuit without depending on the value of.

[0010]

The present invention has the following means for achieving the above object. That is, the target maximum distance direction amplitude detection circuit of the present invention comprises a first register for holding a video signal having amplitude information; an amplitude of an input radar video and an amplitude of a held video held in the first register. A comparator that compares the distance quantization units and outputs a signal A indicating that the held video amplitude is greater than or equal to the input radar video amplitude or a signal B indicating that when the held video amplitude is less than the input radar video amplitude; When the output signal of the comparator is received, the signal C indicating that is output only when the output signal is the signal A continuously for a preset number of times, and when the output of the comparator is the signal B and the signal A is set. A status update circuit for returning to the initial state when the number of times is exceeded; the holding video held in the first register and the input radar video are input, and the output of the comparator is the signal A and the status is The holding video is selected when the output of the update circuit is not the signal C, the input radar video is selected when the output of the comparator is the signal B and the output of the status update circuit is not the signal C, and the output of the status update circuit is selected. When the signal is C, a selector that selects the input radar video regardless of the output of the comparator and outputs it to the first register respectively; and when the output of the status update circuit is the signal C, the held video of the first register is displayed. A second register which receives, holds and outputs this;
Is a target maximum distance direction amplitude detection circuit.

[0011]

The operation of the above means configuration is as follows. Now, if the amplitude of the input radar video is larger than the amplitude of the holding video held in the first register, the comparator outputs the signal B, and the status updating circuit continuously outputs the signal A for the preset number of times. The signal C is not output because it is not in such a state. Therefore, the selector has been added 2
The input radar video is selected from the two videos and sent to the first register to update the held video in the first register.

On the other hand, if the amplitude of the input radar video is equal to or smaller than the amplitude of the holding video held in the first register, the comparator outputs the signal A and sends the signal A to the status updating circuit. To do. At this time, the status update circuit does not output the signal C unless the number of times the signal A is output has reached the preset number of consecutive times. Therefore, the selector selects the holding video from the first register of the two added videos and outputs it to the first register.

Eventually, the first register is updated with the video held one distance quantization unit time before, and as a result, the held video does not change. The status update circuit outputs the signal C when the number of times the signal A is output has just reached a preset number. Therefore, even if the output of the comparator is the signal A, the selector selects the input radar video and sends it to the first register, and the first register is updated by the input radar video and at the same time holds it. The held video that has been held is moved to the second register and held and is ready for output.

By the way, assuming that the preset number of times is a natural number k which is the next highest rank of (distance resolution R) / (distance quantization unit r), the circuit of the present invention performs a certain distance quantization by the above operation. If the video amplitude of the distance quantization unit that follows is smaller than the video amplitude in the unit k times consecutively, that is, if the signal A is output k times consecutively, the amplitude in the certain distance quantization unit becomes the range resolution range. It means that the maximum amplitude is.

If the number of appearances of the signal A does not reach k times and the signal B appears at the k'th time (k '<k), it is held in the first register before the distance of the distance resolution is reached. The first retained video was not maximal in range of range resolution, since the incoming radar video had an amplitude greater than that of the recorded video, and the retained video was updated from there It will be ascertained whether the retained video is maximal in the range of range resolution.

When the signal A does not appear and only the signal B appears continuously, the amplitude of the input radar video increases successively, and the hold video also updates to the larger one.
This means that a radar video larger than that comes in, and in reality, such a case cannot occur.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. The lower case alphabet with parentheses in the figure is
It corresponds to that. Reference numeral 41 denotes a register, which corresponds to the first register referred to in the solving means. 42 is a comparator, 4
3 is a status update circuit, 44 is a selector, and 45 is a register which is a second register referred to as a solution means. 46 is AN
The D gate and 47 are inverters. The input radar video and the held video from the register 41 are input to the selector 44 and the comparator 42. The output of the selector 44 is connected to the register 41, and the content held in the register 41 is updated to the output of the selector 44 by the distance quantization clock.

The output of the register 41 is sent to the selector 44 and the register 45. The output of the comparator 42 is sent to the status update circuit 43 and is ANDed.
It is applied to one input of gate 46. The output of the status update circuit 43 is applied to the register 45 and the other input terminal of the AND gate 46 via the inverter 47. The comparator 42 outputs a logic 0 (corresponding to the signal B referred to as a solution means, hereinafter referred to as “0”) when the input radar video amplitude is larger than the held video amplitude, and the input radar video amplitude is equal to or smaller than the held video amplitude. In this case, logic 1 (corresponds to the signal A referred to as the solution means, hereinafter referred to as "1")
Is output.

The status update circuit 43 outputs "1" only when "1" is continuously input a preset number of times from the initial state. That is, when "0" is input to the initial state, the output is "0" in the initial state as it is, and even if "1" is continuously input, "0" is output before reaching the preset number. When "" is input, the state returns to the initial state and the output is "0". Further, after "1" is input a predetermined number of times in succession, the initial state is returned and the output becomes "0" regardless of whether the input is "1" or "0". Such a circuit is a kind of counting circuit and can be realized by a simple circuit. When “1” is input as the selection signal, the selector 44 selects and outputs the held video,
When "0" is input, the input radar video is selected and output.

Now, the preset number of times is k = 6, that is,
An operation example for an input radar video will be described with reference to FIG. 2 as an example in which a distance resolution unit is approximately six times the distance quantization unit. (A) is a distance quantization clock, and updating of the register 41 and state transition of the status updating circuit 43 are performed in synchronization with this clock.

(B) is a waveform of the input radar video,
(C) is the amplitude value sampled by the distance quantization clock. (D) shows the video held in the register 41. (E) is the output of the comparator (c)>
When (d) is “0”, when (c) ≦ (d) is “1”
Becomes (F) is the status update circuit output,
"1" only when (e) outputs "1" 6 times in succession
Is output. (G) is the output of the selector, and (c) and (d)
The one with the larger amplitude is output, and this is updated and held in the register 41 of (d) with a delay of one clock. (H) is a video held in the register 45, and when the output of the status update circuit in (f) becomes "1", the video held in the register 41 in (d) is shifted.

Now, assuming that the video amplitude held in the register 41 of (d) is 0 at _first, when the input radar video amplitude value A _{1 of} (c) is input, A ₁ > 0, so the video of (e) is input. The output of the comparator is "0", and the output of the status update circuit in (f) is also "0", which is inverted by the inverter 47 and becomes "1", which is added to the AND gate 46.
The output of the gate 46 becomes "0", and the output of the selector (g) becomes the input radar video A ₁ , which is held in the register 41 at the next clock.

Next, it is compared with the input radar video A ₂ , but since A ₂ > A ₁ from the waveform diagram, (e) becomes “0” and (f) also becomes “0”, so (g) shows A _2. And is held in the register 41 at the next clock. Then, it is compared with the input radar video A ₃ , but from the waveform diagram, A ₂ >
Since it is A ₃ , (e) is "1", and (f) is "0", but it is inverted by the inverter 47 and becomes "1". AN
The output of the D gate becomes "1", (g) is A _2, and the
This updates the register 41 at the next clock, but since it is the same A ₂ as before the update, the held content does not change.

Since the subsequent input radar video up to A ₄ , A ₅ , A ₆ , A ₇ , and A ₈ is smaller than A ₂ , the same operation as in A ₃ is performed. As a result, since "1" appears 6 times in succession in the comparator output of (e), "1" appears in the status update circuit output of (f) at the next clock. Since it is inverted and "0" is input to the AND gate 46, AND
The output (selection signal) of the gate becomes "0", and the selector selects and outputs the input radar video A ₉ at that time, and it is held in the register 41 at the next clock.

At the same time, the video A ₂ held by the register 41 is
It is shifted to the register 45 which receives the output of the status update circuit and is held and output as the maximum amplitude value. The following input radar video A ₁₀ is stored in the register 41
_Since A ₁₀ > A ₉ is compared with ₉ , (e) becomes “0” and (g) becomes A ₁₀ , which is held in the register 41. The same operation will be continued thereafter.

As described above, in the present embodiment, when the amplitude of each input radar video amplitude becomes smaller in each successive 6 units of distance quantization, the first input radar video becomes smaller. The amplitude can be detected as the maximum amplitude video in the range resolution range.

[0027]

As described above, the target maximum distance-direction amplitude detection circuit of the present invention is mainly composed of two registers, one selector, one comparator and one status. It is composed of only the update circuit, and the number k determined by the distance resolution and the distance quantization unit can be set only by changing the number of bits of the status update circuit, which is a simple counting circuit, and the update table. In comparison with the case where k registers, selectors, and comparators have to be provided for each, there is an advantage that the setting and changing of k can be performed very easily with a very simple configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional target maximum amplitude detection circuit in the distance direction.

[Explanation of symbols]

 11 register 12 register 13 register 14 register 15 register 21 selector 22 selector 23 selector 24 selector 25 selector 31 comparator 32 comparator 33 comparator 34 comparator 35 comparator 41 register 42 comparator 43 status update circuit 44 Selector 45 Register 46 AND gate 47 Inverter

Claims (1)

[Claims] 1. A first register for holding a video signal having amplitude information; an amplitude of an input radar video and an amplitude of a held video held in the first register are compared for each distance quantization unit and held. A comparator that outputs a signal A indicating that the video amplitude is greater than or equal to the input radar video amplitude, or a signal B indicating that when the video amplitude is less than the input radar video amplitude; Output the signal C indicating that the signal A has been output continuously for a preset number of times, and the comparator output outputs the signal B.
And a status update circuit that returns to the initial state when the signal A exceeds the set number of times; the holding video held in the first register and the input radar video are input, and the output of the comparator is the signal A and When the output of the status update circuit is not the signal C, the holding video is selected. When the output of the comparator is the signal B and the output of the status update circuit is not the signal C, the input radar video is selected and the output of the status update circuit is selected. When the signal is C, a selector that selects the input radar video regardless of the output of the comparator and outputs it to the first register respectively; and when the output of the status update circuit is the signal C, the held video of the first register is displayed. A second register for receiving, holding and outputting the same; and a target maximum distance direction amplitude detection circuit.