JPH0646705B2 - Low power CMOS integrated circuit - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a CMOS circuit, and more particularly to a circuit suitable for low power consumption.

[Background of the Invention]

A circuit diagram of a conventional CMOS inverter is shown in FIG.
The static characteristics are shown in FIG. The disadvantage of this circuit is that when the power V _in of the input φ _{in is} between the power supply voltage V _CC and 0, a steady current flows, resulting in high power consumption. That is, the threshold voltage of the p-channel MOS transistor 3 is set to V _TP (V _TP <0), the n-channel MO transistor
When the threshold voltage of the S-transistor 4 is V _TN (V _TN > 0), when V _TN <V _in <V _CC − | V _TP | An electric current flows. This state is shown in FIG. This becomes a particular problem when this circuit is backed up by a power source having a small capacity such as a battery.

[Object of the Invention]

It is an object of the present invention to provide a means for preventing the above-mentioned through current from flowing during backup and reducing the load of the backup power supply.

[Outline of Invention]

In order to prevent the shoot-through current, the threshold voltage V _TN of the n-channel MOS transistor may be increased and the threshold voltage V _TP of the p-channel MOS transistor may be decreased (that is, the absolute value may be increased). In particular, if V _TN -V _TP > V _CC (2), no through current will flow. However, this causes a problem that the transfer conductance of the MOS transistor becomes smaller and the speed becomes slower. Therefore, in normal times, the MOS transistor operates like a conventional CMOS circuit.
It suffices that the condition (2) be met only during backup. Of course, if this is done, the speed will be slower, but in general, high speed operation is often not necessary at the time of backup. For example, a dynamic RAM requires a high-speed operation with a cycle time of about 300 ns for normal access, but a cycle time of about 16 .mu.s is required for back-up because only refreshing is required.

Example of Invention

FIG. 2 (a) shows a circuit diagram of an embodiment of the present invention. This embodiment comprises a CMOS inverter composed of an enhancement type p-channel MOS transistor 3 and an enhancement type n-channel MOS transistor 4, two power supplies 1 and 2 for driving it, and a switching switch 5. In normal times, the inverter is driven by the first power supply 1, and between the output power V _{1 of 1} and the threshold voltages V _TP and V _TN of the MOS transistors 3 and 4, V _TN −V _TP <| The relationship of V ₁ | ... (3) is established. The static characteristics of the inverter at this time are the same as those of the conventional CMOS inverter, as shown in FIG.

When the first power supply becomes unavailable, the switching switch 5 automatically operates to supply current from the second power supply 2 for backup. The output voltage V _{2 of} this second power supply _{2
V 2 |} | the V _{TN -V} TP> to be lower than V ₁ by setting so that ... _(4), the static characteristics of the inverter at this time is as shown in FIG. (C) Become. In other words, they follow different paths when descends when the voltage V _in of the input terminal rises, becomes the characteristic having a so-called hysteresis, no particular trouble in operation as an inverter.
The p-channel MOS transistor 3 has 0 ≦ V _in ≦ V ₂ −
Only when | V _TP | becomes conductive, and n channel M
The OS transistor 4 becomes conductive only when V _TN ≤V _in ≤V ₂ . Therefore, V ₂ − | V _TP | <V
_{When in} <V _TN , both 3 and 4 are in a non-conducting state, so that a through current does not flow.

In this _{way, V TN -V TP> | V} 2 | in the conditions, CM
The static characteristics of the OS inverter exhibit hysteresis because of the following reasons.

That is, when the voltage of the input φin is 0 volt, the p-channel MOS transistor (3) is on and the n-channel MOS transistor (3) is on.
The transistor (4) is off and the output φout is equal to the voltage V ₂ of the second power supply 2.

When the voltage of the input φin rises, the voltage of the input φin becomes V ₂
When −│V _TP │ is reached, the p-channel MOS transistor (3) is turned off, and the output φout is in a high impedance floating state, but the stray capacitance (not shown) of the output out has a second value. The voltage V _{2 of the} power supply 2 remains charged. Furthermore, when the voltage of the input φin rises and reaches the threshold value | V _TN | of the N-channel MOS transistor (4), the N-channel MOS transistor (4) is turned on, and the stray capacitance of the output φout is discharged to 0 Become a bolt.

When the voltage of the input φin drops from this state, the N-channel MOS transistor (4) is turned off when the threshold value V _TN of the N-channel MOS transistor (4) is reached first.
The output φout is in a high impedance floating state, but the stray capacitance of the output φout remains discharged to 0 volts. Furthermore, the voltage at the input φin drops, and the input φin
When the voltage of in becomes lower than V ₂ − | V _TP |, the p-channel MOS transistor (3) is turned on, and the stray capacitance of the output φout is charged to the voltage V ₂ of the second power supply 2. That is, the voltage of the input φin is lower than V ₂ − | V _TP |
If higher than _TN , p-channel MOS transistor
Both (3) and the N-channel MOS transistor (4) are turned off, and the stray capacitance of the output φout maintains the previous state. Therefore, the static characteristics of the input and output of the CMOS inverter show a sterilization as shown in FIG.

A normal operation mode / back up mode switching signal for controlling the switching switch 5 for switching between the first power source 1 and the second power source 2 is applied from the outside of the integrated circuit, and, for example, this switching signal is at a high level. In the case of, the switching switch 5 is connected to the side of the first power supply 1 and the voltage V ₁ is supplied, and when the switching signal is at the low level, the switching switch 5 is connected to the side of the second power supply 2 and the voltage V ₁ is supplied. ₂ can be supplied.

In addition, the voltage V ₁ of the _first power supply 1 and the voltage V ₁ of the second power supply 2
₂ is provided with a voltage comparator, and when the voltage V ₁ of the first power supply 1 for normal operation is higher than the voltage V ₂ of the second power supply 2 for backup, the high level output of the voltage comparator supplying voltages V ₁ and connecting the changeover switch 5 to the first side of the power supply 1, the voltage V ₁ of the first power supply 1 for the normal operation
Is lower than the voltage V ₂ of the second power supply 2 for backup, it is also possible to supply the voltage V ₂ by connecting the switching switch 5 to the side of the second power supply 2 by the low level output of the voltage comparator. Is.

In this embodiment, in order to satisfy the conditions (3) and (4),
In consideration of manufacturing variations and operating margin, V ₂ is V
_It should be much lower than ₁ . If a power supply satisfying this condition cannot be obtained as a backup power supply, for example, as shown in FIG. This embodiment uses V ₂ ′
Power supply 2'having an output voltage of
The voltage is stepped down by the S-transistor group 7 so that the voltage V ₂ at the output (point A) satisfies the conditions of the above equations (3) and (4). The number of MOS transistors included in the MOS transistor group 7 is n (n = 2 in the figure), and its threshold voltage is V
if _r, the _{V 2 = V 2 '-nV r} ...... (5). In addition to this, the method shown in FIG. In this method, the depletion type M
If the threshold voltage of the OS transistor 8 is V _TD (V _TD <0), then V ₂ = | V _TD | ... (6)

FIG. 5 shows another embodiment of the present invention. In this embodiment, the bias voltage is applied to the substrates of the MOS transistors 3 and 4 at the time of back-up to increase the absolute value of the threshold voltage so that the conditions of the above expressions (3) and (4) are satisfied. Is. Three switching switches 5, 11, 12
Are interlocked with each other, and in normal times, they are all connected to the one shown in the figure. Therefore, the CMOS inverter is driven by the first power supply 1, and the MOS transistor 3,
4 has never had a substrate bias. At this time, the threshold voltage _{V TP1,} V of the output voltages _{V 1} and 3, 4 of the power supply 1
Between the _{TN1, V TN1 -V TP1 <|} V 1 | and relationships ... (7) is satisfied, the static characteristics of the inverter as shown in FIG. (B), as with conventional CMOS inverter Is.

When the first power supply 1 becomes unusable, the switching switches 5, 11, 12 are automatically connected to the opposite sides. The CMOS inverter is connected to the second power supply 2 for back-up, and the MOS transistors 3 and 4 are biased by the power supplies 9 and 10, respectively.
Therefore, the threshold voltages V _TP2 , V of 3 and 4 at this time
_TN2 are values V _TP1 and V in normal times, respectively.
_The absolute value is larger than _TN1 . That is, V _TP2 <V _TP1 <0 (8) V _TN2 > V _TN1 > 0 (9). And V _{TP2, V TN 2,} between the output voltage _{V 2} of the second power supply _{2, V TN2 -V TP2 <|} V 2 | by setting as ... (10) the relationship is established, the inverter The static characteristics are as shown in FIG. 7C, and no through current flows.

This embodiment has an advantage that V ₁ and V ₂ may be substantially the same value as long as the change in the threshold voltage of the MOS transistor due to the substrate bias is sufficiently large.

It should be noted that although all of the embodiments described above describe one CMOS inverter, the present invention applies not only to the inverter but also to other CMOS logic circuits such as NAND gates and NOR gates, or a circuit combining them. Applicable to

〔The invention's effect〕

As described above, according to the present invention, the through current of the CMOS circuit can be completely prevented at the time of back-up, and the load on the back-up power supply can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a conventional CMOS inverter and a diagram showing its static characteristics, and FIGS. 2 to 5 are explanatory diagrams of a CMOS inverter according to the present invention. 1, 2, 2 ', 9, 10 ... power supply, 3 ... p-channel M
OS transistor, 4 ... N-channel MOS transistor, 5, 11, 12 ... Switch, 6 ... Capacitor,
7 ... Enhancement type n-channel MOS transistor group, 8 ... Depletion type n-channel MOS transistor.

Front page continuation (72) Inventor Yoshinobu Nakagome 1-280 Higashi Koigakubo, Kokubunji, Tokyo Inside Hitachi Central Research Laboratory (72) Inventor Shinichi Ikenaga 1-280 Higashi Koigakubo, Kokubunji, Tokyo Hitachi Central Research Co., Ltd. In-house (56) Bibliographic references Sho 54-106869 (JP, U)

Claims (3)

[Claims] 1. A p-channel MO whose gate is commonly connected to an input terminal and whose drain is commonly connected to an output terminal.
A CMOS circuit having an S-transistor and an N-channel MOS transistor, and an operating voltage switch for switching between a _first operating voltage V ₁ for a normal operating state and a second operating voltage V ₂ for backup and supplying the CMOS circuit with the operating voltage. Supply means for supplying the first operating voltage V ₁ to the CMOS circuit by the operating voltage switching supplying means.
The threshold voltage V _TP1 of the channel MOS transistor, the threshold voltage V _TN1 of the N channel MOS transistor, and the first operating voltage V ₁ are established so that a relationship of V _TN1 −V _TP1 <| V ₁ | is established. The values of V _TN1 , V _TP1 , and V ₁ are set, respectively, and the p value when the second operating voltage V ₂ is supplied to the CMOS circuit by the operating voltage switching supply means.
Between the threshold voltage V _TP2 of the channel MOS transistor, the threshold voltage V _TN2 of the channel MOS transistor, and the second operating voltage V ₂ , the above V is established so that a relationship of V _TN2- V _TP2 > | V ₂ | is established. _{TN 2,} the _{V TP2,} low power CMOS integrated circuits, characterized in that the value of the _{V 2} is set respectively. 2. The above V _TP1 , V _TN1 , V _TP2 and V
Between _{TN2, V TP1>} low power CMOS integrated circuit according to paragraph 1 claims, wherein at least one holds the _{V TP2} and _V TN1 _{<V TN2.} 3. When the second operating voltage V ₂ is being supplied to the CMOS circuit by the operating voltage switching supply means, the CMOS circuit has an input voltage at the input terminal and an output voltage at the output terminal. The low power CMOS integrated circuit according to claim 1 or 2, wherein the low power CMOS integrated circuit exhibits a hysteresis characteristic.