JPS63171020U - - Google Patents
Info
- Publication number
- JPS63171020U JPS63171020U JP6289487U JP6289487U JPS63171020U JP S63171020 U JPS63171020 U JP S63171020U JP 6289487 U JP6289487 U JP 6289487U JP 6289487 U JP6289487 U JP 6289487U JP S63171020 U JPS63171020 U JP S63171020U
- Authority
- JP
- Japan
- Prior art keywords
- inverter
- voltage
- power supply
- mos
- constant current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000295 complement effect Effects 0.000 claims 1
- 238000010408 sweeping Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Logic Circuits (AREA)
- Amplifiers (AREA)
Description
第１図は本考案の第１実施例を示す回路図、第
２図及び第３図は本考案の第２及び第３実施例を
示す回路図、第４図は従来のＣ―ＭＯＳ形アンプ
を示す回路図、第５図はオペアンプを利用した従
来のアンプを示す回路図、第６図はＣ―ＭＯＳイ
ンバータの内部回路図、第７図は電源電圧を高く
設定した場合におけるＣ―ＭＯＳインバータの入
出力特性図、第８図は電源電圧をその動作可能最
低電圧と略等しくした場合におけるＣ―ＭＯＳイ
ンバータの入出力特性図である。
図面中、１１はインバータ、１２，１３はＭＯ
Ｓ―ＦＥＴ、１４は帰還抵抗（帰還用インピーダ
ンス素子）、１７は電源ライン、１８は定電流回
路である。
Fig. 1 is a circuit diagram showing the first embodiment of the present invention, Figs. 2 and 3 are circuit diagrams showing the second and third embodiments of the invention, and Fig. 4 is a conventional C-MOS type amplifier. Figure 5 is a circuit diagram showing a conventional amplifier using an operational amplifier, Figure 6 is an internal circuit diagram of a C-MOS inverter, and Figure 7 is a C-MOS inverter when the power supply voltage is set high. FIG. 8 is an input/output characteristic diagram of the C-MOS inverter when the power supply voltage is made approximately equal to the lowest operable voltage. In the drawing, 11 is an inverter, 12 and 13 are MO
14 is a feedback resistor (feedback impedance element), 17 is a power supply line, and 18 is a constant current circuit.
Claims (1)
したインバータの入出力間に掃還用インピーダン
ス素子を設けて構成したものにおいて、前記イン
バータの電源回路に定電流回路を設けて前記イン
バータへの印加電圧がその動作可能最低電圧と略
等しくなるようにしたことを特徴とするＣ―ＭＯ
Ｓ形アンプ。 In an inverter configured by connecting two MOS-FETs in a complementary manner, a sweeping impedance element is provided between the input and output of the inverter, and a constant current circuit is provided in the power supply circuit of the inverter to apply voltage to the inverter. A C-MO characterized in that the voltage is approximately equal to its lowest operable voltage.
S type amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6289487U JPS63171020U (en) | 1987-04-24 | 1987-04-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6289487U JPS63171020U (en) | 1987-04-24 | 1987-04-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63171020U true JPS63171020U (en) | 1988-11-08 |
Family
ID=30897612
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6289487U Pending JPS63171020U (en) | 1987-04-24 | 1987-04-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63171020U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5342654A (en) * | 1976-09-30 | 1978-04-18 | Toshiba Corp | Semiconductor device |
| JPS60167523A (en) * | 1984-02-10 | 1985-08-30 | Hitachi Ltd | Low power cmos integrated circuit |
-
1987
- 1987-04-24 JP JP6289487U patent/JPS63171020U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5342654A (en) * | 1976-09-30 | 1978-04-18 | Toshiba Corp | Semiconductor device |
| JPS60167523A (en) * | 1984-02-10 | 1985-08-30 | Hitachi Ltd | Low power cmos integrated circuit |