JPH0645940A - Digital/analog converter - Google Patents

Abstract

PURPOSE:To improve a differential non-linear error at a change point of a maximum weight bit due to the dispersion of resistance values and to improve the precision of analog output voltage. CONSTITUTION:Plural R-2R type resistor ladder circuit networks 21, 22 are connected in parallel with an analog output terminal VOUT. When the MSB of digital input signals 0SB (=LSB) to (n-1)SB (=MSB) is '0', the 0SB to (n-2)SB are impressed to one terminals of shunt resistors RA0 to RAn-2 through ORs 410 to 41n-2, and when the MSB is '1', power supply potential VDD is impressed to one terminals of all the shunt resistors RA0 to RAn-2 through the ORs 410 to 41n-2. When the MSB is '0', GND potential is impressed to one terminals of all shunt registers RB0 to RBn-2 through ANDs 420 to 42n-2, and when the MSB is '1', 0SB to (n-2)SB are impressed to one terminals of the RB0 to RBn-2 through the ANDs 420 to 42n-2. Consequently an analog signal is outputted from the VOUT.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention comprises an R-2R type resistor ladder network having a plurality of series resistors (series resistors) R and shunt resistors (shunt resistors), and converts a digital signal into an analog signal. The present invention relates to a digital / analog converter (hereinafter referred to as a D / A converter).

[0002]

2. Description of the Related Art Conventionally, as a D / A converter, a D / A converter using an R-2R type resistor ladder circuit having a plurality of series resistors R and a shunt resistor 2R and a D / A converter using a weighting type circuit are used. / A converter and the like. Among them, in the D / A converter using the R-2R type resistance ladder circuit, since the circuit resistance is of two types, that is, the series resistance R and the shunt resistance 2R, it is possible to select one having the same accuracy and temperature coefficient. Since the resistance value can be kept low, high-speed conversion is also possible.
Since it has the advantage that the signal source impedance when the ladder circuit is viewed from the analog output terminal is constant,
Many are used.

FIG. 2 is a circuit diagram showing a configuration example of an n-bit D / A converter using a conventional R-2R type resistance ladder circuit. This D / A converter includes an R-2R resistance ladder network 10 for converting digital signals from _n- bit digital input terminals a _{0 to} a _n-1 into analog signals and outputting the analog signals to an analog output terminal V _OUT. I have it. R-2
The R-type resistor ladder network 10 has n series resistors ra _{0 to} ran _-1 each having a resistance value R, and each series resistor r.
The contact points J _{0 to} J _n-1 of a _{0 to} ran _-1 have a resistance value of 2
(N + 1) shunt resistors RA _{L having} a double resistance value 2R,
RA _{0 to} RA _n-1 are connected in a ladder shape. One end of the first stage shunt resistor RA _L is the first power source V1, for example, is connected to ground (GND) level. Each shunt resistance R
One of A _{0 to} RA _n-1 has n digital input terminals a.
_{0 to} a _n-1 are respectively connected, and a drive buffer 11 ₀ for driving and inputting n-bit digital input signals 0SB to (n-1) SB to the respective digital input terminals a _{0 to} a _n-1. .About.11 _n-1 are connected to each other. The digital input signal 0SB is the least significant bit (LSB), and the digital input signal (n-1) SB is the most significant bit (MS).
B).

An n-bit digital input signal 0SB to (n-) having a V1 level ("0") of the GND level or a V2 level ("1") of the power supply potential (VDD) level.
1) When SB is input, the digital input signal 0SB to
The (n-1) SB is driven by the drive buffers 11 _{0 to} 11 _n-1 and input to the digital input terminals a _{0 to} a _n-1 , respectively. Then, the digital input signals 0SB to (n-
1) SB is converted into an analog signal by the R-2R resistance ladder network 10, and the voltage is output from the analog output terminal V _OUT as in the following equation. V _OUT = (2 ^n-1 · (n-1) SB + 2 ^n-2 · (n-2) SB +… + 2 ¹ · ¹ SB + LSB) / 2 _n · (V2-V1) However, when a _i = V1 level iSB = "0", a _i =
ISB = “1” at the V2 level.

[0005]

However, the D / A converter having the above structure has the following problems. Figure 3
4A is a circuit diagram in the case where the D / A converter of FIG. 2 has a variation in resistance value, and FIGS. 4A and 4B are transfer characteristic diagrams of the circuit of FIG. When configuring the D / A converter 2 for example, an integrated circuit, formed by series resistor ra ₀ ~ra _n-1, and the shunt resistor _{RA L, RA 0 ~RA n-} 1 is N-type diffusion, polysilicon or the like However, even if these resistance elements have the same shape, the resistance values R and 2R vary in manufacturing. The accuracy of the voltage of the analog output terminal V _OUT of the D / A converter deteriorates due to the variations in the resistance values R and 2R.

For example, as shown in FIG. 3, the shunt resistor RA _n-1 connected to the maximum weight bit MSB and the shunt resistor RA _n-2 connected to the next weight bit (n-2) SB are connected. Variation error ΔR, Δ in resistance value 2R
R _a and resistance values 2R + ΔR and 2R + ΔR _a , respectively.
The transfer characteristic when the above condition becomes is as shown in FIG. Further, FIG. 4B shows the transfer characteristics when the resistance value 2R has variation errors −ΔR and −ΔR _a , and the resistance values 2R−ΔR and 2R−ΔR _a , respectively. Therefore, the influence of the resistance value variation ± ΔR corresponding to the maximum weight bit MSB in FIG. 3 is (n−2) in that the MSB changes.
The influence of resistance value variation ± ΔR _a corresponding to SB is (n−
2) At the point where SB changes, the differential nonlinearity error appears as accuracy deterioration of the voltage output from the analog output terminal V _OUT . (N-2) the resistance of the shunt resistor RA _n-2 corresponding to SB variation ± [Delta] R _a by contact J
_If the voltage fluctuation corresponding to the ideal output voltage of _n-2 is ΔV, the voltage fluctuation with respect to the ideal output voltage on the contact J _n−1, that is, the analog output terminal V _OUT is about half of ΔV / 2. However, the output impedance seen from the contact J _n-2 and the contact J _n-1 toward the first _- stage shunt resistance is almost the resistance value R.
It is supposed to match. The present invention has solved the problem that the conventional technique has, that the differential non-linearity error due to the variation in the resistance value is large, and in particular, the differential non-linearity error at the change point of the maximum weight bit MSB is large. D composed of R-2R type resistor ladder network
A / A converter is provided.

[0007]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a D / R using an R-2R type resistance ladder circuit.
In the A converter, (n-2) series resistors R and n
Number of shunt resistors 2R and n digital input terminals connected to one ends of the shunt resistors 2R, respectively, of the final stage shunt resistor 2R of the first and second R-2R type resistor ladder networks. The other end is commonly connected to form an analog output terminal, and a first power source is applied to the digital input terminal connected to the first stage shunt resistor 2R of the first R-2R type resistor ladder network, and the second power source is applied. The maximum weight bit of the digital input signal is applied to the digital input terminal connected to the first stage shunt resistor 2R of the R-2R type resistor ladder network.

The other (n-1) digital input terminals of the first R-2R type resistance ladder network are:
When the maximum weight bit is logical "0", the digital input signal is applied to one end of the corresponding shunt resistor 2R,
When the maximum weight bit is logic "1", the second power supply is applied to one end of all the corresponding shunt resistors 2R. Further, in the other (n) of the second R-2R resistance ladder network,
-1) All the shunt resistors 2R corresponding to the digital input terminals when the maximum weight bit is logical "0".
The first power supply is applied to one end of each of the shunt resistors and the digital input signal is applied to one end of the corresponding shunt resistor 2R when the maximum weight bit is logic "1".

[0009]

According to the present invention, since the D / A converter is configured as described above, the transfer characteristic of the first R-2R type resistance ladder network and the second R-2R type resistance ladder network are provided. Of the first R-2R resistance ladder network and the output impedance value of the second R-2R resistance ladder network viewed from the analog output terminal. Assuming that there is no difference, the voltage at the analog output terminal is the average of the transfer characteristics of the first R-2R type resistor ladder network and the transfer characteristic of the second R-2R type resistor ladder network. Become. As a result, transfer characteristics are obtained such that the maximum weight bit changes at the point of contact, and the differential nonlinearity error at the point of change of the maximum weight bit is improved. Therefore, the above problem can be solved.

[0010]

FIG. 1 is a circuit diagram of an n-bit D / A converter showing an embodiment of the present invention. This D / A converter
A first R-2 for converting a digital signal from the _n- bit digital input terminals a _{0 to} a _n-1 into an analog output voltage.
An R-type resistor ladder network 21 and a second R-2R resistor ladder network 2 for converting a digital signal from the _n- bit digital input terminals b _{0 to} b _n-1 into an analog output voltage.
2 and. The first R-2R type resistor ladder network 21 includes (n-2) series resistors ra having a resistance value R.
_{0 to} ran _-3 and n shunt resistors RA having a resistance value of 2R
It is a circuit configuration in which _{0 to} RA _n-1 are connected in a ladder shape.
The second R-2R type resistor ladder network 22, the resistance value (n-2) pieces of the series resistance rb ₀ ~rb _n-3 of R, n pieces of the shunt resistor RB ₀ ~RB _n of resistance 2R _-1 is connected to form a ladder structure. n shunt resistors R
One of A _{0 to} RA _n-1 has n digital input terminals a.
₀ to an _-1 are connected and n shunt resistors R
N digital input terminals b at one end of B _{0 to} RB _{n-1
0 to} b _n-1 are connected. Final stage shunt resistance RA
The other ends of _n-2 and RB _n-2 are commonly connected, connected to the analog output terminal V _OUT , and the first stage shunt resistor RA _n-1.
The digital input terminal a _n-1 connected to one end of
Power source V1 (for example, GND level) is connected.

The respective digital input terminals a _{0 to} a _n-2 are connected to
The input sides of the drive buffers 31 _{0 to} 31 _n-2 are respectively connected, and their output sides are connected with 2-input OR gates 41 ₀ to 4 _0.
The output side of 1 _{n- 2} is connected. The digital input signal (n-1) SB of the maximum weight bit MSB is commonly connected to one input side of each of the 2-input OR gates 41 _{0 to} 41 _n-2 , and the digital input signal 0SB is connected to the other input side.
(= LSB) to (n-2) SB are connected to each other.

The digital input terminals b _{0 to} b _n-1 are connected to
The input sides of the drive buffers 32 _{0 to} 32 _n-1 are connected to each other, and the digital input signal (n-1) SB of the maximum weight bit MSB is input to the input side of the drive buffer 32 _n-1 . . In addition, each drive buffer 32 ₀
To the input side of 32 _n-2 , a 2-input AND gate 42 ₀ to
The output sides of 42 _n-2 are connected to each other. A digital input signal (n-1) S of the maximum weight bit MSB is provided on one input side of each of the 2-input AND gates 42 _{0 to} 42 _n-2.
B is commonly input, and the digital input signals 0SB (= LSB) to (n-2) SB are respectively input to the other input side.

Common digital input signals (n-1) SB (= MSB), 0S input to the 2-input OR gates 41 _{0 to} 41 _n-2 and the 2-input AND gates 42 _{0 to} 42 _n-2.
B (= LSB) to (n-2) SB are V1 level and V2
It is a signal of a combination of levels.

FIG. 5 is a circuit diagram of a D / A converter in which the circuit of FIG. 1 has a 4-bit configuration, and elements common to those in FIG. 1 are designated by common reference numerals. Next, D shown in FIG.
The operation of the A / A converter will be described with reference to FIGS.
FIG. 6 is an equivalent circuit diagram when MSB = “0” in FIG.
FIG. 7 is an equivalent circuit diagram when MSB = “1” in FIG. Further, FIG. 8 shows bits MSB to LS in FIG.
B and digital input signals MSB, 2SB, 1SB, LS
FIG. 6 is a diagram showing a relationship with digital input signals d _{0 to} d ₁₅ corresponding to B. As shown in FIG. 6, when the maximum weight bit MSB of the digital input signal of FIG. 5 is "0", the first R
-Digital input terminal a of the 2R type resistor ladder network 21
A V1 level (GND level “0”) or a V2 level (VDD level “1”) by a digital input signal is applied to ₀ , a ₁ , and a ₂ via each OR gate 41 _{0 to} 41 _2. . The digital input terminals b ₀ , b ₁ and b ₂ of the second R-2R type resistor ladder network 22 are
Since the MSB = “0”, each AND gate 42 ₀ to 4 4
By the action of 2 ₂ all become "0" and V1 level (G
The ND level "0") is applied. The digital input terminal b ₃ of the first-stage shunt resistor 2R of the second R-2R type resistor ladder network 22, the MSB = "0", V1 level (the GND level "0") is applied.

In FIG. 7, when the maximum weight bit MSB of the digital input signal of FIG. 5 is "1", the first R-2R
-Type resistor ladder network 21 digital input terminals a ₀ , a
_Since MSB = “1” in ₁ and a ₂ , all of them become “1” by the action of the OR gates 41 _{0 to} 41 ₂ , and V
Two levels (VDD level “1”) are applied. Second
AND gates 42 _{0 to} 42 ₂ are connected to the digital input terminals b ₀ , b ₁ and b ₂ of the R-2R resistance ladder network 22 of FIG.
V1 level (GND
The level “0”) or the V2 level (VDD level “1”) is applied. At the input terminal b ₃ of the first-stage shunt resistor 2R of the second R-2R type resistor ladder network 22,
V2 level (VDD level “1”) is applied by MSB = “1”. The D / A converter of FIG. 5 has a D / A converter based on the first R-2R resistance ladder network 21 and a D / A converter based on the second R-2R resistance ladder network 22.
The A converter and the analog output terminal V _OUT are connected in parallel. Therefore, if a digital input signal of V1 level (“0”) or V2 level (“1”) is applied to each of the digital input terminals a _{0 to} a ₃ and b _{0 to} b ₃ , a 4-bit input D / A The voltage at the analog output terminal V _OUT of the converter is as follows. V _OUT = (2 ³ · MSB + 2 ² · ² SB + 2 ¹ · ¹ SB + LSB) / 2 ⁴ · (V2-V1) Similarly, in the D / A converter of FIG. 1, the output voltage of the n digital input analog output terminals V _OUT Becomes like the following D / A converter of FIG. 2 of the related art. V _OUT = (2 ^n-1 · (n-1) SB + 2 ^n-2 · (n-2) SB + ... 2 ¹ · ¹ SB + LSB) / 2 ⁿ · (V2-V1) Next, D / A in FIG. 9 and 10 show the case where the converter is integrated into a circuit and the resistance value varies accordingly.
The following description will be given with reference to (a) and (b). Figure 9
A circuit diagram in the case where there is a variation in resistance value in FIG. 1, and FIGS. 10A and 10B are transfer characteristic diagrams in FIG. In FIG. 9, ± ΔR is the shunt resistance RA _n-1.
~RB _n-1 of the resistance value variation error, ± [Delta] R _a is the resistance variation error of the shunt resistor _{RA n-2 ~RB n-2} .
In FIG. 10, V _OUT 21 is an analog output voltage of the first R-2R type resistor ladder network 21, and V _OUT 22 is a second output voltage.
2 is an analog output voltage of the R-2R resistance ladder network 22 of FIG.

As described above, the influence of the variation in the resistance value on the accuracy of the transfer characteristic is the digital input signal 0SB to (n.
-1) The upper bits of SB have a higher degree. Therefore, in the n-bit D / A converter shown in FIG.
The shunt resistor RA _n-1 of the most significant bit MSB in the first R-2R type resistor ladder network 21 and the next (n-
2) Variation errors ΔR and ΔR _a of the resistance value occur in the shunt resistor RA _n-2 corresponding to SB, and the second R-2R
Error variation Δ in the shunt resistance RB _n-1 of the most significant bit MSB in the type resistor ladder network 22 and the shunt resistance RRB _n-2 corresponding to the next (n-2) SB.
R and ΔR _a occur, and 2R + ΔR and 2R + Δ respectively
When R _a , 2R-ΔR, and 2R-ΔR _a , the transfer characteristics are as shown in FIG. Note that (n-3)
For lower bits below SB, ideal resistance value 2R
Is assumed to have been obtained.

Most significant bit MSB of digital input signal
Is "0", the first R-2R type resistor ladder network 21
A corresponding digital input signal is applied to each of the digital input terminals a _{0 to} a _n-2 , and each of the digital input terminals b _{0 to} b _n-2 and b _{n of} the second R-2R type resistor ladder network 22. _The V1 level (GND level) is applied to _-1 .

The first R as seen from the analog output terminal V _OUT
Assuming that there is no difference between the output impedance value of the −2R type resistor ladder network 21 and the output impedance value of the second R−2R type resistor ladder network 22, the analog output terminal V _OUT is R-2R type resistor ladder network 2
1 transfer characteristics and second R-2R type resistor ladder network 22
And the transfer characteristics of are averaged. Second R-2R
-Type resistor ladder network 22 digital input terminals b _{0 to} b
_{Since the} V1 level (GND level) is applied to _n-1 , the analog output terminal V _OUT has a voltage half that of the transfer characteristic of the first R-2R type resistance ladder network 21, and the voltage V1 level of FIG. It has the transfer characteristic of the analog output voltage V _OUT 21 shown in a). Therefore, the analog output voltage V _OUT 21 is
(N-2) The differential non-linearity error becomes maximum at the point where the SB bit changes. On the other hand, when the most significant bit MSB of the digital input signal is "1", V2 is applied to each digital input terminal a _{0 to} a _n-2 of the first R-2R type resistor ladder network 21.
Level (VDD level) is applied, the V2 level (VDD level) is applied to the digital input terminal b _n-1 of the second R-2R resistance ladder network 22, and the other digital input terminals b _{0 to} b _A corresponding digital input signal is applied to _n-2 . Then, the analog output terminal V _OUT is
The first R-2R type resistor ladder network 21 is approximately 1 /
The transfer characteristic is the sum of the voltage of 2 · VDD and the voltage of 1/2 of the transfer characteristic of the second R-2R type resistance ladder network 22, and the analog output voltage V _OUT shown in FIG.
It looks like 22.

Next, the point where the most significant bit MSB changes,
That is, the digital input signal is MSB = "0", (n-
2) From SB to LSB = “1”, MSB =
Consider the differential non-linearity error when changing to the state of “1”, (n−2) SB to LSB = “0”. The former MS
When B = “0”, the first R-2R type resistor ladder network 2
The inputs of the first digital input terminals a _{0 to} a _n-2 are all "1", and the second R-2R type resistor ladder network 22
The inputs to the digital input terminals a _{0 to} a _n-2 and b _n-1 are all "0". On the other hand, when the latter MSB = “1”, the digital input terminals a _{0 to} a _n−2 of the first R-2R resistance ladder network 21 are all “1”, and the second R-2R type resistor ladder network 21 is
-Digital input terminal b of 2R type resistor ladder network 22
_n-1 is "1", the input of the digital input terminal a ₀ ~a _n-2 are all "0". Regarding the digital input terminals of the former and the latter, only b _n-1 changes from "0" to "1". Shunt is connected to the digital input terminal b _n-1 resistors RB _n-1
Is 2R + ΔR, the analog output terminal V _OUT
The effect on the differential non-linearity error is the same as that of the LSB.

In addition to the circuit diagram of FIG. 9, there are many combinations of variations in resistance values, but according to the present embodiment, transmission of the first and second R-2R type resistance ladder networks 21, 22 is performed. The characteristics independently exist, and the transfer characteristics are obtained such that they are in contact with each other at the MSB changing point, and the differential nonlinearity error at the MSB changing point is remarkably improved as compared with the conventional case. The present invention is not limited to the above embodiment, and for example, the OR gates 41 _{0 to} 41 _n-2 and the AND gates 42 _{0 to} 42 _{n-2 in FIG.}
Can be configured by other input switching means, or the first and second power supplies V1 and V2 can be changed to other potentials, and various modifications can be made.

[0021]

As described in detail above, according to the present invention, the first and second R-2R type resistor ladder networks are connected in parallel to the analog output terminal, and the logic state of the maximum weight bit is obtained. Since the digital input signal according to the above is input, the differential nonlinearity error at the point where the maximum weight bit of the analog output terminal changes due to the dispersion of the shunt resistance can be remarkably improved, and the accuracy of the analog output voltage can be improved. .

[Brief description of drawings]

FIG. 1 is a circuit diagram of an n-bit D / A converter showing an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional D / A converter having an n-bit configuration.

FIG. 3 is a circuit diagram when the resistance value of the D / A converter in FIG. 2 varies.

FIG. 4 is a transfer characteristic diagram of FIG.

5 is a circuit diagram when the D / A converter of FIG. 1 has a 4-bit configuration.

FIG. 6 is an equivalent circuit diagram when MSB = “0” in FIG.

FIG. 7 is an equivalent circuit diagram when MSB = “1” in FIG.

8 is a relationship diagram between the bits MSB to LSB of FIG. 5 and the digital input signals d _{0 to} d ₁₅ .

9 is a circuit diagram in the case where the D / A converter of FIG. 1 has a variation in resistance value.

10 is a transfer characteristic diagram of FIG. 9.

[Explanation of symbols]

21 and 22 first, second R-2R type resistor ladder network 41 ₀ ~41 _n-2 OR gates 42 ₀ ~42 _n-2 AND gates 0SB~ (n-1) SB digital input signal a ₀ ~ _{an, -1,} b ₀ ~b _n-1 digital input terminal _{RA 0 ~RA n-1, RB} 0 ~RB n-1 shunt resistor _{ra 0 ~ra n-3, rb} 0 ~rb n-3 series resistor V1, V2 First and second power supply V _OUT Analog output terminal

Claims (1)

[Claims] 1. A first and a first having (n-2) series resistors R, n shunt resistors 2R, and n digital input terminals connected to one ends of the shunt resistors 2R, respectively. The other end of the second stage shunt resistor 2R of the R-2R type resistor ladder network is commonly connected as an analog output terminal, and is connected to the first stage shunt resistor 2R of the first R-2R type resistor ladder network. Applying a first power supply to the digital input terminal and applying a maximum weight bit of the digital input signal to the digital input terminal connected to the first stage shunt resistor 2R of the second R-2R resistance ladder network; The other (n- of the first R-2R resistance ladder network
1) The digital input signal is applied to one of the digital input terminals at one end of the shunt resistor 2R when the maximum weight bit is logic "0", and when the maximum weight bit is logic "1". A second power source is applied to one end of each of the shunt resistors 2R to be connected to the other (n-) of the second R-2R type resistor ladder network.
1) When the maximum weight bit is logic "0", the first power supply is applied to one end of all the corresponding shunt resistors 2R, and when the maximum weight bit is logic "1", Is a digital / analog converter characterized in that the digital input signal is applied to one end of the corresponding shunt resistor 2R.