JPH064580Y2 - Electronic circuit device - Google Patents

Electronic circuit device

Info

Publication number
JPH064580Y2
JPH064580Y2 JP1987169888U JP16988887U JPH064580Y2 JP H064580 Y2 JPH064580 Y2 JP H064580Y2 JP 1987169888 U JP1987169888 U JP 1987169888U JP 16988887 U JP16988887 U JP 16988887U JP H064580 Y2 JPH064580 Y2 JP H064580Y2
Authority
JP
Japan
Prior art keywords
conductive pattern
mechanical strength
high mechanical
conductor
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1987169888U
Other languages
Japanese (ja)
Other versions
JPH0173932U (en
Inventor
直美 須山
真光 筧
Original Assignee
関西日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 関西日本電気株式会社 filed Critical 関西日本電気株式会社
Priority to JP1987169888U priority Critical patent/JPH064580Y2/en
Publication of JPH0173932U publication Critical patent/JPH0173932U/ja
Application granted granted Critical
Publication of JPH064580Y2 publication Critical patent/JPH064580Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【考案の詳細な説明】 産業上の利用分野 本考案は、電子回路装置に関し、詳しくは、配線基板上
の導電パターンの構造に関する。TECHNICAL FIELD The present invention relates to an electronic circuit device, and more particularly, to a structure of a conductive pattern on a wiring board.

従来の技術 電子回路装置は、近年、小型軽量化、高密度実装化に伴
う、高付加価値化を実現容易化するため、リードフレー
ムを使用したトランスファモールドタイプのハイブリッ
ドＩＣが開発されている。2. Description of the Related Art In recent years, transfer mold type hybrid ICs using lead frames have been developed for electronic circuit devices in order to facilitate realization of high added value accompanying miniaturization and weight reduction and high-density mounting.

このハイブリッドＩＣの具体的構造例を第２図及び第３
図を参照しながら説明する。同図において、（１）は、
金属製のリードフレームで、矩形状のランド部（２）を
中心に、ランド部（２）の両側には、複数本のリード
（３）、（３）…を平行配置し、各リード（３）、
（３）…は、タイバー（４）を直交させ、また、ランド
部（２）の両端には、ツリピン（５）を橋絡させて、リ
ードフレーム（１）を一体構造にしてある。（６）は、
上記リードフレーム（１）のランド部（２）と同一形状
で、絶縁性を有する樹脂製の配線基板で、その表裏両面
に、銅等の導電パターン（７）を被着形成し、表面側の
導電パターン（７）の間に、チップ部品化された半導体
素子、集積回路素子、抵抗、コンデンサ等の各種電子部
品（８）、（８）…をマウントする。（９）は、上記配
線基板（６）と同一形状の樹脂製の絶縁性シートで、そ
の両面には、エポキシ系接着剤(10)、(10)を被着してあ
る。2 and 3 show a concrete structure example of this hybrid IC.
Description will be given with reference to the drawings. In the figure, (1) is
With a lead frame made of metal, a plurality of leads (3), (3), ... Are arranged in parallel on both sides of the land (2) around the rectangular land (2). ),
In (3), the lead frames (1) are integrated with each other by making the tie bars (4) orthogonal to each other and bridging the tree pins (5) at both ends of the land portion (2). (6) is
A wiring board made of a resin having the same shape as the land portion (2) of the lead frame (1) and having an insulating property is formed by depositing conductive patterns (7) such as copper on both the front and back surfaces of the wiring board. Various electronic components (8), (8), etc., such as semiconductor elements, integrated circuit elements, resistors, capacitors, etc., which are made into chip components are mounted between the conductive patterns (7). (9) is an insulating sheet made of resin having the same shape as that of the wiring board (6), and epoxy adhesives (10) and (10) are attached to both surfaces thereof.

ハイブリッドＩＣを製造するには、まず、上記リードフ
レーム（１）のランド部（２）と、絶縁性シート（９）
と、配線基板（６）とを積載して、接着剤(10)(10)によ
り固着する。そして、電子部品（８）、（８）…と導電
パターン（７）、及び、導電パターン（７）とリード
（３）、（３）…先端部とを、夫々ワイヤボンディング
にて、ワイヤ(11)によって、電子的に接続する。その
後、配線基板（６）の全体から、リード（３）の先端部
まで被覆されるように、外装樹脂剤(12)で樹脂モールド
する。To manufacture a hybrid IC, first, the land portion (2) of the lead frame (1) and the insulating sheet (9) are used.
And the wiring board (6) are stacked and fixed by the adhesives (10) and (10). Then, the electronic parts (8), (8) ... And the conductive pattern (7), and the conductive pattern (7) and the leads (3), (3). ) To connect electronically. After that, the wiring board (6) is resin-molded with the exterior resin agent (12) so as to cover the entire tip of the lead (3).

次に、配線基板（６）上の導電パターン（７）の構造
を、第４図を参照しながら説明する。同図は、配線基板
（６）の上部と導電パターン（７）の断面図で、右側の
導電パターン（７）には、キャピラリー(13)によって、
ワイヤー(11)をワイヤボンディングしている状態を示
す。導電パターン（７）は、配線基板（６）上に接着剤
〔図示せず〕によって、銅等の導体(7a)を、所望のパタ
ニングに形成し、導体(7a)の外周には、銅よりも機械的
強度の高いニッケル等の機械的強度の高い金属層(7b)と
金属(7c)とを、順次５μｍ程ずつメッキする。これは導
体(7a)である銅、及び、樹脂製の配線基板（６）が軟弱
であるから、導体(7a)に直接ワイヤボンディングできな
いため、導体(7a)の外周に、銅よりも機械的強度の高い
ニッケル等の機械的強度の高い金属層(7b)を形成し、導
体(7a)を補強する。また、金層(7c)を形成するのは、機
械的強度の高い金属層(7b)であるニッケルには、ワイヤ
ボンディングが不可能であるため、機械的強度の高い金
属層(7b)の外周に、金層(7c)を形成して、ワイヤボンデ
ィングを可能にする。Next, the structure of the conductive pattern (7) on the wiring board (6) will be described with reference to FIG. This figure is a cross-sectional view of the upper part of the wiring board (6) and the conductive pattern (7). The conductive pattern (7) on the right side is provided with a capillary (13).
The state where the wire (11) is wire-bonded is shown. The conductive pattern (7) is obtained by forming a conductor (7a) such as copper in a desired patterning on the wiring board (6) with an adhesive (not shown), and arranging the conductor (7a) around the conductor (7a) with copper. Also, a metal layer (7b) having a high mechanical strength such as nickel having a high mechanical strength and a metal (7c) are sequentially plated by about 5 μm each. This is because the conductor (7a) and the wiring board (6) made of resin are weak, and therefore wire bonding cannot be performed directly to the conductor (7a), so that the outer circumference of the conductor (7a) is more mechanical than copper. A metal layer (7b) having high mechanical strength such as nickel having high strength is formed to reinforce the conductor (7a). Further, the gold layer (7c) is formed by the metal layer (7b) having high mechanical strength. Since nickel cannot be wire-bonded, the outer periphery of the metal layer (7b) having high mechanical strength is formed. Then, a gold layer (7c) is formed to enable wire bonding.

考案が解決しようとする問題点 ワイヤボンディングに際して、導電パターン（７）に
は、キャピラリー(13)によって、相当大きな荷重が加わ
る。導電パターン（７）には、機械的強度の高い金属層
(7b)を形成し、補強してあるが、配線基板（６）が樹脂
であることも相挨って、キャピラリー(13)に押圧された
導電パターン（７）は、当該押圧された部分が、第４図
右側に示すように、配線基板（６）の上面まで陥没され
てしまう。Problems to be Solved by the Invention At the time of wire bonding, a considerably large load is applied to the conductive pattern (7) by the capillary (13). The conductive pattern (7) has a metal layer with high mechanical strength.
Although (7b) is formed and reinforced, the fact that the wiring board (6) is made of resin is also dusty, and the conductive pattern (7) pressed by the capillary (13) has As shown in the right side of FIG. 4, the upper surface of the wiring board (6) is depressed.

すると、ワイヤ(11)のボンディング強度が低下し、ワイ
ヤ(11)が外れ易くなるという問題点が生ずる。Then, the bonding strength of the wire (11) is reduced, and the wire (11) is likely to come off.

そこで、機械的強度の高い金属(7b)を厚くすることも考
えられるが、単に、導体(7a)の外周に機械的強度の高い
金属層(7b)を厚くするだけでは、第５図に示すように、
結局、金属(7c)が近接し、ショートし易くなったり、又
は、実際に、金層(7c)が接触することも考えられる。シ
ョートを防止するためには、導電パターン（７）間の金
層(7c)と金層(7c)との間に、１０μｍ以上の間隔が必要
である。Therefore, it is conceivable to thicken the metal (7b) having high mechanical strength. However, if the metal layer (7b) having high mechanical strength is thickened on the outer periphery of the conductor (7a), as shown in FIG. like,
After all, it is conceivable that the metal (7c) will be close to each other and will be easily short-circuited, or that the gold layer (7c) will actually come into contact. In order to prevent a short circuit, a space of 10 μm or more is required between the gold layer (7c) between the conductive patterns (7) and the gold layer (7c).

しかし、小型、高密度実装化を図るためには、導電パタ
ーン（７）を太くして、かつ、間隔を広げることは、好
ましくない。However, it is not preferable to thicken the conductive pattern (7) and widen the space in order to achieve a small size and high density mounting.

そこで、本願考案は、導電パターン（７）の間隔が狭い
まま、導電パターン（７）の耐衝撃性を向上させる電子
回路装置を提供することを目的とする。Therefore, an object of the present invention is to provide an electronic circuit device that improves the impact resistance of the conductive pattern (7) while keeping the distance between the conductive patterns (7) small.

問題点を解決するための手段 本考案は、上記目的を達成するため、電子部品をマウン
トする配線基板上に、導体上に機械的強度の高い金属層
を被着した導電パターンを形成した電子回路装置におい
て、上記配線基板と導電パターンの導体との間に、機械
的強度の高い金属層を介在させたものである。Means for Solving the Problems In order to achieve the above object, the present invention provides an electronic circuit in which a conductive pattern, in which a metal layer having high mechanical strength is deposited on a conductor, is formed on a wiring board for mounting an electronic component. In the device, a metal layer having high mechanical strength is interposed between the wiring board and the conductor of the conductive pattern.

作用 上記解決手段としたことにより、導電パターンの表面
に、押圧力が加わったときであっても、配線基板と導電
パターンの導体との間に介在させた機械的強度の高い金
属層が、配線基板の陥没を防止する。With the above-mentioned solution means, the metal layer having high mechanical strength interposed between the wiring board and the conductor of the conductive pattern, even when a pressing force is applied to the surface of the conductive pattern, is Prevent the substrate from sinking.

実施例 本考案に係る一実施例を、第１図を参照しながら説明す
る。但し、従来の技術において、説明した部品と同一部
品は、同一の符号を附してその説明は省略する。Embodiment An embodiment according to the present invention will be described with reference to FIG. However, in the conventional technique, the same components as those described are given the same reference numerals and the description thereof will be omitted.

同図において、(14)は、本考案に係る導電パターンで、
従来と同様、導体(14a)の外周に、機械的強度の高い金
属層(14b)と金層(14c)とを各５μｍ程度ずつ形成する。
本考案に係る導電パターン(14)の特徴とするところは、
導体(14a)と配線基板（６）との間に、機械的強度の高
い金属層(14d)を介在させたところにある。機械的強度
の高い金属層(14d)を介在しても、ハイブリッドＩＣの
小型、高密度実装化に支障は少ない。In the figure, (14) is a conductive pattern according to the present invention,
As in the conventional case, a metal layer (14b) and a gold layer (14c) each having high mechanical strength are formed on the outer periphery of the conductor (14a) by about 5 μm each.
The features of the conductive pattern (14) according to the present invention are:
A metal layer (14d) having high mechanical strength is interposed between the conductor (14a) and the wiring board (6). Even if the metal layer (14d) having high mechanical strength is interposed, it does not hinder the miniaturization and high-density mounting of the hybrid IC.

配線基板（６）と導体(14a)との間に、機械的強度の高
い金属層(14d)を介在させたことにより、導電パターン
(14)の表面に、キャピラリー(13)等によって、押圧力が
加わった時であっても、前記機械的強度の高い金属層(1
4d)が障壁となり、配線基板（６）が陥没することはな
い。Since the metal layer (14d) having high mechanical strength is interposed between the wiring board (6) and the conductor (14a), the conductive pattern is formed.
On the surface of (14), even when a pressing force is applied by the capillary (13), etc., the metal layer (1
4d) acts as a barrier, and the wiring board (6) does not sink.

ここで、本考案に係る導電パターン(14)の形成方法につ
いて、次に説明する。Here, a method of forming the conductive pattern 14 according to the present invention will be described below.

第１に、導体(14a)の表裏面で、機械的強度の高い金属
層(14b)、(14d)を形成しない箇所をカバーする。第２に
導体(14a)の表裏面に、機械的強度の高い金属をメッキ
して、上記カバーを除去すると、所望の硬い金属層(14
b)、(14d)が形成される。第３に、配線基板（６）上に
接着剤を塗布して、上記表裏面に機械的強度の高い金属
層(14b)、(14b)を形成した導体(14a)を添着する。第４
に、導体(14a)のエッチングをする。すると、導体(14a)
の表面に機械的強度の高い金属層(14b)を形成してある
箇所を除いて、導体(14a)が除去される。第５に、表面
の機械的強度の高い金属層(14b)の外周に金層(14c)を形
成し、第１図に示す導電パターン(14)を得る。この方法
であると、導体(14a)の表裏面に、同時に、機械的強度
の高い金属層(14b)、(14d)を形成するため、この機械的
強度の高い金属層(14b)、(14d)の形成するための時間を
半減することができる。First, it covers the front and back surfaces of the conductor (14a) where the metal layers (14b) and (14d) having high mechanical strength are not formed. Second, by plating the front and back surfaces of the conductor (14a) with a metal having high mechanical strength and removing the cover, a desired hard metal layer (14
b) and (14d) are formed. Thirdly, an adhesive is applied on the wiring board (6) to attach the conductors (14a) having the metal layers (14b) and (14b) having high mechanical strength formed on the front and back surfaces. Fourth
Then, the conductor (14a) is etched. Then the conductor (14a)
The conductor (14a) is removed except the portion where the metal layer (14b) having high mechanical strength is formed on the surface of the. Fifth, a gold layer (14c) is formed on the outer periphery of the metal layer (14b) having a high mechanical strength on the surface to obtain the conductive pattern (14) shown in FIG. According to this method, since the metal layers (14b) and (14d) having high mechanical strength are simultaneously formed on the front and back surfaces of the conductor (14a), the metal layers (14b) and (14d) having high mechanical strength are formed. ) Can be reduced by half.

本考案に係る導電パターン(14)の形成方法としては、配
線基板（６）の表面から順次、機械的強度の高い金属層
(14d)、導体(14a)、機械的強度の高い金属層(14b)、金
層(14c)と形成してもよく、その方法は特定するもので
はない。As a method of forming the conductive pattern (14) according to the present invention, a metal layer having high mechanical strength is sequentially formed from the surface of the wiring board (6).
(14d), conductor (14a), metal layer (14b) having high mechanical strength, and gold layer (14c) may be formed, and the method is not specified.

以上は、本考案に係る一実施例を説明したもので、本考
案は、この実施例に限定されることなく、本考案の要旨
内において、設計変更することができ、機械的強度の高
い金属層は、ニッケルに限定されないし、導体も銅に限
定されるものでない。The above is a description of an embodiment according to the present invention, and the present invention is not limited to this embodiment, and can be modified in design within the scope of the present invention and has a high mechanical strength. The layer is not limited to nickel and the conductor is not limited to copper.

考案の効果 本考案によれば、導電パターンの導体と配線基板との間
に、機械的強度の高い金属層を介在させたことにより、
耐衝撃性が向上し、配線基板が陥没することがなくなる
から、ワイヤボンディングによるワイヤの接合力が強く
なり、延いては、製品の品質の向上につながる。Effect of the Invention According to the present invention, the metal layer having high mechanical strength is interposed between the conductor of the conductive pattern and the wiring board.
Since the impact resistance is improved and the wiring board is prevented from being depressed, the wire bonding force by wire bonding is strengthened, which leads to the improvement of product quality.

【図面の簡単な説明】[Brief description of drawings]

第１図は、本考案にかかる導電パターンの断面図、第２
図は、ハイブリッＩＣの構造を示す斜視図、第３図は、
同じく断面図、第４図は、従来の導電パターンとその問
題点を示した断面図、第５図は、導電パターンの問題点
を示した断面図である。 （１）……リードフレーム、 （２）……ランド部、（３）……リード、 （４）……タイバー、（５）……ツリピン、 （６）……配線基板、（７）……導電パターン、 （８）……電子部品、（９）……絶縁性シート、 (10)……接着剤、(11)……ワイヤー、 (12)……外装樹脂材、(13)……キャピラリー、 (14)……導電パターン、(14a)……導体、 (14b)……機械的強度の高い金属層、 (14c)……金層、 (14d)……機械的強度の高い金属層。FIG. 1 is a sectional view of a conductive pattern according to the present invention, and FIG.
The figure is a perspective view showing the structure of the hybrid IC.
Similarly, FIG. 4 is a sectional view showing the conventional conductive pattern and its problems, and FIG. 5 is a sectional view showing the problem of the conductive pattern. (1) …… Lead frame, (2) …… Land, (3) …… Lead, (4) …… Tie bar, (5) …… Trip pin, (6) …… Wiring board, (7) …… Conductive pattern, (8) …… electronic parts, (9) …… insulating sheet, (10) …… adhesive, (11) …… wire, (12) …… exterior resin material, (13) …… capillary , (14) …… conductive pattern, (14a) …… conductor, (14b) …… metal layer with high mechanical strength, (14c) …… gold layer, (14d) …… metal layer with high mechanical strength.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項１】電子部品をマウントする配線基板上に、導
体上に機械的強度の高い金属層を被着した導電パターン
を形成した電子回路装置において、 上記配線基板と導電パターンの導体との間に、機械的強
度の高い金属層を介在させたことを特徴とする電子回路
装置。1. An electronic circuit device in which a conductive pattern, in which a metal layer having high mechanical strength is deposited on a conductor, is formed on a wiring substrate on which an electronic component is mounted, wherein the conductive pattern is provided between the wiring substrate and the conductor of the conductive pattern. An electronic circuit device having a metal layer having high mechanical strength interposed therebetween.
JP1987169888U 1987-11-05 1987-11-05 Electronic circuit device Expired - Lifetime JPH064580Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987169888U JPH064580Y2 (en) 1987-11-05 1987-11-05 Electronic circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987169888U JPH064580Y2 (en) 1987-11-05 1987-11-05 Electronic circuit device

Publications (2)

Publication Number Publication Date
JPH0173932U JPH0173932U (en) 1989-05-18
JPH064580Y2 true JPH064580Y2 (en) 1994-02-02

Family

ID=31460344

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987169888U Expired - Lifetime JPH064580Y2 (en) 1987-11-05 1987-11-05 Electronic circuit device

Country Status (1)

Country Link
JP (1) JPH064580Y2 (en)

Also Published As

Publication number Publication date
JPH0173932U (en) 1989-05-18

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