JPH0645444A - Designing method for layout of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To transform gates efficiently in a short time and suppress the number of the gates after transformation by a method wherein the gates to be transformed are automatically selected by paying attention to critical paths. CONSTITUTION:The initial arrangement of gates 11 is performed first and a critical path is extracted by delay analysis. Then an average wiring length over all the nets 13 is calculated. The average wiring length is calculated for every identical fan-out. A gate transformation candidate gate 15 which drives the net 13 whose wiring length is longer than the calculated average wiring length is extracted among the gates 11 of which the critical path is composed. The reduced portion of a signal propagation delay time when the extracted transformation candidate gate 15 is transformed to a high driving gate 17 is calculated and the transformation candidate gates 15 are transformed to the high driving gates 17 in the order of the scale of the reduced portion. With this constitution, useless gate transformation can be eliminated and the burden for layout can be relieved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout design method for a semiconductor integrated circuit, and more particularly to a layout design method for reducing a signal propagation delay time on a critical path by gate conversion.

[0002]

2. Description of the Related Art A signal propagation delay time in a semiconductor integrated circuit includes a delay of an element such as a gate which constitutes the semiconductor integrated circuit, a delay due to a wiring, and a delay due to an input capacitance. With the recent progress in semiconductor integrated circuit technology, the delay due to wiring has a greater effect than the delay of the element itself in a critical path in which the signal propagation delay time does not satisfy the required specifications as the circuit becomes finer and larger.

As shown in FIG. 4, a typical configuration of the critical path 41 is two flip-flops (FF) 43.
It comprises a chain of a plurality of gates 45 and nets 47 arranged between a and 43b.

In order to improve the performance of the semiconductor integrated circuit and allow it to operate normally, it is necessary to reduce the signal propagation delay time of the critical path. Therefore, as described above, reducing the delay due to the wiring further reduces the signal propagation delay time.

In layout design, as a method for reducing the wiring delay, method 1. A method of arranging so that the wiring delay does not increase when the gate is arranged.

Method 2. Gate conversion (ECO: Engeneer C
hange order) (JP-A-2-26069).

Are known.

Among them, the method 1 has a drawback that it becomes difficult to perform the gate arrangement so as to satisfy the required specifications of all the critical paths as the circuit becomes large in scale, and the processing time increases.

On the other hand, the method 2 is a method of setting an upper limit of the delay time per one stage of the gate, determining that a gate exceeding the upper limit is driving a high load, and converting the gate into a gate having a high driving force. Therefore, it is effective in reducing the wiring delay.

However, in the conventional ECO, the gate to be converted is searched over the entire semiconductor integrated circuit, and efficient gate conversion has not been performed. In addition, since a gate having a high driving force is often realized by connecting general gates in parallel, the number of gates substantially increases (the area occupied by the gates increases). Therefore, if many gate conversions are performed, the layout design will be burdened.

Further, an upper limit (drive limit) of the number of gates that can be driven by each gate is determined for each gate, and if it is attempted to drive a number of gates exceeding this upper limit (drive limit violation), the circuit Normal operation cannot be guaranteed. For this reason, when converting the gate, the drive limit of the gate before the gate to be converted must be taken into consideration, and the selection of the gate to be converted was made based on the experience of the designer.

[0012]

As described above, in the conventional ECO in the layout design, the search for the gate to be converted is performed over the entire semiconductor integrated circuit, and there is a drawback that efficient gate conversion is not performed. there were. In addition, there is a problem in that the number of gates is substantially increased by converting to a gate having a high driving force. Further, since the gate to be converted is selected based on the experience of the designer, there is a problem that the processing time becomes long.

Therefore, the present invention has been made in view of such a conventional situation, and an object thereof is to automatically select a gate to be converted by focusing on a critical path. It is an object of the present invention to provide a layout design method for a semiconductor integrated circuit, which can efficiently perform gate conversion in a short time and prevent an increase in the number of gates after conversion.

[0014]

In order to achieve the above object, the present invention provides a layout design in which a plurality of gates are arranged on a semiconductor substrate and a signal propagation delay time on a path between these gates is reduced. Then, a delay analysis in the initial stage of layout design extracts a critical path whose signal propagation delay time on the path does not meet the required specifications, and average wiring of nets between gates on the extracted critical path. The length is calculated for each same fan-out, and a gate that drives a net longer than the calculated average wiring length for each same fan-out is extracted for each same fan-out as a conversion candidate gate, and the extracted conversion candidate gate The signal propagation delay on the critical path when the conversion candidate gate is converted into a high driving force gate that is logically equivalent and has a high driving force for each The calculated decrease amount of the signal propagation delay time is large, and even if it is converted into a high driving force gate, the upper limit of the number of drivable gates of the gate in the preceding stage of this converted high driving force gate is It is provided with a means for selecting in order from the conversion candidate gates that do not exceed and converting to a high driving force gate.

[0015]

According to the present invention, the gates are initially arranged (generally arranged), delay analysis is performed, and critical paths are extracted. This is to improve the accuracy of predicting the wiring length by determining the approximate position of the gate.

Next, the average wiring length for all nets, which is an index of the conversion candidate gate, is calculated. This average wiring length is calculated for each same fan-out (the number of net branches). The reason why the average wiring length is calculated for each same fan-out is to preferentially convert a gate with a small fan-out and to postpone a gate with a large fan-out as late as possible.

Based on the calculated average wiring length, a gate conversion candidate gate for driving a net having a wiring length longer than the average wiring length is extracted from the gates constituting the critical path. Since it is more effective to execute the gate conversion on a net having a long wiring length, the gate conversion efficiency is improved by extracting a gate that drives a net having a wiring length longer than the average wiring length.

The reduction amount of the signal propagation delay time when the extracted conversion candidate gate is converted into the high driving force gate is calculated, and the conversion candidate gate having the largest reduction amount is selected in order to convert into the high driving force gate. There is. At this time, if the drive limit of the gate at the preceding stage is exceeded by converting the gate into a high driving force gate, normal operation of the circuit cannot be guaranteed. Therefore, such a conversion candidate gate is excluded from the conversion candidates.

Whether the required specifications of the signal propagation delay time on the critical path are satisfied by the above gate conversion,
Repeat until there are no conversion candidates.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a flow chart showing the processing procedure of the gate conversion method in the layout design method of the present invention.

First, a plurality of gates are initially placed on a semiconductor substrate (step 1), delay time is analyzed, and a critical path is extracted (step 2). If the critical path does not exist, the required specifications are satisfied, and the process is terminated (No at step 3).

If there is a critical path (affirmative in step 3), from all the delay time analysis results,
The average wiring length is calculated for each identical fan-out (step 4).

Next, among the gates forming the critical path, the gate driving a net having a wiring length longer than the average wiring length is extracted as a conversion candidate gate. If there is no high driving force gate which is logically equivalent to this conversion candidate gate and has a high driving force, the conversion is impossible and the process is completed (No at step 5).

If there is a high driving force gate, the reduction amount of the signal propagation delay time on the critical path when the conversion candidate gate is converted into this high driving force gate is calculated for each conversion candidate gate (step 6). . Here, a method of calculating the decrease in delay time will be described below.

The critical path is composed of a set of gates 11 and nets 13 in N stages as shown in FIG.
Has output resistance, wiring capacitance, and input capacitance, the critical path signal propagation delay time is

[Equation 1] Can be calculated by

Considering a case where one conversion candidate gate is converted into a high driving force gate, generally, one conversion candidate gate 15 (FIG. 3A) is connected in parallel as shown in FIG. It is converted into a high driving force gate 17 (FIG. 3B).

When the gates are connected in parallel, the gate internal delay and the input capacitance increase, and the output resistance decreases. For this reason,
The amount of decrease in delay time when one conversion candidate gate is converted into a high driving force gate can be calculated by the following formula.

(Decrease in delay time) = (Increase in gate internal delay) −
(Decrease in output resistance) • {(Wiring capacitance) + (Next stage input capacitance)} + (Previous stage gate output resistance) • (Increase in input capacitance due to conversion) As can be seen from this equation, high driving force By converting to a gate, the delay inside the high driving force gate increases,
The delay time from the previous gate may increase.

Considering this, it can be said that the effect of improving the delay time is higher when the conversion candidate gate for driving the net having the largest wiring capacity (long wiring length) is converted.

The calculation of the decrease in delay time is performed for each conversion candidate gate by using the above equation, and the conversion candidate gates are selected in order from the one having a large decrease and converted into the high driving force gate (step 7). At this time, by converting to a high driving force gate, conversion candidate gates that exceed the drive limit of the preceding gate are excluded from conversion candidates.

Each time one conversion candidate gate is converted into a high driving force gate, the delay time calculated in step 6 is reduced from the delay time of the critical path.
This is the delay time after conversion of this critical path. Then, if the delay time after conversion satisfies the required specifications for this critical path (Yes at Step 8) or if there is no other conversion candidate gate (No at Step 5), the process is completed.

After the gate conversion is completed, the gate is actually arranged in the initial arrangement and the check is strictly performed. This is because the gate having a high driving force is larger than the normal gate and the arrangement position actually differs, so that the influence is checked.

[0034]

As described above, according to the layout designing method of the present invention, the gates that drive nets longer than the average wiring length are limited to the gates that are converted into the high driving force gates. The layout load can be reduced without conversion. Also, because the gate that drives the net with the longest possible wiring is converted,
The effect of improving the delay time is also high.

[Brief description of drawings]

FIG. 1 is a flowchart showing a processing procedure of a gate conversion method in a layout design method of the present invention.

FIG. 2 is a circuit diagram of a critical path including a gate and a net.

FIG. 3 is a comparison diagram of a conversion candidate gate and a high driving force gate.

FIG. 4 is a circuit diagram showing a typical configuration of a critical path.

[Explanation of symbols]

 11 gates 13 nets 15 conversion candidate gates 17 high driving force gates

Claims (1)

[Claims] 1. A plurality of gates are arranged on a semiconductor substrate,
When performing layout design to reduce the signal propagation delay time on the path between these gates, a critical path whose signal propagation delay time on the path does not meet the required specifications is extracted by delay analysis in the initial stage of layout design. , The average wiring length of the net between the extracted gates on the critical path is calculated for each same fan-out, and the gate that drives the net longer than the calculated average wiring length for the same fan-out is selected as a conversion candidate. Signal propagation on the critical path when each fan-out is extracted as a gate, and each of the extracted conversion candidate gates is converted into a logically equivalent high driving force gate with high driving force. Calculate the decrease in delay time, and if the calculated decrease in signal propagation delay is large and convert to a high driving force gate, The converted high driving force selected from the conversion candidates gate, not scooped drivable gates maximum number of gates in the preceding stage in the order of the gate, the layout design method of a semiconductor integrated circuit and converting the high driving force gates of.