JP2877528B2 - Layout method of semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[Object of the Invention]

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout method for a semiconductor integrated circuit.

[0003]

2. Description of the Related Art The higher the operating frequency which is a performance index of a semiconductor integrated circuit, the better. To increase the operating frequency, the delay time of the path having the longest signal propagation delay time (critical path) among the signal paths is shortened. It is necessary to. In the case of a synchronous circuit using a clock signal,
Corresponding to the propagation delay time from the output terminal or register output terminal of the external input pad to the input terminal or register input terminal of the external output pad, and if the number of gates passing through the signal path is N stages, approximately

[0004]

(Equation 1)

[0005] Here, I _i is the internal delay time of the gate, K _i is the drive coefficient (proportional to the on-resistance of the output gate, the smaller the drive capability, the higher the drive capability), F _i is the sum of the input load capacitances of the driven gate, W _i is the wiring load capacity to be driven. It should be noted that _Ii and _Ki are originally different between the rise and fall of the input signal.

By the way, the most effective way to shorten the delay time is to modify the logical structure of the circuit. Specifically, local logic conversion for reducing the number of gate stages of the critical path, replacement with a gate having a short delay time, and the like are performed. At that time, gossip logic modification result is determined based on the delay time calculated by substituting W _i obtained from the expected line length for each net (1). However, at the time of logic design, since the layout processing has not been performed, the estimated wiring length value having a rather coarse accuracy is used. Therefore, if the predicted value deviates greatly from the actual value, it may lead to erroneous timing optimization processing. In particular, as the circuit pattern becomes finer, the wiring capacitance becomes more dominant than the gate load capacitance, and this tendency becomes more remarkable.

As a countermeasure against such a problem, as shown in FIG. 4, a timing analysis (step 63) is performed after the layout design (step 62), and if there is a timing error (step 64 affirmative), the timing error is determined. The circuit logic configuration near the location is corrected (step 61).
Conventionally, layout design (step 62) is performed again. However, even a small modification in the logical design is often a large modification in the layout design, and a path that did not cause a problem in the previous layout may become a new critical path causing a timing error.

In recent years, as another measure, in the layout design (step 62), the logical design (step 6) has been performed.
A method of performing a layout process (a net weight method or a path restriction method) so as to match the wiring length predicted at the time point 1) or the predicted path delay time has been proposed. For example, Burstein, M. andYoussef, M., “Timing Infl
uenced Layout Design ”, Proc.22nd Design Automatio
n Conf., pp 124-130, 1985 and Prasitjutrakul, S. and
Kubitz, W., “Path-Delay Constrained Floorplanning: A
Mathematical Programming Approach for Initial Pla
cement ”, Proc. 26th Design Automation Conf., pp364-3
69,1989. The common feature of these methods is that the net wiring length is shortened in accordance with a target value (wiring length or delay time) to reduce the wiring capacity and the delay time.

However, even with such control of the net wiring length, there may be some places where timing constraints cannot be observed. This is because, in the layout processing, it is required to observe constraints such as a space for arranging gates and wiring resources, which may be in a trade-off state. In that case, the logical design must be reviewed again. As described above, the conventional design flow has a problem that it takes a long time to converge the design loop in the sense of eliminating a timing error.

[0010]

As described above, in the conventional layout processing relying only on the control of the net wiring length,
Some timing constraints may not be met, and the logic design must be repeated several times to correct the timing error. The poor convergence of this design is
This is because the circuit logic is modified in the logic design and the wiring length is controlled in the layout design. Accordingly, the present invention has been made in view of such circumstances, and an object of the present invention is to reduce a signal delay time by incorporating a gate replacement process performed as a circuit logic correction into a layout process. Accordingly, it is an object of the present invention to provide a layout method capable of shortening a layout design time.

[Structure of the Invention]

[0012]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method for laying out a semiconductor integrated circuit in which a plurality of logic gates are arranged on a semiconductor substrate and the logic gates are connected by signal wiring. , A logic gate constituting a signal path sequence having a small delay time margin with respect to the required specification of the maximum delay time is logically equivalent to this logic gate,
When the logic gate on the semiconductor substrate is replaced with a logic gate that is logically equivalent to this logic gate and has a lower driving capability, and the signal propagation delay time is reduced. Is characterized in that this gate replacement is determined.

[0013]

At the end of the rough placement processing, a timing analysis is performed based on the estimated wiring length of each net to extract a critical path, and a path when the gate on the path is replaced with a gate having a high drive capability. Investigate the effect of reducing the delay time and accept the replacement if any. Also, if you are originally using a gate with high driving capacity,
Regardless of whether it is on the critical path or not, if the delay time does not increase even if the gate is replaced with a gate having low drive capability, the replacement is accepted.

After the gate replacement, timing analysis is performed again. If there is a timing error, the subsequent layout processing is stopped and fed back to the logic design processing. Note that, as replacement gates, logically equivalent gates having different drive capacities or a plurality of identical gates connected in parallel are registered in the library data in advance.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. First, the mechanism by which the delay time can be reduced by gate replacement will be described. If the gate of the i-th stage on the signal path is replaced with a gate having a different drive capability, the delay time of the i-th stage and the load capacitance seen from the (i-1) -th stage change. The change amount of the delay time before and after the replacement is ΔT = (I _i ′ + K _i ′ * (F _i + W _i )) − (I _i + K _i * (F _i + W _i ) + (I _i−1 + K _i−1) * (F _i-1 '+ W _i-1 ))-(I _i-1 + K _i-1 * (F _i-1 + W _i-1 )) = ΔI _i + ΔK _i * (F _i + W _i ) + K _{i- 1} * ΔF _i-1 (2) In the formula, the one with a dash indicates a parameter changed after the substitution.

When increasing the drive capability, ΔK _i <0
Since it is, [Delta] T <0 That condition for reducing the delay _{time, W i> -F i -K i} -1 * ΔF i-1 / ΔK i -ΔI i / ΔK i ... (3) become. Conversely, when the wiring capacitance of the net, that is, the wiring length is equal to or more than a certain value, the delay time can be reduced by enhancing the drive capability of the output gate of the net.

On the other hand, when the drive capacity is reduced, ΔK
Since _i> 0, conditions to reduce the delay time, W _i a _{<-F i -K i-1 *} ΔF i-1 / ΔK i -ΔI i / ΔK i ... (4). Conversely, when the wiring capacitance of the net, that is, the wiring length is equal to or less than a certain value, the delay time can be reduced by reducing the drive capability of the output side gate of the net. However, the positive value on the right side of equation (4) is always the second term (ie, -K _i-1 * ΔF _i-1 / ΔK).
_i ) only, the upper limit value of the wiring capacitance becomes significant only when the second term is a somewhat large positive value.

Next, the layout processing procedure will be described. FIG. 1 is an overall flow of an embodiment according to the layout method of the present invention. As can be seen from the figure, steps 2 to 7 are the layout design, and a gate replacement process (step 3) is provided after the completion of the rough placement process (step 2) to check for a timing error (steps 4 and 5). ), Detailed placement processing / wiring processing (step 6,
7). The difference from the conventional example shown in FIG. 4 is that the layout design includes a gate replacement process or a timing error check (steps 3 to 5).

Here, the point at which the gate replacement process, which is a feature of the present description, is performed immediately after the general arrangement is as follows.
For the following reasons. (A) If the gate replacement is performed after the detailed layout processing, circuit patterns overlap between adjacent gates at the layout position as it is, so that a rearrangement processing for removing this is necessary. In order to avoid this redo, gate replacement must be performed at least before the detailed placement processing. (B) In order to perform gate replacement to reduce gate delay, it is necessary that the accuracy of the delay time calculation is high to some extent, that is, the prediction accuracy of the net wiring length is high. Once the arrangement is determined, it is almost fixed, and the outline is determined at the approximate arrangement stage.

Next, a detailed processing flow of the gate replacement (step 3) will be described with reference to FIG. As shown in FIG. 2, in the first half of the process (steps 31 to 39), the replacement process with a gate having a high drive capability is performed, and in the second half (steps 40 to 44), the replacement process with a gate with a low drive capability is performed. It is carried out. In addition, in the gate replacement,
As shown in FIG. 3, in addition to logically equivalent gates 51 and 52 registered as libraries and having different drive capacities,
A gate 53 in which a plurality of identical gates 52 are connected in parallel is also a replacement target.

First, a virtual wiring length is calculated (step 31). This is performed for calculating the delay time, and a value obtained by multiplying a half-perimeter of the minimum rectangle formed by the net by a coefficient according to the number of fan-outs is used. Next, a critical path is extracted (step 32). This is a process of searching for a path that does not fit in delay specifications represented by a clock cycle time or a path with a small delay margin in a signal path that connects pads and registers to each other.

Thereafter, replacement with a gate having a high drive capability is performed (steps 33 to 39). That is, one critical path is taken out in descending order of delay time (step 33), and gates constituting the path are taken out sequentially from the starting point of signal propagation (step 34). Then, a delay time value when a logically equivalent gate is replaced with a gate having a high drive capability is obtained, and the amount of delay time reduction before the replacement is calculated using equation (2) (step 35). If there are a plurality of types of replacement gates that can be selected, each is calculated.
Further, if there is a delay time reduction, the gate replacement is accepted, and if not, the gate replacement is left as it is (steps 36 and 3).
7). When there are a plurality of types of gate replacements in which the delay time is reduced, the one with the largest reduction amount is adopted. Steps 34 to 38 are repeated until the end gate of the path is reached. The processing from step 33 onward is repeated until processing has been completed for all critical paths.

After replacement with a gate having a high drive capability is performed, replacement with a gate having a low drive capability is performed (steps 40 to 44). First, one gate on the chip is arbitrarily taken out (step 40). However, gates that have already been replaced with gates with high driving capability are excluded. A delay time value when a logically equivalent gate is replaced with a gate having a lower drive capacity is obtained, and the amount of delay time reduction before the replacement is calculated using equation (2) (step 41). If there are a plurality of types of replacement gates that can be selected, each is calculated. If there is a decrease in the delay time, the gate replacement is accepted;
2, 43). When there are a plurality of types of gate replacements in which the delay time is reduced, the one with the largest reduction amount is adopted. The processes from step 40 onward are repeated until all gates have been processed. Thus, the gate replacement processing is incorporated in the layout design.

Finally, a specific effect will be described by taking the case of an inverter chain as an example. The specifications of logically equivalent gates with different drive capacities include: Is used.

The first example relates to a replacement process with a gate having a high drive capability, and the following gate connection situation is assumed. Now, assuming that the i-th gate is a replacement target gate, F _i
= 2, ΔI _i = 0.2−0.2 = 0, Ki ₋₁ = 0.02
Since it is the (3) of the right side _{= -F i -K i-1 *} ΔF i-1 / ΔK i -ΔI i / ΔK i = -2-0.02 * ΔF i-1 / ΔK i .

Therefore, when the gate IV2 of the i-th stage is replaced with IV4, ΔF _i−1 / ΔK _i = (4-2) / (0.02-0.04) = − 100. ) Gives W _i > 0, and W
_i = 12 satisfies this. That is, the delay time is reduced by the enhancement of the driving capability. Then, the decrease amount is as follows: ΔT = ΔI _i + ΔK _i * (F _i + W _i ) + K _i−1 * ΔF _i−1 = −0.02 * 14 + 0.02 * 2 = −0.24

It should be noted that replacement with a gate having a high drive capability causes a reduction in integration due to an increase in gate area at the expense of a reduction in delay time. Therefore, it is important to use this replacement only for a critical path. The second example relates to a replacement process with a gate having a low drive capability, and has the following gate connection status.

[0028] Now, assuming that the i-th gate is a replacement target gate, F _{i
= 1, ΔI i = 0,} K i-1 = from 0.08, (4) the right side of the equation _{= -F i -K i-1 *} ΔF i-1 / ΔK i -ΔI i / ΔK i = −1−0.08 * ΔF _i−1 / ΔK _i .

Therefore, when the gate IV2 of the i-th stage is replaced with IV, ΔF _i-1 / ΔK _i = (1-2) / (0.
08−0.04) = − 25, the expression (4) is
_i <1, and W _i = 0.4 in this example satisfies this.
That is, the delay time is reduced due to the reduction in the drive capability.
Then, the decrease amount is as follows: ΔT = ΔI _i + ΔK _i * (F _i + W _i ) + K _i−1 * ΔF _i−1 = 0.04 * 1.4−0.08 * 1 = −0.024.

Note that replacement with a gate having a low drive capability usually involves a reduction in gate area. Therefore, if all of the gates on the chip that can reduce the delay time are replaced, the performance is improved and the degree of integration is increased. It can be used to improve the degree.

As described above, by replacing the gate with a gate having a high drive capability, the delay time of the critical path can be reduced, and the operating frequency of the circuit can be improved. On the other hand, by replacing the places where gates with high drive capability are originally used with gates with low drive capability within the range that does not increase the delay time, the circuit operating frequency is slightly improved and the degree of integration is reduced by reducing the gate occupation area. Is obtained.

Further, by introducing the gate replacement into the layout design processing, finer timing optimization can be achieved. In other words, since gate replacement does not change the net connection topology (input / output connection relationship) on the layout, the timing optimization is more powerful than the net wiring length control method without significantly affecting the results during the layout. Because you can do it. As a result, it is possible to reduce the frequency of occurrence of the design correction related to the timing error portion and shorten the design turnaround time.

[0033]

As described above, according to the semiconductor integrated circuit layout method of the present invention, the gate replacement processing is incorporated in the layout processing to reduce the signal delay time. As a result, the number of design corrections that have been repeated due to a timing error can be reduced, and the layout design time can be reduced.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an overall process of the present invention.

FIG. 2 is a flowchart showing a detailed process of gate replacement according to the present invention.

FIG. 3 is a circuit diagram showing an example of gates having different driving capabilities for gate replacement.

FIG. 4 is a flowchart showing a conventional design method.

Claims (2)

(57) [Claims] When laying out a semiconductor integrated circuit in which a plurality of logic gates are arranged on a semiconductor substrate and the logic gates are connected by signal wiring, a signal having a small delay time margin with respect to a required specification of a maximum delay time is used. The logic gate forming the path sequence is replaced with a logic gate which is logically equivalent to the logic gate and has a high driving capability, and when the signal propagation delay time is reduced, this gate replacement is determined. Layout method of a semiconductor integrated circuit. 2. When laying out a plurality of logic gates on a semiconductor substrate and laying out a semiconductor integrated circuit connecting the logic gates with signal wiring, the logic gates on the semiconductor substrate are logically connected to the logic gates. And replacing the logic gate with a logic gate having a low driving capability, and determining the gate replacement when the signal propagation delay time is reduced.