JPH06314313A - Delay optimization method - Google Patents

Abstract

PURPOSE:To attain the delay optimization without increasing unnecessarily the cost factors such as the increase of the chip area, etc., by using an application rule selecting means which selects an application subject block and an application rule in order to minimize the evaluation value that is calculated from plural evaluation items including the delay improvement degree and the cost factors. CONSTITUTION:A limit condition setting part 1 sets the limit conditions to the delay time and stores the conditions after converting them into an inner data structure. A circuit dividing part 2 divides a subject circuit into the blocks for each optimization processing unit. A delay analyzing part 3 carries out the delay analysis based on the limit conditions. Then an end deciding part 4 decides whether the optimization processing should be completed or not based on the result of delay analysis. If the limit conditions are not attained and may possibly be improved, an applicatioin rule selecting part 5 selects one of candidate application rules A-N for the subject block. In this case, the delay improvement degree and the cost factors such as the chip occupying area, etc., are evaluated for application of each of rules A-N.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay optimization method,
In particular, it relates to a delay optimization method used in a logic synthesis system in designing a digital logic circuit by CAD.

[0002]

2. Description of the Related Art When performing logic synthesis in the design of a digital logic circuit by CAD, delay optimization is important in order to realize a given logic function so as to minimize a signal propagation delay time in the logic circuit. is there.

Conventionally, a delay optimizing method, which is a method or rule for performing this delay optimizing, is collectively applied to the entire circuit to which the application is applied, as described in, for example, Japanese Patent Application Laid-Open No. 2-41572. Then, a plurality of delay optimizing methods are sequentially applied, or a delay optimizing method is used irrespective of the above method to select a partial circuit or block to be applied and optimize so as to minimize the maximum delay.

Referring to FIG. 3 showing an example of a conventional delay optimization method of this kind, this delay optimization method is performed by inputting a circuit description of a synchronous logic circuit described in a hardware description language or a functional block diagram. A certain circuit specification 21, a synthesis rule base 22 that stores logic synthesis rules for the circuit configuration of various functional blocks, and a logic circuit that synthesizes a logic circuit according to the logic synthesis rule from the synthesis rule base 22 using the circuit specification 21 as an input. A logic circuit synthesizing unit 23, a net list 24 of a logic circuit synthesizing output target, a synthesizing rule list 25 including a list of applied synthesizing rules and cut information of applicable blocks, and a delay analyzing unit for performing a delay analysis of the net list 24. 26, an error path list 27 that is output when there is a maximum delay error, a synthesis rule list 25, and an error Critical block extraction unit 28 for extracting a Kurichi cull block 29 from the path list 27.
And a critical block 29.

Referring to FIG. 4 showing details of the critical block extraction unit 28, the critical block extraction unit 28 includes a synthesis rule list 25 and an error path list 27.
A block path extraction unit 31 that obtains a path of a functional block corresponding to the error path from the above and a maximum stage number block search unit 32 that searches for a functional block having the largest number of stages among the functional blocks.

To explain the operation, the logic circuit synthesizing unit 23 receives the circuit specification 21 as an input and synthesizes the rule base 22.
The netlist 24 is generated in accordance with the logic synthesis rule from. At the same time, the synthesis rule list 25 when this netlist is generated is output. The delay analysis unit 26 analyzes the netlist 24 and generates an error path list 27 when there is a maximum delay error that violates a constraint condition. When the error path list 27 is generated, the critical block extraction unit 28 uses the synthesis rule list 25 to extract the critical functional block 29 on the error path. That is, the block path extraction unit 31 obtains the path of the functional block corresponding to the error path from the synthesis rule list 25 and the error path list 27, and optimizes the functional block having the largest number of stages among these functional blocks. The target critical block 29 is determined. The logic circuit synthesis unit 23 applies different rules to the critical block 29 and synthesizes the functional block again. The delay is optimized by repeating these processes.

Referring to FIG. 5 and FIG. 6, which show an example of a circuit to be optimized to which two of delay priority mapping and buffering are applied as an example of a rule for optimizing the entire circuit at once, this optimization is performed. The target circuit is the parallel circuits c1 and c2 of the plurality of blocks c to be fanned out of the plurality of cascade-connected blocks a to d and the parallel circuit d1 of the plurality of blocks d to be fanned out of the block c. , D2 are included. Where block a
Assume that the path from to block d is an error path. The delay of this error path consists of the sum of the intrinsic delays of the blocks a to d and the sum of the delays of the wirings between the blocks ab, bc, and cd.

Here, the delay priority mapping is a method of improving the intrinsic delay of the critical block by reconfiguring the block by using a higher speed circuit element in the technology library. Referring to FIG. 6, FIG.
Critical block 2 extracted as the block with the largest number of stages by the critical block extraction unit 28 in
The block a which is 9 is reconfigured into a block aH using a higher speed circuit element.

Buffering is a technique for improving the delay by inserting a buffer circuit in the output section of a block having a plurality of fan-outs to reduce the wiring delay on the error path. Referring to FIG. 6, by inserting the buffer circuit B1 in the fan-out portion other than the wiring between the blocks bc which is the error path of the output portion of the block b, the wiring capacitance between the blocks bc is reduced and the delay due to this is reduced. Improve.

Now, when the error path between the blocks a to d is to be improved in delay, the delay priority mapping is applied to each of the blocks a to d, and the buffering is applied to each of the blocks b and c. It is possible. However, the degree of each delay improvement and the magnitude of cost increase factors such as an increase in area required therefor are different.

[0011]

The above-described conventional delay optimizing method has a plurality of optimizing methods collectively applied to the entire circuit regardless of the size of a cost increase factor such as an increase in area with respect to the degree of delay improvement. Is applied sequentially, or the delay optimization target circuit is selected by the maximum number of stages, etc. regardless of the above method, so considering the above cost increase factors, it cannot be said that the design is not necessarily optimized and the cost is unnecessary. There was a drawback that it increased.

[0012]

A delay optimization method according to the present invention synthesizes a logic circuit according to a synthesis rule by using a logic function specification of a digital logic circuit given in a hardware description or a functional block diagram as an input. In a delay optimization method for performing a delay optimization process to minimize a propagation delay time of the logic circuit for realizing the logic function specification included in a logic synthesis system, an arrival time of an input signal and a required output time of an output signal. Constraint condition setting means for setting a constraint condition of the delay time based on the clock waveform, a circuit dividing means for dividing the optimization target circuit into a plurality of blocks which are unit circuits of the delay optimization processing, and each of the blocks. Delay analysis means for executing delay analysis, termination condition determination means for determining whether or not the result of the delay analysis satisfies the constraint conditions, and delay modification means. And an application rule selecting means for selecting an application rule to be applied to each of the blocks from among a plurality of optimization rules so as to maximize an evaluation value calculated from a plurality of predetermined evaluation items including a factor and a cost factor. , And a plurality of rule executing means for executing optimization processing corresponding to respective predetermined application rules.

[0013]

Embodiments of the present invention will now be described with reference to the drawings.

Referring to FIG. 1 which is a block diagram showing an embodiment of the delay optimizing method of the present invention, the delay optimizing method according to the present embodiment is composed of an input signal arrival time, an output signal request time, and a delay time according to a clock waveform. A constraint condition setting unit 1 that sets constraint conditions, a circuit dividing unit 2 that divides a target circuit into blocks of optimization processing units, a delay analyzing unit 3 that performs delay analysis of the blocks under the constraint conditions, and the delay analyzing unit. Termination condition determination unit 4 that determines whether or not to terminate the processing based on the result
And an application rule selection unit 5 that selects which of a plurality of application candidate rules to apply to the target block, and a plurality of rules that are respectively executed corresponding to the plurality of application rules A to N. The execution units 6A to 6N are provided.

Referring to FIG. 2, which shows a block diagram of the configuration of the application rule selecting unit 5, the application rule selecting unit 5 shows the delay improvement degree and the cost factor when the respective application rules A to N are applied. Rule evaluation unit 51A to be evaluated
51N and the selection part 52 which selects an application rule based on the evaluation result of rule evaluation part 51A-51N.

Next, the operation of this embodiment will be described.
Here, the rule A is the delay priority mapping described above, and the rule N is the buffering.

First, the constraint condition setting unit 1 sets constraint conditions for the delay time based on the arrival time of the input signal supplied to the input terminal, the required time of the output signal supplied to the output terminal, and the clock waveform. Then, this constraint condition is converted into an internal data structure and stored. Next, the circuit dividing unit 2 divides the target circuit into unit circuits for executing the optimization process. As an example of this division method, there is a method (rule) of dividing into units of trees having an element having a plurality of fanouts as a root. Next, the delay analysis unit 3 executes the delay analysis under the above constraint conditions. The end determination unit 4 determines whether to end the optimization process based on the result of the delay analysis. That is, if the constraint condition is satisfied, the optimization process ends.

If the above constraint conditions are not satisfied and there is a possibility of delay improvement, the process proceeds to the next execution of the applicable rule selection unit 5. The application rule selection unit 5 selects which of the plurality of application candidate rules A to N is applied to the target block. First, the rule evaluation section 51A
Each of .about.51N corresponds to the application rules A to N and evaluates the cost factor such as the delay improvement degree and the chip occupied area when applied respectively.

In the case of the delay-priority mapping of rule A, in the above evaluation, the number of elements x in the target block, the maximum number of stages y, etc. are the evaluation parameters. The rule evaluation unit 51A calculates the delay improvement level G and the cost factor C by the following evaluation formulas (1) and (2) which are predetermined based on the evaluation parameter number of elements x and maximum step number y. .

[0020]

Here, k ₁ , k ₂ , k ₃ and k ₄ are coefficients depending on the technology library, and i is a subscript indicating the i-th block.

In the case of the buffering of rule N, the fan-out number z of the target block output section or the like becomes an evaluation parameter in the above evaluation. The rule evaluation unit 51N calculates the delay improvement degree G and the cost factor C by the following evaluation formulas (3) and (4) which are predetermined based on the fan-out number z which is the evaluation parameter.

[0023]

Here, k ₅ and k ₆ are coefficients depending on the technology library.

The selection units 52 are rule evaluation units 51A and 5A, respectively.
Each delay improvement degree G and cost factor C calculated in 1N
On the other hand, the target block having the maximum evaluation value E in the following evaluation formula (5) and the application rule applied to this block are selected.

[0026]

Here, k ₇ and k ₈ are coefficients determined by the combining strategy. For example, when cost is emphasized, the value of k ₈ is set large. In this way, for example, in FIG. 5 and FIG. 6 used in the above-mentioned conventional example, the block a is selected for the rule A and the block c is selected for the rule N. Next, the selected blocks a and c are processed by the respective rule execution units 6A and 6N by the respective optimization rules A and N. The optimized blocks a and c are supplied to the delay analysis processing unit 3 again, and the subsequent processes are repeated.

Since the delay optimization rule has a dependency relationship with the circuit division method, the block selected by the selection unit is supplied to the circuit division unit instead of being supplied to the delay analysis processing unit, and the subsequent processing is repeated. Needless to say, this can be applied without departing from the spirit of the present invention.

[0029]

As described above, the delay optimizing method of the present invention sets the application target block and the application rule so as to maximize the evaluation value calculated from a plurality of evaluation items including the delay improvement degree and the cost factor. Providing the application rule selecting means for selecting has an effect that the delay optimization can be executed without unnecessarily increasing cost factors such as an increase in chip area.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a delay optimization method of the present invention.

FIG. 2 is a block diagram showing a configuration of an application rule selection unit in FIG.

FIG. 3 is a block diagram showing an example of a conventional delay optimization method.

FIG. 4 is a block diagram showing a configuration of a critical block extraction unit in FIG.

FIG. 5 is a diagram showing an example of an error path of an optimization target circuit.

FIG. 6 is a diagram showing an example of delay optimization for the optimization target block of FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 constraint condition setting part 2 circuit division part 3,26 delay analysis part 4 end condition determination part 5 applicable rule selection part 6A-6B rule execution part 21 circuit specification 22 synthesis rule base 23 logic circuit synthesis part 24 netlist 25 synthesis rule list 27 Error Path List 28 Critical Block Extraction Unit 29 Critical Block 31 Block Path Extraction Unit 32 Maximum Stage Block Search Unit 51A to 51N Rule Evaluation Unit 52 Selection Unit

Claims (2)

[Claims] 1. Realization of the logical function specification included in a logic synthesis system that synthesizes the logic circuit according to a synthesis rule by inputting a logic function specification of a digital logic circuit given in a hardware description or a functional block diagram. In the delay optimization method for performing the delay optimization process to minimize the propagation delay time of the logic circuit, the constraint condition of the delay time based on the arrival time of the input signal, the required output time of the output signal, and the clock waveform is Constraint condition setting means for setting, circuit dividing means for dividing the optimization target circuit into a plurality of blocks which are unit circuits of the delay optimization processing, delay analysis means for executing delay analysis for each block, and the delay An end condition determining means for determining whether or not the analysis result satisfies the constraint condition, and a predetermined multiple factor including a delay improvement degree and a cost factor. An application rule selecting means for selecting an application rule to be applied to each of the blocks from among a plurality of optimization rules so as to maximize the evaluation value calculated from the evaluation items of A delay optimizing method comprising: a plurality of rule executing means for respectively executing an optimizing process. 2. The same number of rule evaluation units as the plurality of units that respectively evaluate the delay improvement degree and the cost factor when the application rule selection unit applies each corresponding to each of the plurality of application rules, The delay optimizing method according to claim 1, further comprising a selecting unit that selects the applicable rule based on the evaluation results of the same number of rule evaluation units.