JP4003071B2 - Semiconductor integrated circuit design method and design apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for designing a semiconductor integrated circuit, and more particularly to a method and apparatus for designing a semiconductor integrated circuit for reducing power consumption of the semiconductor integrated circuit.
[0002]
[Prior art]
In recent years, the power consumption of CMOS-LSI has generally been increasing due to the improvement in clock frequency and higher integration due to the miniaturization of LSI processes, and in particular, CPUs exceeding 100 W have also appeared. The increase in power consumption leads to an increase in mounting cost and cooling cost, and thus there is an increasing need to suppress the power consumption of LSI as much as possible.
[0003]
However, in designing an LSI, it is necessary to satisfy a predetermined operating frequency, so that it cannot be easily converted into a gate with low power consumption.
[0004]
Therefore, as one of the placement and routing methods for a semiconductor integrated circuit, a design flow has been proposed in which a block including an excessive delay margin and an excessive capacity margin is detected after rough wiring, and the block is changed or deleted (for example, Patent Documents). 1).
[0005]
Also, the circuit is divided into a plurality of logical paths, and the divided logical paths are grouped into a plurality of groups according to the timing constraints, and the gate sizes of the elements included in the logical paths in order from the group with sufficient timing. A method for reducing power consumption and thereby reducing power consumption is considered (for example, see Patent Document 2).
[0006]
[Patent Document 1]
Japanese Patent Laid-Open No. 11-330252 [Patent Document 2]
Japanese Patent Laid-Open No. 10-92942
[Problems to be solved by the invention]
However, when a block including an excessive delay margin and an excessive capacity margin is detected after rough wiring, and the block is changed or deleted, the block is detected after rough wiring. There is a problem that a difference from the result occurs. In addition, when detailed wiring is performed after changing or deleting a detected block and problems such as delay over occur, it is not possible to correct only the part where the problem occurred. There is.
[0008]
Also, the circuit is divided into a plurality of logical paths, and the divided logical paths are grouped into a plurality of groups according to the timing constraints, and the gate sizes of the elements included in the logical paths in order from the group with sufficient timing. However, it can be said that the power consumption can be greatly reduced because only the gate size of the element included in the divided logical path is resized. I want.
[0009]
The present invention has been made in view of the above-described problems of the prior art, and a semiconductor integrated circuit design method and design apparatus capable of further reducing the power consumption of a circuit after detailed wiring. The purpose is to provide.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides:
Processing to output a netlist of a semiconductor integrated circuit;
A process of performing detailed wiring of the semiconductor integrated circuit using the netlist;
Processing for analyzing a delay margin for each of a plurality of paths constituting the semiconductor integrated circuit in which the detailed wiring is made;
A process of dividing the analyzed delay margin into a path with a predetermined value or more and a path with the delay margin less than a predetermined value;
A process of outputting a DEF file after the detailed wiring process;
The DEF file, the DEF file the delay margin including a predetermined value or more passes, a process of the delay margin is divided into a DEF file that contains the path less than the predetermined value,
A process of performing logic optimization only on a DEF file including a path having a delay margin equal to or greater than a predetermined value;
There sequentially row and a process of coupling the divided DEF file,
In the reprocessing step after the logic optimization process, the process is selected from the plurality of processes according to a design flow .
[0013]
A net list output means for outputting a net list of the semiconductor integrated circuit;
Detailed wiring means for performing detailed wiring of the semiconductor integrated circuit using the netlist;
Delay analysis means for analyzing a delay margin for each of a plurality of paths constituting the semiconductor integrated circuit in which the detailed wiring is made;
Path extraction means for dividing the analyzed delay margin into a path having a predetermined value or more and a path having the delay margin less than a predetermined value;
DEF file output means for outputting a DEF file after the detailed wiring processing in the detailed wiring means;
The DEF file, the DEF file the delay margin including a predetermined value or more paths, and netlist dividing means the delay margin is divided into a DEF file that contains the path less than the predetermined value,
Low power consumption means for performing logic optimization only on a DEF file including a path having a delay margin equal to or greater than a predetermined value;
Have a netlist coupling means for coupling the divided DEF file,
In the reprocessing step after the logic optimization process, the process is selected from the processes in the plurality of means according to the design flow .
[0016]
(Function)
In the present invention configured as described above, the net list of the semiconductor integrated circuit is output, the detailed wiring of the semiconductor integrated circuit is performed using the output net list, and the semiconductor integrated circuit having the detailed wiring is configured. Analyzes the delay margin for each of multiple paths, and further divides the analyzed delay margin into a path with a delay margin greater than a predetermined value and a path with a delay margin less than a predetermined value. Is divided into a netlist including a path with a delay margin less than a predetermined value, and only a netlist including a path with a delay margin of a predetermined value or more is subjected to low power consumption, and then divided. Join netlists.
[0017]
In this way, since the paths constituting the semiconductor integrated circuit are divided at the net list level, not only gate resizing but also logic optimization, etc. for a net list including a path having a delay margin of a predetermined value or more, Processing that can significantly reduce power consumption can be performed.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0019]
FIG. 1 is a flowchart for explaining a method of designing a semiconductor integrated circuit according to the present invention.
[0020]
In this embodiment, as shown in FIG. 1, RTL (Register Transfer Level) input processing (step S1), logic synthesis processing using a logic synthesis tool or the like (step S2), netlist output processing (step S3), A placement process using an automatic placement tool or the like (step S4), a rough routing process using an automatic wiring tool or the like (step S5) and a detailed routing process (step S6), and a plurality of components constituting the semiconductor integrated circuit after wiring Delay analysis processing (step S7) for analyzing delay margin for each path, design check processing (step S8) such as SI (signal integrity) and DRC (design rule check), and LSI design data payout processing (step S9) ) And a delay analysis process in step S7, a path and delay whose delay margin is greater than or equal to a predetermined value A delay margin is used to extract a path extraction process (step S10) for separating a path having a value less than a predetermined value, a DEF output process (step S11) for outputting a DEF that is a net list after detailed wiring, and a DEF after detailed wiring. DEF division processing (step S12) for dividing a DEF including a path having a predetermined value or more and a DEF including a path having a delay margin less than the predetermined value, and gate resizing to be performed on a DEF having a delay margin having a predetermined value or more. Processing (step S13), logic optimization processing (step S14) performed on a DEF including a path with a delay margin equal to or greater than a predetermined value, and DEF including a path with a delay margin less than a predetermined value and the delay margin equal to or greater than a predetermined value DEF after the gate resize processing is performed in step S13 on the DEF including the path of S1 or step S14 And DEF combining processing (step S15) for combining the DEF after the logic optimization processing is performed.
[0021]
In this embodiment, in the configuration as described above, a netlist including a path with a small delay margin based on a delay verification result after detailed wiring at the time of LSI design (generally used is a DEF file = Design Exchange Format, files that contain post-layout information such as placement and routing results) and netlists with paths with large delay margins. Perform free power saving processing such as logic optimization, and then combine the netlists again, and place the cell placement information (placement direction and placement coordinates) recorded in the netlist including the path with a small delay margin. ), Relocating and rewiring a netlist that includes paths with a large delay margin while retaining wiring route information, etc. Reduce power consumption without changing the delay value of no path. Here, DEF is a language that uses a simple and parseable syntax stored in an ASCII file to capture part or all of a design description at any point in the development process. Design-specific logical data that can be expressed in DEF includes internal cell connectivity (netlist), cell grouping (hierarchy), timing parameters and path constraints, scan chain, clock tree information, etc. included. The physical description includes cell grouping by hard area or soft area, cell arrangement including direction, internal connection data (wiring geometry), logical ECO change for back annotation, and the like.
[0022]
Hereinafter, a series of processes shown in FIG. 1 will be described in detail.
[0023]
First, RTL is input to a logic synthesis tool or the like (step S1).
[0024]
Next, logic synthesis is performed by a logic synthesis tool or the like based on the input RTL (step S2), and a net list is output (step S3).
[0025]
Next, placement processing is performed using an automatic placement tool or the like based on the output netlist (step S4).
[0026]
Next, rough wiring processing and detailed wiring processing are performed using an automatic wiring tool or the like (steps S5 and S6).
[0027]
Thereafter, the delay margin for each of the plurality of paths constituting the semiconductor integrated circuit after wiring is analyzed (step S7).
[0028]
Here, conventionally, if the delay analysis in step S7 is performed to satisfy the target operating frequency and the design check in step S8 is satisfied, the LSI design data is issued in step S9, and the LSI design ends. In the present embodiment, processing as described below is added in a situation where further lower power consumption is required with respect to LSI power consumption that has been increasing in recent years.
[0029]
(1) Design flow effective from the early stage to the middle stage of LSI design For example, if the target operating frequency of the LSI to be designed is 1 GHz, the CLK cycle must be kept within 1.0 ns. Delay analysis is performed on all paths in step S7, and then, in step S10, a path having a delay margin equal to or greater than a predetermined threshold and a path having a delay margin less than the predetermined threshold are separated. Here, if the threshold is 0.6 ns, a path exceeding 0.6 ns is classified as having a small delay margin because the delay margin is less than a predetermined value, and a path having a delay margin of 0.6 ns or less is set to be greater than or equal to the predetermined value. Are classified as large delay margins.
[0030]
In step S11, the DEF output after the detailed wiring is performed. After that, in step S12, the output DEF, the delay margin large and small path classification results are used to include a path with a small delay margin. Dividing into DEF and DEF including a path with a large delay margin.
[0031]
Here, the DEF division method may be divided into two DEF files, or cell placement information and wiring route information of a portion classified as having a small delay margin in one DEF file may have a FIXED attribute (already placed / It is also possible to change to an automatic placement / automatic wiring tool that cannot be changed because it is wired.
[0032]
Thereafter, in step S14, logic optimization is performed to reduce power consumption for DEF including a path with a large delay margin, and the power consumption is actively reduced. However, in this case, since the netlist including the path with the large delay margin is changed by the logic optimization, the cell placement information and the wiring route information of the netlist including the path with the large delay margin are those of the DEF output. In step S15, DEF including a path with a small delay margin and DEF including a path with a large delay margin are combined. Thereafter, the placement process in step S4, the rough wiring process in step S5, the detailed wiring process in step S6, the delay analysis process in step S7, the design check process in step S8, or the delay analysis process in step S7 and the path in step S10 again. An extraction process is performed, and a flow for reducing power consumption is performed again.
[0033]
By performing the above-described series of processing, it is necessary to re-execute the netlist placement processing, rough routing processing, and detailed routing processing including a path with a large delay margin, but a netlist cell including a path with a small delay margin. Since the placement information and the wiring route information are stored as the DEF output in step S11, the path with a small delay margin is almost the same as the first delay analysis processing in step S7 even after the placement and wiring are performed again. As a result, a delay value can be obtained, so that even if the power consumption is reduced, the delay is hardly exceeded with respect to the target operating frequency, and the design efficiency and the power consumption can be reduced.
[0034]
(2) Design flow effective in later stage of LSI design As in the design flow of (1) above, delay analysis is performed for all paths in step S7, and then a delay margin is set to a predetermined value in step S10. A path that is equal to or greater than a threshold value and a path that has a delay margin less than a predetermined threshold value are separated. Here, if the threshold is 0.6 ns, a path exceeding 0.6 ns is classified as having a small delay margin because the delay margin is less than a predetermined value, and a path having a delay margin of 0.6 ns or less is set to be greater than or equal to the predetermined value. Are classified as large delay margins.
[0035]
In step S11, the DEF output after the detailed wiring is performed. After that, in step S12, the output DEF, the delay margin large and small path classification results are used to include a path with a small delay margin. Dividing into DEF and DEF including a path with a large delay margin.
[0036]
Here, LSI design with the following library is considered (standard cell system using cells with uniform height).
[0037]
2 and 3 are diagrams showing an example of an inverter circuit structure used in the LSI design flow shown in FIG. FIG. 4 is a diagram showing an example of the cell size of the library in the LSI design flow shown in FIG.
[0038]
As shown in FIG. 3, the load driving capability is increased by connecting the gates of the load driving force standard = 1 W shown in FIG. 2 in parallel (load driving force double = 2 W). However, as shown in FIG. 4, the height in the vertical direction is the same for all types of gates, and the length in the horizontal direction varies depending on the load driving capability.
[0039]
In this design flow, only the gate resizing process is performed on the DEF including a path with a large delay margin among the divided DEFs. In order to reduce power consumption, conversion from a high power gate to a low power gate is performed without changing the logic of the gate.
[0040]
FIG. 5 is a diagram showing an example of gate resizing in the LSI design flow shown in FIG.
[0041]
As shown in FIG. 5, in this case, since the cell arrangement information described in the DEF does not change before and after the gate resizing, the arrangement processing in step S4 is omitted, and only the portion where the gate resizing is performed is performed. What is necessary is just to re-execute the rough wiring process in S5 and the detailed wiring process in step S6.
[0042]
FIG. 6 is a diagram for explaining the effect of gate resizing in the LSI design flow shown in FIG.
[0043]
As shown in FIG. 6, when the cell size is reduced, the input capacitance generated with respect to the output of the previous stage gate is reduced, so that the power consumption is reduced.
[0044]
Further, without wires after the DEF coupling process in the step S 15 (connection information of the net on the net list even if the gate resizing becomes possible omitted because there is no change), the time of the first wire A simple delay analysis process that is different from the actual wiring is performed using the RC value in a pseudo manner, the path extraction process in step S10 again (the threshold may be changed at this time), and the DEF division in step S12 process, provides low power consumption as much as possible repeated flow of DEF coupling process in the gate resizing and step S 15 in step S 13, using the finally finished DEF, global routing in step S5, step S6 Detailed wiring in step S1, delay analysis processing in step S7, design check processing in step S8 And design flow of LSI design data payout process in step S9 is also conceivable.
[0045]
When performing the above-described series of processing, cell placement information does not change before and after gate resizing in a DEF including a path with a large delay margin. Therefore, the placement processing in step S4 is omitted, and only the portion where gate resizing is performed. Since the rough wiring process in step S5 and the detailed wiring process in step S6 may be performed again, the processing time of the tool can be shortened.
[0046]
Further, after the DEF coupling process in step S 15, performs a simple delay analysis processing RC value during the first wiring without wires using artificially, path extraction processing in step S10 again, Step S12 DEF division processing in, in case of repeating a flow of DEF coupling process in the gate resizing and step S 15 is in the step S 13, the pseudo-data because it uses data when different but that once the wiring and the wiring line However, it is highly accurate (compared to virtual wiring data, etc.), and further reduces the processing time of the tool for a design flow that can reduce power consumption as much as possible while omitting wiring processing. Design efficiency and low power consumption are less likely to exceed the target operating frequency even with low power consumption. Chikaraka can be achieved.
[0047]
Furthermore, even if the delay margin size of a path which is converted by the low power consumption is delayed over after rewiring, only the path delayed over a target, DEF dividing process in step S12, the gate resizing processing in step S 13 (in this case Low conversion from power gate to High power gate) and can be modified to focus only on the path that is delayed over by performing the flow of DEF coupling processing in step S 15.
[0048]
An apparatus for designing a semiconductor integrated circuit capable of reducing power consumption can be configured by means for executing each of the series of processes described above.
[0049]
【The invention's effect】
Since the present invention is configured as described above, the following effects can be obtained.
[0050]
(1) By using the data after detailed wiring, it is possible to eliminate a delay error due to wiring during path extraction.
[0051]
(2) After detailed routing, by dividing the delay list into a netlist (for example, DEF file) including a path with a delay margin of a predetermined value or more and a netlist including a path with a delay margin of less than the predetermined value, the delay margin is reduced. Once the netlist including the path with the large delay margin is changed without changing the delay value of the netlist including the path with the small delay margin, the arrangement information and the wiring route information of the netlist including the path are completely retained. Thus, the process for reducing power consumption can be performed repeatedly a plurality of times.
[0052]
(3) By selecting a process for reprocessing according to the design flow, it is possible to reduce the LSI design time.
[Brief description of the drawings]
FIG. 1 is a flowchart for explaining a method of designing a semiconductor integrated circuit according to the present invention.
FIG. 2 is a diagram showing an example of an inverter circuit structure used in the LSI design flow shown in FIG. 1;
3 is a diagram showing an example of an inverter circuit structure used in the LSI design flow shown in FIG. 1. FIG.
4 is a diagram showing an example of a cell size of a library in the LSI design flow shown in FIG. 1. FIG.
5 is a diagram showing an example of gate resizing in the LSI design flow shown in FIG. 1. FIG.
6 is a diagram for explaining the effect of gate resizing in the LSI design flow shown in FIG. 1; FIG.
[Explanation of symbols]
10 2W inverter 20 1W inverter

Claims (2)

Processing to output a netlist of a semiconductor integrated circuit;
A process of performing detailed wiring of the semiconductor integrated circuit using the netlist;
Processing for analyzing a delay margin for each of a plurality of paths constituting the semiconductor integrated circuit in which the detailed wiring is made;
A process of dividing the analyzed delay margin into a path with a predetermined value or more and a path with the delay margin less than a predetermined value;
A process of outputting a DEF file after the detailed wiring process;
The DEF file, the DEF file the delay margin including a predetermined value or more passes, a process of the delay margin is divided into a DEF file that contains the path less than the predetermined value,
A process of performing logic optimization only on a DEF file including a path having a delay margin equal to or greater than a predetermined value;
There sequentially row and a process of coupling the divided DEF file,
A method for designing a semiconductor integrated circuit , wherein in the reprocessing step after the logic optimization process, a process is selected from the plurality of processes according to a design flow . Netlist output means for outputting a netlist of a semiconductor integrated circuit;
Detailed wiring means for performing detailed wiring of the semiconductor integrated circuit using the netlist;
Delay analysis means for analyzing a delay margin for each of a plurality of paths constituting the semiconductor integrated circuit in which the detailed wiring is made;
Path extraction means for dividing the analyzed delay margin into a path having a predetermined value or more and a path having the delay margin less than a predetermined value;
DEF file output means for outputting a DEF file after the detailed wiring processing in the detailed wiring means;
The DEF file, the DEF file the delay margin including a predetermined value or more paths, and netlist dividing means the delay margin is divided into a DEF file that contains the path less than the predetermined value,
Low power consumption means for performing logic optimization only on a DEF file including a path having a delay margin equal to or greater than a predetermined value;
Have a netlist coupling means for coupling the divided DEF file,
In the reprocessing step after the logic optimization processing, processing is selected and performed in accordance with a design flow from processing in the plurality of means .

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