JPH064470A - Data transfer system - Google Patents

Abstract

PURPOSE:To shorten the bus occupancy time at the time of data transfer, and to improve the processing capacity by constituting the system so that address buses of two systems and read/write buses of two systems are driven in one bus cycle from a first module, and a read operation and a write operation are executed simultaneously in a second module of a transmitting side and in a second module of a receiving side, respectively. CONSTITUTION:Address buses 3A, 3B and read/write buses 6A, 6B in buses for connecting a first module 1 for requesting transmission or reception of data, and second modules 2A, 2B for answering a first module 1 are constituted of two systems of that which is used for a read operation by a second module 2A of a transmitting side, and that which is used for a write operation by a second module 2B of a receiving side. In such a way, a second module 2A of the transmitting side, and a second module 2B of the receiving side can execute simultaneously the read operation and the write operation, respectively, and a data transfer in one bus cycle can be executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system for transferring data between a plurality of modules which respond to a module requesting transmission or reception of data.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a conventional data transfer system. In the figure, reference numeral 1 is a master module as a first module that requests transmission or reception of data, and 2A and 2B are slave modules as a plurality of second modules that respond to the master module 1. Reference numeral 3 denotes an address bus for the master module 1 to notify the slave modules 2A and 2B of a symmetrical area for data transfer. Reference numeral 4 denotes data for exchanging data between the master module 1 and the slave modules 2A and 2B. A bus 5 is a control bus for exchanging signals for performing predetermined control between the master module 1 and each slave module 2A, 2B, and 6 is a data for the master module 1 to send data to each slave module 2A, 2B. This is a read / write bus that informs the transfer direction.

Next, the operation will be described. Here, FIG.
FIG. 6 is a timing diagram showing a time relationship of signals transmitted on each bus of the conventional data transfer system configured as described above. When transferring data from the slave module 2A to the slave module 2B, the master module 1 first activates the read bus cycle to output the address of the data to be written to the address bus 3 and to the read / write bus 6. Output a read signal.
Next, the master module 1 sends a timing signal (1) to the control bus 5. Slave module 2
When A receives the timing signal (1) from the master module 1, it outputs data to the data bus 4 in response to the address on the address bus 3 and further outputs the timing signal (2) to the control bus 5. . When the master module 1 receives the timing signal (2) from the slave module 2A, it stores the data on the data bus 4 in an internal storage means (not shown) and ends the read bus cycle.

Next, the master module 1 activates a write bus cycle to output an address to which data is to be written to the address bus 3 and read / write bus 6
The write signal is output to. The master module 1 further sends the data stored in the internal storage means to the data bus 4 in the read bus cycle, and then sends the timing signal (1) to the control bus 5. When the slave module 2B receives the timing signal (1) from the master module 1, it reads the data on the data bus 4 in response to the address on the address bus 3 and outputs the timing signal (2) to the control bus 5. To do. The master module 1 is this slave module 2
When the timing signal (2) from B is received, the read bus cycle is ended, and the data transfer from the slave module 2A to the slave module 2B is completed.

[0005]

Since the conventional data transfer system is constructed as described above, when data is transferred from one slave module 2A to another slave module 2B, the master module 1 is slave module 2A. After reading data once, the same data must be written to the slave module 2B, which requires two bus cycles of a read bus cycle and a write bus cycle, and occupies the bus multiple times in one data transfer. There was a problem that it would be done.

The present invention has been made to solve the above problems, and an object thereof is to obtain a data transfer system with improved bus performance by reducing the bus occupation rate during data transfer. To do.

[0007]

A data transfer system according to the present invention is a first requesting transmission or reception of data.
Of the address module and the read / write bus in the bus connecting the second module responsive to the first module and the plurality of second modules responsive to the first module are used by the second module on the transmission side for the read operation. And the second module on the receiving side is used for the write operation.

[0008]

The first module of the present invention has two systems of address buses and two systems of read / write in one bus cycle.
By driving the write bus, the second module on the transmission side simultaneously performs the read operation, and the second module on the reception side simultaneously performs the write operation, thereby enabling data transfer within one bus cycle. The bus occupancy rate is reduced and a data transfer system with high bus performance is realized.

[0009]

【Example】

Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is a master module as a first module, 2A and 2B are slave modules as a second module, 4 is a data bus, and 5 is a control bus. Since these are the same as or equivalent to those, detailed description will be omitted.

3A and 3B are address buses of two systems provided in place of the conventional address bus 3, and 6A and 6B are used.
Reference numeral B is a two-system read / write bus provided in place of the conventional read / write bus 6. Also, 7
A and 7B are multiplexers arranged in the slave module 2A or 2B to select one of the two systems of address buses 3A and 3B, and 8A and 8B are also arranged in the slave module 2A or 2B. This is a multiplexer for selecting one of the two read / write buses 6A and 6B.

Next, the operation will be described. Here, FIG.
FIG. 3 is a timing diagram showing a time relationship of signals transmitted on each bus of the data transfer system of the first embodiment configured as described above. When data is to be transferred from the slave module 2A to the slave module 2B, the master module 1 activates an inter-slave data transfer bus cycle and transfers the data to the first system address bus (hereinafter referred to as # 1 address bus) 3A. The address of the data to be transferred is output, and the address of the transfer destination of the data is output to the second-system address bus (hereinafter referred to as # 2 address bus) 3B. Next, the master module 1 is the first system read / write bus (hereinafter referred to as # 1 read / write bus).
The read signal is output to 6A and the write signal is output to the second read / write bus (hereinafter referred to as # 2 read / write bus) 6B.

Next, the master module 1 sends a timing signal (1) to the control bus 5. When the slave module 2A receives the timing signal (1) from the master module 1, the multiplexer 7A causes the multiplexer 7A to # 1 the address bus 3 of the two address buses.
A is selected and 2 is set by the multiplexer 8A.
The # 1 read / write bus 6A of the read / write buses of the system is selected. The slave module 2A outputs data to the data bus 4 in response to the address on the # 1 address bus 3A and the read signal on the # 1 read / write bus 6A, and also outputs a timing signal (2) on the control bus 5. Is sent.

When the slave module 2B receives the timing signal (2) from the slave module 2A, the multiplexer 7B selects the # 2 address bus 3B from the two address buses, and the multiplexer 8B further selects the two systems. The # 2 read / write bus 6B of the read / write buses is selected. The slave module 2B responds to the address on the # 2 address bus 3B and the write signal on the # 2 read / write bus 6B by responding to the slave module 2 on the data bus 4.
The data sent from A is read and the timing signal (3) is sent on the control bus 5.

When the master module 1 receives the timing signal (3) from the slave module 2B, it terminates the inter-slave data transfer bus cycle, and the data transfer from the slave module 2A to the slave module 2B is completed. As a result, data at an arbitrary address of one slave module 2A is transferred to an arbitrary address of the other slave module 2B within one bus cycle without passing through the storage means inside the master module 1.

[0015]

As described above, according to the present invention, the first
Drive two address buses and two read / write buses in one bus cycle, and the second module on the transmission side performs the read operation and the second module on the reception side performs the write operation. Since they are configured to be performed at the same time, data can be transferred within one bus cycle, and the bus occupation time during data transfer between the second modules can be greatly reduced, resulting in a data transfer system with high processing capability. It is effective.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the above embodiment.

FIG. 3 is a block diagram showing a conventional data transfer system.

FIG. 4 is a timing chart for explaining the operation.

[Explanation of symbols]

 1 Master Module (1st Module) 2A, 2B Slave Module (2nd Module) 3A, 3B Address Bus 4 Data Bus 5 Control Bus 6A, 6B Read / Write Bus

Claims (1)

[Claims] 1. A first requesting transmission or reception of data
And a plurality of second modules responsive to the first module for address bus, data bus,
In a data transfer system, which is connected by a control bus and a read / write bus, and transfers data between the second modules via the first module, the address bus and the read / write bus are respectively transmitted to the transmission side. The data transfer system is provided with two systems, one for the read operation of the second module and the one for the write operation of the second module on the receiving side.