JPH064468A - Multi-processing system - Google Patents

Abstract

PURPOSE:To reduce the debug manhour of the multi-processing system, and also, to reduce the mounting area. CONSTITUTION:The multi-processing system is constituted by providing a slave CPU 1, a slave CPU 6 and a slave CPU 7, a master CPU 8, an IC memory 9, and a peripheral I/O device 10. A priority control circuit 12 is provided with inverters 16, 17 and 18, and NAND circuits 13, 14 and 15, as external circuits. The slave CPUs 1, 6 and 7 are formed by the same component, respectively, and each slave CPU is provided with a CPU block 2, a master/slave control circuit 3, a slave holding request inhibiting circuit 4, and a slave holding request output control circuit 5, as viewed in the slave CPU 1 in the figure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-processing system, and more particularly to a multi-processing system formed by including a master microcomputer and a plurality of slave microcomputers.

[0002]

2. Description of the Related Art Generally, a master microcomputer (hereinafter referred to as a master CPU) and a slave microcomputer (hereinafter referred to as a slave CPU) are required to form a multi-processing system. The slave CPU has two buses, the first bus is called the main bus, and it has program fetch, data access, refresh access and DMA.
It has a function of executing transfer and the like. The second bus is called a local bus, and can perform data access, refresh access, DMA transfer, etc., and is mainly used to transfer data to an external microcomputer. It has a data access function. As described above, the local bus can transfer data to and from an external microcomputer. Therefore, in the microcomputer, data transmission / reception, calculation, control, etc. are individually performed using the main bus, etc. The local bus can be used to transfer information such as data transmission / reception results, calculation results and control results executed in each microcomputer to an external microcomputer. By using the local bus to convey information,
A multi-computer including a microcomputer, an external microcomputer, and an IC memory and peripheral I / O connected to the microcomputer.
Information in the processing system can be distributed and processed, and the information processing capability of the entire multi-processing system can be improved.

A slave CPU included in a conventional multi-processing system includes a hold request output circuit for controlling a hold request output capable of bus wait operation, a hold response input circuit for receiving a hold response input, and a central processing unit. Have The master CPU connected to this slave CPU has a hold request input circuit capable of bus waiting operation, a hold response output circuit for controlling a hold response output, and a central processing unit.

In a multi-processing system, a slave CPU, a master CPU, a readable / writable IC memory or a peripheral I / O device are usually connected to form a system. In this case, the bus connecting the master CPU and the slave CPU is
It is the local bus described above. Whether the read or write operation for the IC memory or the peripheral I / O device is performed by the slave CPU is arbitrated by the hold request signal and the hold response signal. This multi-processing system has 1 slave CPU
In the case where the multi-processing system is configured by using each, the processing capacity of the multi-processing system is inevitably limited, and in order to improve the processing capacity, a plurality of slave CPUs are used.
Need to be integrated into the system. FIG. 6 is a block diagram showing a conventional example of a multi-processing system which is configured by using three slave CPUs and connecting a master CPU, an IC memory, peripheral I / O devices and the like.

As shown in FIG. 6, the multi-processing system according to the conventional example has a slave CPU 46,
47 and 48, master CPU 49, IC memory 5
0 and a peripheral I / O device 51, and as an external circuit, a master / slave control circuit 52 including an inverter 56, D flip-flops 57, 59 and 60, an OR circuit 58, and an inverter. 80, 8
1 and 82, a slave hold request prohibiting circuit 53 including a quad D flip-flop 83, a D flip-flop 61, inverters 62, 63 and 64, and a NAN.
Slave hold request output control circuit 54 including D circuits 65, 68 and 71, NOR circuits 66, 69 and 72, OR circuits 67, 70 and 73, and inverter 75.
And 76, and a priority control circuit 55 including NAND circuits 77, 78 and 79. The three transitions of this conventional example will be described below.

The first transition is that when the master CPU 49 has acquired the bus, the slave CPU 48
When the hold request output of becomes active,
This is a case where the hold request output of the slave CPU 47 is earlier than the active timing. However, regarding this first transition, the timing when the hold request of the slave CPU 47 becomes active is the master CPU 4
The case where the hold response of 9 is before being activated will be described. The second transition is a case where the slave CPU 47 acquires the bus by the first transition and then releases the bus in the slave CPU 47, which will be described. The third transition is a case where the master CPU 49 makes a bus wait request after the slave CPU 48 acquires the bus by the second operation transition.

In the first transition, the master CPU 49
Slave C while acquiring the bus at
The PU 48 outputs the hold request signal 11
8 becomes active, whereby the AND circuits 63, O
The master hold request signal 120 is activated via the R circuit 65 and the OR circuit 72. At this time, the slave hold request signal 114 in the slave CPU 46 is assumed to be inactive, and the hold request signal 118 of the slave CPU 48.
Of the hold request signal 11 of the slave CPU 47 before the master hold response signal 121 output from the master CPU 79 becomes active.
Suppose 6 becomes active.

Hold request signal 1 of slave CPU 47
When 16 is activated, the output of the OR circuit 68 goes high via the AND circuit 66. Since the hold request signal 118 of the slave CPU 48 is active, the master hold request signal 120 output from the OR circuit 72 is already at the high level. In the master CPU 49, a slave CPU
Release the bus according to the hold request signal 118 of 48,
The master hold response signal 121 is output as a high level. When the master hold response signal 121 becomes active, two circuit operations are performed. The first circuit operation is a hold response operation for the slave CPU. The second circuit operation is an operation for making the hold request signal output from the slave CPU appear to be inactive.

First, the operation of the first circuit will be described. In this circuit operation, when the master hold response signal 121 output from the master CPU 49 becomes active, the NAND circuit 7 passes through the inverter 56.
7, 78 and 79. The inverters 75 and 76 and the NAND circuits 77, 78 and 79 form a priority control circuit 55.
The outputs of 78 and 79 are the slave CPU 4 respectively.
8, as hold response signals 119, 117 and 115 to the slave CPU 47 and the slave CPU 46, they are input to the corresponding slave CPUs. In this case, the output of the OR circuit 73 is low level, and the OR circuit 70
Output of the NAND circuit 7 is at a high level, and the output of the OR circuit 67 is at a high level.
The output of 9 is high level, the output of NAND circuit 78 is low level, and the output of NAND circuit 77 is high level. Since the output of the NAND circuit 78 is low level, the hold response signal 1 to the slave CPU 47 is
17 becomes active, which causes slave CPU4
7 wins the bus.

Next, the operation of the second circuit will be described. When the master hold response signal 121 becomes active, the D flip-flop 5 is passed through the inverter 56.
CK input of 7 becomes high level. On the other hand, master CP
Since the master hold request signal 120 to U49 is high level in this case, the D flip-flop 5
The output of 7 goes high. On the other hand, since the output of the inverter 56 is high level, the output of the OR circuit 58 becomes high level and is input to the D flip-flop 59. Therefore, at the timing when the synchronization signal 122 output from the master CPU 49 becomes high level, D
The Q output of the flip-flop 59 becomes high level,
As a result, the CLR of the quad D flip-flop 83 is
The input becomes high level, and the CK input of the quad D flip-flop 83 is ready to be received. D
The synchronization signal 122 output from the master CPU 49 after the Q output of the flip-flop 59 becomes high level
Becomes a low level once, and at the timing of the next high level, the Q output of the D flip-flop 60 becomes a high level. When the Q output of the D flip-flop 60 becomes high level, the CK input of the quad D flip-flop 83 becomes high level.

On the other hand, corresponding to the hold response signals 115, 117 and 119 to the slave CPU 46, the slave CPU 47 and the slave CPU 48, respectively,
The outputs of the inverters 82, 81, and 80 are low level, high level, and low level, respectively, and at the timing when the CK input of the quad D flip-flop 83 becomes high level, the quad D
The D inputs to the flip-flop 83 are low level, high level and low level, respectively, whereby the Q inverted output of the quad D flip-flop 83 is high level, low level and high level, respectively.
The NOR circuit 7 is output at the level and corresponds to each.
2, 69 and 66. After the Q output of the D flip-flop 60 becomes high level, the master CP
Since the Q inverted output of the D flip-flop 61 becomes low level at the timing when the synchronizing signal 122 output from U49 once becomes low level and then becomes high level, the AND circuit 65, the AND circuit 68, and The output of the AND circuit 71 becomes low level and at the same time O
The output of the R circuit 66 becomes low level, the output of the OR circuit 69 becomes high level, and the output of the OR circuit 72 becomes low level. Since the outputs of the AND circuit 65 and the NOR circuit 66 are both low level, the output of the OR circuit 67 is low level, and the output of the OR circuit 73 is also low level. In the case of the OR circuit 70, A
Since the output of the ND circuit 68 is low level and the output of the OR circuit 69 is high level, its output is high level. Therefore, the master output from the OR circuit 74
Hold request signal 120 is active (high level)
Will remain. However, even though the hold request signal 118 output from the slave CPU 48 is active, the hold request signal 118 output from the slave CPU 48 is inactive because the output of the OR circuit 67 is low level. It will be as if it were.

Next, as for the second transition, as described above, a case where the slave CPU 47 releases the bus after the slave CPU 47 acquires the bus by the first transition will be described. However, the case where the hold request signal of the slave CPU 48 is activated by the first transition is described. Also, slave CP
When the master CPU 49 transits to the slave CPU 48 after U47 releases the bus, the slave CPU 4
7 and the hold request signals 116 and 114 output from the slave CPU 46 are both assumed to be inactive.

In the slave CPU 47, the bus is released and the hold request signal 116 output from the slave CPU 47 is made inactive. Upon receiving this inactive hold request signal 116, the NOR circuit 6
9, the master hold request signal 120 becomes inactive via the OR circuit 70 and the OR circuit 74. In the master CPU 49, when the master hold request signal 120 becomes inactive, the master hold response signal 121 is made inactive and the bus is acquired. When the master hold response signal 121 becomes inactive, the hold response signal 117 input to the slave CPU 47 via the inverter 56 and the NAND circuit 78 is made inactive. And at the same time,
The output of the OR circuit 58 goes low via the inverter 56.
At the timing when the level becomes high and the synchronization signal 122 output from the master CPU 49 becomes high level, D
The Q output of the flip-flop 59 and the CLR input of the quad D flip-flop 83 become low level,
Output of NOR circuit 66, output of NOR circuit 69 and N
Both outputs of the OR circuit 72 remain low level.

The Q output of the D flip-flop 59 is low.
After reaching the level, the synchronization signal 122 output from the master CPU 49 once goes to the low level and then goes to the next high level.
At the timing of reaching the level, the Q output of the D flip-flop 60 becomes the low level. When the Q output of the D flip-flop 60 becomes low level, the CK input of the quad D flip-flop 83 becomes low level. However, since the CLR input of the quad D flip-flop 83 is low level, the quad D flip-flop 8
The Q inverted output of 3 does not change. D flip-flop 60
Of the master CPU4 after the Q output of
At the timing when the synchronization signal 122 output from the signal 9 goes to the low level and then goes to the next high level, D
Since the Q-inverted output of the flip-flop 61 becomes high level, the output of the NOR circuit 66, the output of the NOR circuit 69 and the output of the NOR circuit 72 remain at the low level, and at the same time, the output of the AND circuit 68 And A
The output of the ND circuit 71 also remains at the low level, but the output of the AND circuit 65 becomes at the high level because the hold request signal 118 of the slave CPU 48 remains active. The output of the AND circuit 65 is output as an active master hold request signal 120 via the OR circuit 67 and the OR circuit 74, and is input to the master CPU 49. Master CPU 49
In, the bus is released, the master hold response signal 121 is activated and output, and the hold response signal 119 to the slave CPU 48 is activated via the inverter 56 and the NAND circuit 77. In the slave CPU 48, the hold response signal 119
When is activated, the bus is acquired.

Next, the third transition will be described. Third
As described above, the transition will be described in the case where the master CPU 49 makes a bus wait request after the slave CPU 48 acquires the bus by the second transition. At the time when the slave CPU 48 acquires the bus,
When there is a bus access request such as a high-priority refresh of the master CPU 49, the master CPU 49
In, the master hold response signal 121 is made inactive and output. Master hold response signal 1
When 21 becomes inactive, the slave CPU 48 releases the bus and makes the hold request signal 118 inactive and outputs it. When the hold request signal 118 becomes inactive, the master hold request signal 120 becomes inactive via the inverter 62, the NOR circuit 66, the OR circuit 67, and the OR circuit 74. When the master hold request signal 120 becomes inactive, the master CPU 49 acquires the bus.
Further, when the master hold request signal 120 becomes inactive, the CLR of the D flip-flop 57 is
The input becomes low level, and the Q output of the D flip-flop 57 also becomes low level. Therefore, this
The output of the circuit 58 becomes low level. When the output of the OR circuit 58 goes low, the Q output of the D flip-flop 59 and the CLR input of the quad D flip-flop 83 go low at the timing when the synchronizing signal 122 output from the master CPU 49 goes high. Therefore, the output of the NOR circuit 66, the output of the NOR circuit 69, and the output of the NOR circuit 72 remain at the low level.

The Q output of the D flip-flop 59 is low.
After reaching the level, the sync signal 122 output from the master CPU 49 once goes low and the sync signal 1
At the timing when it becomes the next high level after 22, D
The Q output of the flip-flop 60 becomes low level.
When the Q output of the D flip-flop 60 becomes low level, the CK input of the quad D flip-flop 83 becomes low level, but since the CLR input of the quad D flip-flop 83 is low level, the quad D flip-flop The level of the Q inverted output of 83 remains unchanged. After the Q output of the D flip-flop 60 becomes low level, the synchronization signal 122 output from the master CPU 49 once becomes low level and at the next high level, the D flip-flop 6
Since the Q inverted output of 1 becomes the high level, the output of the NOR circuit 66, the output of the NOR circuit 69, and the NOR circuit 7
Both of the outputs of 2 remain at the low level, and at the same time, the outputs of the NAND circuit 68 and the NAND circuit 71 also remain at the low level, but the output of the NAND circuit 65 requires the hold request of the slave CPU 48. The signal 118 is high because it remains active again.

In the conventional multi-processing system shown in FIG. 6, when a slave CPU is added to expand the system, it is included in a slave hold request output control circuit 54 included in an external circuit. Circuit elements corresponding to the inverter 62, the NAND circuit 65, the NOR circuit 66 and the OR circuit 67, the inverter 75 and the NAND circuit 7 included in the priority control circuit 55.
7, a circuit element corresponding to the inverters 80, 81 and 82 included in the slave hold request prohibiting circuit 53 and a D flip-flop in the quad D flip-flop 83, and an input system to the OR circuit 74. It is realized by adding in proportion to the number of additional slave CPUs. Even if the entire external circuit of this system is built into the master CPU and integrated into a single chip, connection is limited by the number of terminals in the IC package of the master CPU, which is two terminals each time the number of connectable slave CPUs is increased. The number of possible slave CPUs is limited.

[0018]

In the above conventional multi-processing system, the number of circuit elements included in the external circuit of the system increases in proportion to the number of slave CPUs added to expand the system. However, there is a drawback in that a huge amount of external circuit design and de-vacuum man-hours are required, and a mounting area of the system becomes large.

In addition, I of the master CPU which is made into one chip
Due to the limitation of the number of terminals of the C package, the number of slave CPUs that can be added to the system is limited, which makes it impossible to expand the system.

[0020]

A multi-processing system of the present invention includes an IC memory and peripheral I / O devices, a master CPU and a plurality of slave CPUs.
In a multi-processing system configured to be connected via a priority control circuit, the CPU block receiving a slave hold response signal input from the priority control circuit and outputting a predetermined hold request signal. And a master hold request signal generated as a logical sum of a sync signal and a master hold response signal input from the master CPU and a hold request signal output from the plurality of slave CPUs, A master / slave control circuit that outputs a signal A that determines whether the hold request signal is a request from the master side or a request from the slave side, the slave hold response signal, and the master / slave control circuit. Input the signal A and the slave hold response signal If a revertive, the slave hold request prohibition circuit for outputting an active signal B,
A slave hold request signal is received in response to the signal B output from the slave hold request prohibiting circuit, the hold request signal output from the CPU block, and the synchronization signal output from the master CPU. A slave hold request output control circuit for outputting, and a hold request signal output from the CPU block controlled by the master / slave control circuit and the slave hold request prohibition circuit. It is characterized by being able to.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in FIG. 1, this embodiment comprises slave CPUs 1, 6 and 7, a master CPU 8, an IC memory 9, and a peripheral I / O device 10, and as an external circuit, An OR circuit 11 is provided with a priority control circuit 12 including inverters 16, 17 and 18, NAND circuits 13, 14 and 15. 2 is a block diagram showing the internal configuration of the slave CPU 1 in this embodiment, and FIG. 3 is the slave C.
It is a circuit diagram which shows one Example of PU1. 2 and 3
As is clearer, the slave CPU 1 includes a CPU block 2, an inverter 19, a D flip-flop 20,
22 and 23, a master / slave control circuit 3 including an OR circuit 21, a slave hold request prohibiting circuit 4 including an inverter 24 and a D flip-flop 25, and A
The slave hold request output control circuit 5 including the ND circuit 27, the inverter 28, the NOR circuit 29, and the OR circuit 30 is provided. The three transitions of this embodiment will be described below with reference to FIGS. 1 and 3.

In the first transition, when the master CPU 8 acquires the bus, the slave hold request signal 102 of the slave CPU 1 becomes active when the slave hold request signal 102 of the slave CPU 1 becomes active. This is when it is earlier than the timing. However, regarding the first transition, a case will be described in which the timing at which the slave hold request signal 110 of the slave CPU 6 becomes active is before the master hold response of the master CPU 8 becomes active. The second transition is the slave C after the slave CPU 6 acquires the bus by the first transition.
This is a case where the bus is released in PU6, and this will be described. The third transition is the second transition.
After the slave CPU1 acquires the bus by the transition of
This is the case where the master CPU 8 makes a bus wait request.

In the first transition, while the master CPU 8 is acquiring the bus, the slave CP
In U1, the output slave hold request signal 102 becomes active, whereby the OR circuit 11
The master hold request signal 104 is activated via the. At this time, the slave hold request signal 112 in the slave CPU 7 is assumed to be inactive, and the master hold response signal output from the master CPU 8 after the slave hold request signal 102 of the slave CPU 1 becomes active. Slave CPU before 105 becomes active
Suppose the slave hold request signal 110 of 6 becomes active.

Consider a case where the slave hold request signal 110 of the slave CPU 6 becomes active. Even if the slave hold request signal 110 of the slave CPU 6 becomes active, the slave hold request signal 102 of the slave CPU 1 becomes active,
The master hold request signal 104 output from the OR circuit 11 is at high level. The master CPU 8 outputs the response signal 105 as active according to the slave hold request signal 102 output from the slave CPU 1. When the master hold response signal 105 becomes active, two circuit operations are performed. The first circuit operation is a hold response operation for the slave CPU. The second circuit operation is an operation for making the slave hold request signal output from the slave CPU appear to be inactive.

First, the operation of the first circuit will be described. In this circuit operation, when the master hold response signal 105 output from the master CPU 8 becomes active, the master hold response signal 105 passes through the inverter 16 to the NAND circuits 13, 14 and 1
Input to 5. Inverters 16, 17 and 18;
The NAND circuits 13, 14 and 15 form a priority control circuit 12, and the outputs of the NAND circuits 13, 14 and 15 are the slave CPU 7 and the slave C, respectively.
The slave hold response signals 113, 111, and 103 to the PU 6 and the slave CPU 1 are input to the corresponding slave CPUs. In this case, the slave hold request signal 102 output from the slave CPU 1 is low level, the slave hold request signal 110 output from the slave CPU 6 is low level,
Since the slave hold request signal 112 output from the slave CPU 7 is at the high level, the output of the NAND circuit 13 is at the high level and the NAND
The output of the circuit 14 becomes low level, and the output of the NAND circuit 15 becomes high level. Since the output of the NAND circuit 14 is low, the slave CPU 6
The hold response signal 111 becomes active, and the slave CPU 6 acquires the bus.

Next, the operation of the second circuit will be described. In FIG. 3, when the master hold response signal 105 becomes active, the CK input of the D flip-flop 20 via the inverter 19 becomes high level. On the other hand, since the master hold request signal 104 to the master CPU 8 is high level in this case, the output of the D flip-flop 20 becomes high level. On the other hand, since the output of the inverter 19 is high level, the output 108 of the OR circuit 21 becomes high level and is input to the D flip-flop 22. Therefore, at the timing when the synchronization signal 101 output from the master CPU 8 becomes high level, the Q output of the D flip-flop 22 becomes high level.
CLR input becomes high level, and the CK input of the D flip-flop 25 is ready to be received. D
After the Q output of the flip-flop 22 becomes high level, the synchronization signal 101 output from the master CPU 8 once becomes low level, and at the timing when it becomes the next high level, the Q output of the D flip-flop 23 becomes Become high level. When the Q output of the D flip-flop 23 becomes high level, CK of the D flip-flop 25
The input goes high.

At the timing when the CK input of the D flip-flop 25 becomes high level, the Q inverted output of the D flip-flop 25 changes. D flip-flop 2
At the timing when the CK input of 5 becomes high level,
D flip-flop 25 output from the inverter 24
Becomes low level, and the Q inverted output of the D flip-flop 25 to the NOR circuit 29 becomes high level. After the Q output of the D flip-flop 23 becomes high level, the synchronization signal 101 output from the master CPU 8 once becomes low level, and at the timing when it becomes the next high level, the Q inversion of the D flip-flop 26 is performed. Since the output goes low, the AND circuit 27
Output goes low, and at the same time, the output of the NOR circuit 29 goes low. Since both the output of the AND circuit 27 and the output of the NOR circuit 29 are low level, the output of the OR circuit 30, that is, the slave hold request signal 102 is low level. Although the hold request signal 107 output from the CPU block 2 is active, the slave hold request signal 102 output from the OR circuit 30 becomes low level, so that the slave hold request of the slave CPU 1 The signal 102 is output at the inactive level.

Next, as for the second transition, as described above, the case where the slave CPU 6 releases the bus after the slave CPU 6 acquires the bus by the first transition will be described. However, this is due to the first transition
The case where the hold request signal 107 output from the CPU block 2 inside the slave CPU 1 is active will be described. In addition, after the slave CPU 6 releases the bus,
Space hold request signal 1 output from slave CPU 6 and slave CPU 7 when transitioning to 1
Assume that 10 and 112 are both inactive.

In the slave CPU 6, the bus is released and the space hold request signal 110 output from the slave CPU 6 is made inactive. This inactive space hold request signal 110 is
It is output as an inactive master hold request signal 104 via the OR circuit 11. Master CPU
In FIG. 8, when the master hold request signal 104 becomes inactive, the master hold response signal 105
Inactivate and win the bus. When the master hold response signal 105 becomes inactive, the space hold response signal 11 input to the slave CPU 6 via the inverter 16 and the NAND circuit 14
Make 1 inactive. At the same time, the output of the OR circuit 21 becomes low level via the inverter 19, and at the timing when the synchronization signal 101 output from the master CPU 8 becomes high level, the Q output of the D flip-flop 22 and the D flip-flop 22. 25 CL
The R input becomes low level, and the output of the NOR circuit 29 remains low level.

The Q output of the D flip-flop 22 is low.
At the timing when the synchronization signal 101 output from the master CPU 8 once goes to the low level and then goes to the next high level after reaching the level, the D flip-flop 2
The Q output of 3 becomes low level. When the Q output of the D flip-flop 23 becomes low level, the CK input of the D flip-flop 25 becomes low level, but since the CLR input of the D flip-flop 25 is low level, the Q of the D flip-flop 25 becomes The inverting output does not change. After the Q output of the D flip-flop 23 becomes the low level, the synchronization signal 101 output from the master CPU 8 once becomes the low level and then becomes the next high level.
Since the Q inversion output of the NOR circuit 2 becomes high level,
The output of 9 remains low level, and the AND circuit 27
Is output from the hold request signal 107 of the CPU block 2.
Will remain high because it remains active. The output of the AND circuit 27 is the OR circuit 30.
Is output as an active master hold request signal 104 via the OR circuit 11 and the master CPU 8
Entered in. The master CPU 8 releases the bus, activates and outputs the master hold response signal 105, and activates the master hold response signal 103 to the slave CPU 1 via the inverter 16 and the NAND circuit 15. In the slave CPU 1, when the hold response signal 103 is active and is input, the bus is acquired.

Next, the third transition will be described. Third
As described above, the transition will be described in the case where the master CPU 8 issues a bus wait request after the slave CPU 1 acquires the bus by the second transition. When there is a bus access request such as a high-priority refresh of the master CPU 8 when the slave CPU 1 has acquired the bus, the master CPU 8 outputs the master hold response signal 105 inactive. To do. When the master hold response signal 105 becomes inactive, the inverter 16 and the NAND
The slave hold response signal 103 output from the slave CPU 1 via the circuit becomes inactive. When the slave hold response signal 103 becomes inactive, the slave CPU 1 releases the bus,
The slave hold response signal 103 is made inactive. As a result, via the OR circuit 11, the master
The hold request signal 104 becomes inactive. When the master hold request signal 104 becomes inactive, the master CPU 8 acquires the bus. When the master hold request signal 104 becomes inactive, the CLR input of the D flip-flop 20 becomes low level via the inverter 19, and the C of the D flip-flop 20 becomes C.
The LR input becomes low level, and the Q output of the D flip-flop 20 becomes low level. When the Q output of the D flip-flop 20 becomes low level, the OR circuit 2
The output of 1 becomes low level. When the output of the OR circuit 21 goes low, the input of the sync signal 101 goes high.
At the timing of reaching the level, the Q output of the D flip-flop 22 and the CLR of the D flip-flop 25
The input becomes low level, and the output of the NOR circuit 29 remains low level.

After the Q output of the D flip-flop 22 becomes the low level, the synchronizing signal 101 output from the master CPU 8 once becomes the low level and then becomes the next high level.
Q inversion output becomes low level. As a result, the CK input of the D flip-flop 25 becomes low level, but since the CLR input of the D flip-flop 25 is low level, the Q inverted output of the D flip-flop 25 does not change. After the Q output of the D flip-flop 23 becomes low level, the synchronization signal 101 output from the master CPU 8 once becomes low level and at the next high level, the Q inversion of the D flip-flop 26 is performed. Output goes high. As a result, the output of the NOR circuit 29 remains at low level, and the output of the AND circuit 27 becomes high level because the hold request signal 107 output from the CPU block 2 remains active again. Become. Therefore,
It is possible to easily realize a multi-processing system configured by connecting a master CPU and a plurality of slave CPUs. Also, slave C to be multi-connected
A slave CPU can be easily added by increasing the number of inverters and the number of NAND circuits by one as external circuits for each increase in PU. Also, FIG.
As shown in (3), a lot of external hardware is not required, which facilitates hardware debugging and also reduces the mounting area. In addition, FIG.
(B), (c), (d), (e), (f), (g),
(H), (i), (j), (k), and (l) are operation timing charts in the present embodiment, which are the synchronization signal 101 and the slave hold request signals 112 and 11, respectively.
0 and 102, master hold request signal 104, bus signal 106, master hold response signal 105, slave hold response signals 113, 111 and 103,
Master / slave signals 108 and 109 are shown.

The slave CP is shown in FIG.
FIG. 7 is a circuit diagram of another embodiment of U, including a CPU block 2 and
Master / slave control circuit 31 including inverters 34 and 35, D flip-flops 36 and 38, and OR circuit 37, slave hold request prohibiting circuit 32 including D flip-flop 41, D flip-flops 39 and 40, OR circuit 42, inverter 43, NA
A slave hold request output control circuit 33 including an ND circuit 44 and an OR circuit 45 is provided. The operation of this slave CPU is the same as in the case of the first embodiment described above.

[0035]

As described above, according to the present invention, it is possible to facilitate hardware debugging at the time of developing the multi-processor system and to reduce the mounting area of the system. is there.

As an external circuit, the slave CPU 1
There is an effect that a multi-processing system can be configured by connecting many slave CPUs by only adding one inverter and NAND circuit for each.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a slave CPU according to the present embodiment.

FIG. 3 is a circuit diagram showing a first embodiment of a slave CPU in this embodiment.

FIG. 4 is an operation timing chart in the present embodiment.

FIG. 5 is a circuit diagram showing a second embodiment of the slave CPU in this embodiment.

FIG. 6 is a block diagram showing a conventional example.

[Explanation of symbols]

1, 6, 7, 46 to 48 Slave CPU 2 CPU block 3, 31, 52 Master / slave control circuit 4, 32, 53 Slave hold request prohibition circuit 5, 33, 54 Slave hold request output control circuit 8, 49 Master CPU 9,50 IC memory 10,51 Peripheral I / O device 11, 21, 30, 37, 42, 45, 58, 67, 7
0, 73, 74 OR circuit 12, 55 Priority control circuit 13-15, 27, 44, 77-79 NAND circuit 16-19, 24, 28, 34, 35, 43, 56, 6
2 to 64, 75, 76, 80 to 82 Inverter 20, 22, 23, 25, 26, 36, 38 to 41, 5
7, 59 to 61 D flip-flop 27, 65, 68, 71 AND circuit 29, 42, 66, 69, 72 NOR circuit 83 Quad D flip-flop

Claims (1)

[Claims] 1. A multi-processing system including an IC memory and a peripheral I / O device, wherein a master CPU and a plurality of slave CPUs are connected via a priority control circuit, wherein the priority control circuit. A slave hold response signal input from the master CPU, a CPU block that outputs a predetermined hold request signal, a synchronization signal and a master hold response signal input from the master CPU, and a plurality of slave CPUs. Master / hold request signal generated as a logical sum of hold request signals, and outputs a signal A for determining whether the master / hold request signal is a request by the master side or a request by the slave side. Slave control circuit, slave hold response signal, master / A slave hold request prohibition circuit which inputs the signal A output from the slave control circuit and outputs an active signal B when the slave hold response signal is inactive, and the slave hold request prohibition circuit. A slave hold request that receives the signal B output from the circuit, the hold request signal output from the CPU block, and the synchronization signal output from the master CPU, and outputs a slave hold request signal. An output control circuit, and a hold request signal output from the CPU block can be controlled by the master / slave control circuit and the slave hold request prohibition circuit. Multi-processing system.