JPH0644299B2 - Data Flow Processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of use) The present invention relates to a data flow processor characterized in that a memory unit and an arithmetic unit are connected by a pipeline bus and the arithmetic order is controlled by a data flow method. It is about.

(Prior Art) Conventionally, there is a μPD7281 manufactured by NEC Corporation as a data flow processor.

The μPD7281 has a structure as shown in FIG. The token, which is the unit of data input to the device from the external bus, has a data value, a link table address for referring to the link table 92 after input, and a module number indicating the device on which the token is to be processed. The unit 91 inputs the token internally when the module number of the token passing through the external bus matches the number of the device, and otherwise outputs the token directly from the external bus through the token output unit 97. The input token refers to the link table 92 by its own link table address, and after obtaining the function table address for referencing the function table 93 and the link table address for referencing the link table 92 next time, the function is executed. Sent to table 93.

The token refers to the function table address in the function table 93, and then refers to and updates the management information of the data memory 94, and at the same time obtains a processing code indicating the processing content in the processing unit 96 and an access address of the data memory 94. , And is sent to the data memory 94, where it waits for the operand of the other party of the binary operation or reads out a constant for constant operation, if necessary. The queue memory 95 is a memory for temporarily holding the token when the processing unit 96 is processing the previous token and cannot input the next token, and when the processing unit 96 is not busy, the token is processed from the queue memory 95. Sent to the unit 96, depending on the processing code, arithmetic operation,
It receives one of a logical operation, a shift, a comparison, a bit inversion, a priority encoding, a shunt, a numerical value generation, a copy, and an operation using an internal register.
If the processing code of the token indicates output, the token is sent from the queue memory 95 to the token output unit 97, transformed into the form of the input token, and then output to the external bus. The token processed by the processing unit 96 is sent to the link table 92, and again referred to by the link table address. In the same manner, the data is passed through the internal link bus until the output instruction is executed, and the necessary processing is performed on the data value.

(Problems to be Solved by the Invention) When a plurality of data in the form of vector data are handled collectively by the above data flow processor and processing is performed on them, they are decomposed into a stack of binary operations. , Two pieces of binary operation data of such a partial portion must be waited for in the processor by a wait instruction to advance the processing. In this case, the token makes the internal ring 1 in order to perform one binary operation. There is a problem that the processing speed becomes slow because it is necessary to go around.

In order to solve this, the processing unit has a register, multiple data that should be processed collectively can be poured into the processing unit one after another, and it can be processed at high speed by using the internal state in the register. In order to know that the continuous operation of vector data is completed and the result should be output, it is necessary to pre-program the number of these collected data as an instruction for the operation and count the tokens passing through. It is impossible to input variable vector data for processing.

For example, consider the case of processing a vector having only non-zero elements in the original matrix as seen in the numerical calculation that handles a sparse matrix. At this time, the length of vector data is variable,
When these data are continuously read from the memory and input to the data flow processor that performs the process of summing them, the flow graph that describes the processing program by giving the same identifier because they flow as continuous data Must flow into the same arc at. At that time, in order to identify the end, it is necessary to send a token having data indicating that the token is the end of vector data at the end. However, in addition, when there are a plurality of program modules that perform summation in the same data flow processor and they are to be operated independently, in order to share only one register and perform correct operation,
At the same time, the synchronous operation must be realized by software so that only one program module performs the cumulative addition process.

An example of a flow graph describing the program in that case is shown in FIG. In FIG. 7, as described above, for each data of the data token string input with the same identifier, it is first judged whether or not it is the end mark, and then the cumulative addition operation is performed, The register is being read when the mark is detected. Further, in order to prevent the cumulative addition processing in a plurality of program modules as described above from interfering with each other, it is controlled so that only one program module operates at a time.

In this way, for the problem that the vector data with identification information that the length is variable and is the last at the end is input to this data flow processor one after another and the sum of the vector data elements is obtained, By recognizing the tail end, it is not possible to process the input data by passing it through the processing unit one by one, and this must be realized by software, and moreover, the synchronization of multiple program modules must also be programmed. It is unavoidable that the load of software becomes heavy and the processing speed becomes slow due to the synchronization overhead.

The present invention provides a mechanism in which a token string having variable-length vector data can be completed by passing through a processing unit once for an addition operation, and further, interference between a plurality of program modules does not occur. The purpose is to provide a data flow processor that reduces the token flow rate in the data flow processor and realizes high-speed processing.

(Means for Solving Problems) A data flow processor of the present invention is a link table which is connected in order on a ring bus and stores a destination address of a token, and a function for generating an address for referring to an instruction code. Table address generation unit, function table for storing instruction code, data memory for temporarily storing data used for binary operation, queue memory for temporarily holding token, processing for processing token data and outputting the result to the link table It has a unit and further has a token output unit for sending a token from the queue memory to the external bus and a token input unit for inputting a token from the external bus and sending it to the link table or the token output unit. Is characterized by .

(Operation) In the present invention, when obtaining the sum of vector data of length N, a set token of length N having the vector data is used. These tokens have a set identifier in addition to a link table address, a data value, etc. which have been conventionally held as a token. This is, for example, "1" in the first token of the N set of tokens, "2" in the second to N-1th tokens, and "0" in the last token. These tokens have the same link table address, and are continuously input to the function table address generator after obtaining the same function table base address by reference in the link table. The access address of the function table is obtained by calculating the above set identifier. As a result, for example, in this case, the first token has the instruction code "set its data value in the register of the processing unit and the token disappears" from the second to the N-1th "the data value For the Nth instruction code, "add the data value to the register of the processing unit and then use the value of the register as the result data token."
Has the instruction code.

By such a method, even if the length of the vector data to be processed is not given in advance by the program in the data flow processor, the set token input by sending these N tokens to the arithmetic unit once By executing different instructions, it is possible to perform the processing that is complete for the purpose.

(Example) Next, this invention is demonstrated with reference to drawings.

FIG. 1 is an internal block diagram showing a configuration of a data flow processor according to an embodiment of the present invention. 11 is a token input unit, 12 is a link table, 20 is a function table address generation unit, 13 is a function table, and 14 is a function table.
Is a data memory, 15 is a queue memory, 16 is a processing unit, 17 is a token output unit, and a link table 12, a function table address generation unit 20, a function table 13, a data memory 14, a queue memory
15, the processing unit 16 is connected in a ring shape by a pipeline bus in this order as shown in the figure,
The token is transferred on this internal ring bus in synchronization with the pipeline clock in the data flow processor.

FIG. 2 is an overall configuration diagram of an example of a data processing device using an embodiment of the present invention. In this device, a plurality of data flow processors 1 and 2 and one memory interface circuit 3 are connected by an external bus 5, and the external bus 5 is connected to the memory 4 via the memory interface circuit 3. The token is transferred asynchronously on the external bus 5 by the handshake method.

FIG. 3 shows the format of a token which is a unit of data.

The token 60 on the external bus 5 comprises a module number 61, a set identifier 62, a link table address 63 and a data section 64.

Reference numeral 65 indicates the format of the token sent from the link table 12 to the function table address generation unit 20, and 66 indicates the format of the token sent from the function table address generation unit 20 to the function table 13.

The tokens used in this embodiment can be processed as one unit with a set token composed of one or a plurality of tokens. The group token always flows continuously in the processing device, and has the same module number 61 and the same link table address 63, 83, 87.

The pair identifiers 62, 82, 86 are used to identify the token within a pair token, and are "0" if the token alone constitutes a pair token, or one another within a pair token composed of multiple tokens. Can have different values if they need to be distinguished. However, the last token in the group token has "0" as the group identifier.

The token input unit 11 takes in only those tokens whose module number 61 is equal to the number given to the device among the tokens inputted by the token input request signal 42 from the preceding data flow processor or memory interface circuit. The tokens are sent to the table 12 in synchronism with the pipeline cycle, and the other tokens are sent as they are to the token output unit 17 as passing tokens. However, when the link table 12 or the token output unit 17 is in the busy state during the processing of the group token as described below, the token is not sent, and the handshake acknowledge signal 43 is sent to the preceding data flow processor or memory interface circuit. Stop input by not returning.

The link table 12 inputs a token from the processing unit 16 or the token input unit 11, but when both requests are made at the same time, the input from the token input unit 11 is usually prioritized. However, the processing unit 16 gives priority to it while the continuous token is being generated by the copy operation, and if the input token set identifier is not "0" regardless of which token it is, the token is Since it is a token other than the last one of the group tokens and the rest of the group tokens are input continuously, inform the person who is not the source of those tokens that they are busy and input. By stopping, the entire tokens in the set are preferentially input continuously. This guarantees the continuity of the group token.

The token input to the link table 12 from the processing unit 16 or the token input unit 11 refers to its internal memory by using the link table address 63 as in the conventional case, and the function table base address 81 and the next link table obtained there. 12 The link table address 83 for reference is sent to the function table address generation unit 20. The token format at this time is shown at 65 in FIG.

The function table address generator 20 generates the function table address 85 as described later, and the third
A token of the form 66 in the figure is sent to the function table 13.

In the function table 13, the internal table is accessed by the function table address 85 of the input token 66, the management information of the data memory 14 is referred / updated, and at the same time, the processing code indicating the processing content in the processing unit 16, and The access address of the data memory 14 is added to the token.

The data memory 14 is accessed by the above-mentioned access address, and if necessary, as a queue for waiting for the token having the address of the binary operation data or the token having the data when the write token is output to the memory interface circuit, Alternatively, it is used as a memory for storing constants for constant calculation.

The queue memory 15 is a memory for temporarily holding the token before inputting the token to the processing unit 16 or the token output unit 17, and outputs the token according to the processing code of the token at the head of the queue. The operation of sending to the unit 17 is performed.

The processing unit 16 has a function of performing arithmetic operations, logical operations, shifts, comparisons, bit inversions, priority encodings, shunting, number generation, copying, internal register operations and operations using the same as in the conventional processing, or Having some of the above-mentioned functions, it also performs arithmetic processing on the data of the token input from the queue memory 15 according to the processing code of the token, and sends the token having the data of the arithmetic result to the link table 12.

When the processing code 68 of the token at the head of the FIFO forming the queue memory 15 indicates output, the token is sent to the token output unit 17. However, when the token output unit 17 is in the busy state, the output to the token output unit 17 is stopped.

The token output unit 17 transforms the token input from the queue memory 15 or the token input unit 11 into a token format 60 on the external bus 5a, and a data flow processor or a memory interface circuit at a subsequent stage via the external bus 5a. Output to. However, when there is a request from both the queue memory 15 and the token input unit 11 at the same time, the input from the token input unit 11 is usually given priority. However, if the set identifier of the input token is not "0" regardless of which one, the token is a token other than the end of the set token consisting of multiple tokens, and the set tokens are consecutive. Since it is understood that the rest of the tokens will be input, by notifying the non-source of those tokens that they are in a busy state and stopping the input, priority is given to the entire set of tokens To do. This guarantees the continuity of the group token.

When the memory interface circuit 3 receives a token 60 having a module number 61 destined to it from the data flow processors 1 and 2, the operation specified by the ring table address 63 and data 64 therein is performed. For example, when a read request token is given, a read operation is performed from the memory 4 by using the value contained in the data 64 as an address, and the token having the read value is sent to the data flow processor designated by the link table address 63, or the write data is written. When a token having a token and a token having a write address are given as a pair token, they are used to perform a write operation to the memory 4. Further, when the memory interface circuit 3 is given a token having a value N and a "read group token generation command", it performs a read operation N times from the memory 4, holds those values, and has a length N having a necessary group identifier. To generate a pair token of and send it to the data flow processor.

Next, details of the embodiment of the function table address generator 20 will be described with reference to FIG.

The function table address generator 20 is a register 50
Has a token format entered from the link table 12
The token with 65 is held in this register 50 in synchronization with the pipeline clock. The value of the function table base address 81 of the token 65 held in the register 50 and the value of the pair identifier 82 are input to the adder 51, and the adder 51 adds the sum to the function table address 85 of the output token having the token format 66. Output as the value of the field. For the other fields 86, 87, 88 of the output token 66, the values of the corresponding fields 82, 83, 84 on the register 50 are used as they are.

As a result, multiple tokens that make up a group token have the same function table base address by inputting to the link table with the same link table address, but different function table addresses by having different group identifiers. It becomes possible to have. By using it to access different addresses in the function table 13, each token in the set tokens having the same link table address 63 and continuously flowing in the data flow processor is subjected to different processing. You can

Next, a method and operation for obtaining the sum of vector data of length N using this data flow processor will be described.

In advance, the address a of the link table 12 is set to b as the function table base address, and the address (b + 1) of the function table 13 is set to the address (the data value is set in the register of the processing unit and the token disappears) to the address ( b + 2)
To the instruction code "Add that data value to the register of the processing unit and the token disappears"
An instruction code "add the data value to the register of the processing unit and then use the value of the register as a result data token" is set in the address b.

In addition, a set token of length N is prepared in the memory interface circuit, and each of N pieces of data to be summed as data has a value a as a link table address. As the set identifier, the first token has "1", the second to N-1th tokens have "2", and the last token has "0".

The tokens that form this group of tokens are continuously input to the link table 12 and the address a indicated by the link table address is accessed, so that N tokens having b as the function table base address 81 in the format 65 are consecutive. And is sent to the function table address generation unit 20. In the function table address generation unit 20, the first token is (b + 1) by adding the function table base address and the set identifier “1”, and similarly from the second token to the N−1th token (b + 2), At the end, b is obtained as the function table address 85, respectively.

These tokens are continuously sent as they are to the function table 13, and by accessing the table by the function table address that they have,
For the first token, the instruction code "Set the data value in the processing unit register and the token disappears" is added to the second to N-1th instruction "Add the data value to the processing unit register. , The token disappears ", the Nth is" add the data value to the register of the processing unit, and then use the value of the register as the result data token. "
Then, the processing unit 16 can use the register according to the code to obtain the sum.

Note that unlike the present embodiment, "0" is used as the last group identifier of the group token of length N and "1" is used for the other tokens, and the N-1th tokens from the beginning are added to the register. , It is also possible to use an instruction that the last token is added, the result is output and the register is cleared at the same time. Furthermore, a set token of length N + 1 consisting of N tokens having "1" and one token having "0" as a set identifier is used, the former is register addition, the latter is the result output and register without addition. It is also possible to achieve clearing.

As an example, FIG. 5 shows an example of a flow graph in which a program for performing the cumulative addition processing described in the section of the problem of the conventional apparatus is described using this embodiment. In FIG. 5, as described above, in the data token string input with the same identifier, the end is identified by the pair identifier of the token, so an instruction to determine it is unnecessary, and each Since the vector data always flows continuously under the control of the set token, there is no possibility of causing interference between a plurality of program modules, and therefore it is not necessary to incorporate a synchronization mechanism. This reduces the load on the program and speeds up the processing because there is no program overhead for synchronous control.

(Effects of the Invention) As described above, according to the present invention, it is possible to perform different processing by individual tokens in continuous data. In the case where pre-processing and post-processing are performed before and after the processing of, even if the number of continuous data is not known in advance, it is possible to send these N tokens to the arithmetic unit once and The processing can be continuously performed with the intermediate processing, and the load on the program can be reduced and the processing can be speeded up.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a data flow processor of the present invention, FIG. 2 is an overall configuration diagram showing an example of a processing device using the data flow processor, and FIG. 3 is a diagram showing a format of a token used for explaining the present invention. 4, FIG. 4 is a detailed block diagram showing an embodiment of the function table address generation unit 20, FIG. 5 is a flow graph diagram showing a method of implementing the cumulative addition process in the present invention, and FIG. 6 is a conventional device. FIG. 7 is a configuration diagram of a data flow processor for the purpose, and FIG. 7 is a flow graph diagram showing a method of realizing the cumulative addition process in the conventional apparatus. In the figure, 11 …… Token input section, 12 …… Link table, 13 ……
Function table, 14 …… Data memory, 15 ……
Cue memory, 16 ... Processing unit, 17 ...
Token output part, 20 ... Function table address generation part.

Claims (1)

[Claims] 1. A data flow processor that performs processing by flowing a token, which is a unit of data, to an internal ring-shaped bus, and a link that stores destination addresses of tokens that are connected in sequence on the bus. Table, function table address generation unit that generates addresses for referencing instruction codes, function table that stores instruction codes, data memory that temporarily stores data used for binary operation, queue memory that temporarily holds tokens, and tokens It has a processing unit that performs data processing and outputs the result to the link table, and further outputs a token from the queue memory to the external bus and a token output unit, and inputs the token from the external bus to the link table or the token output unit. Token input When a set token composed of a plurality of continuously flowing tokens and having a set identifier for identifying each other is given as an input to the data flow processor, the token is stored in the function table. A function table base address that each of the tokens in the set token has in common in the function table address generation unit, an address for referring to a processing instruction for
A data flow processor, wherein each token is generated by an operation with a different set identifier in each token.