JPH0644069A - Microprocessor for controlling peripheral device - Google Patents

Abstract

PURPOSE:To provide a microprocessor capable of controlling a peripheral device just by changing the microprocessor and reloading a register by adding minimum hardwares while maintaining interchangeability. CONSTITUTION:An address comparator circuit 6 compares addresses outputted by a bus control unit 11 with the contents of a register reloading branching destination address latch 15 for which latched contents can be easily reloaded, starts a register reloading branching destination 2 when the coincidence of the addresses is confirmed and transfers the next register contents from a ROM 4 without changing a software while monitoring an instruction execution state inside the microprocessor. The reset address of the microprocessor is set to the address latch 15 immediately after resetting and a flag register 5 inhibits the decoding of instructions exclusively for reloading the contents of the address latch 15 when the function is not used and holds the interchangeability to the conventional software.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peripheral device control circuit, and more particularly to a microprocessor for controlling a peripheral device having a microprocessor as a control means.

[0002]

2. Description of the Related Art Conventionally, a microprocessor is mainly used,
In a computer system with a small overall system scale, the performance required for peripheral devices of the computer system, such as external storage devices, printing devices, and communication devices, is extremely simplified and simple, and the required processing per hour is required. Since the speed was also limited, the structure of the peripheral device was simple and in many cases it was a circuit that could perform the required functions at the minimum level. However, recently, even in the case of a computer system in which the entire system is small in scale, high speed, high institution, and high function are required due to the dramatic increase in speed and integration of semiconductor integrated circuits and the rapid sophistication of society. It is being requested.

Along with this, the peripheral devices of the computer system are also required to have higher functions. Therefore, the peripheral devices are provided with a plurality of or several levels of functions in advance, and when the user uses them, they are directly connected by a DIP switch or the like. Peripheral devices that select and use the necessary functions by means of hardware switching have first appeared, but the user understands the peripheral device, computer system and software instruction manual for each application software used in the computer system. Therefore, it requires the user to have some knowledge of the computer system itself. For this reason, even if there is another computer system having the same device configuration as the computer system, the same application software cannot always be executed, and it is difficult to change the device configuring the system.

In order to eliminate such inconvenience, recently, by using a microprocessor for controlling the peripheral device itself in the peripheral device and making the peripheral device itself a simple computer device, the function of the peripheral device is expanded. There are many methods used to achieve this by software. When a user installs a new application software or changes the device of a computer system, in many cases the peripheral device itself is converted to a computer device by simply specifying the patch file or batch file created for each peripheral device provided by the software manufacturer. We provided a user-friendly environment where software or peripheral device installation was completed.

On the other hand, in the peripheral device using the microprocessor for controlling the inside of the peripheral device, the process for changing the condition setting for switching the function inside the device is directly performed by the DIP switch or the like which has been conventionally performed. The switching process becomes an indirect and complicated process by software, requires a processing time determined by the CPU bus cycle and the number of execution clocks, and runs counter to the demand for high speed required for computer systems. In order to reduce the processing time of the microprocessor required to switch the functions of peripheral devices and the processing time required to transfer data, and to meet the demand for higher speed of the entire computer system, the number of operating clocks inside the device is generally increased to process the microprocessor. Measures have been taken such as increasing the speed, using a faster and more powerful microprocessor for controlling peripheral devices, and making a multiprocessor system with an increased number of microprocessors.

However, the speedup by these methods is
Although effective, it is not a basic solution because it accepts the problems caused by the structure of the processing procedure of the conventional microprocessor, leading to higher cost, more complicated timing design, and internal device It causes a new problem that the control program of is lost.
Therefore, in order to solve the problem of speeding up from the level of self-confidence of the microprocessor, the procedure of switching the contents of registers necessary for switching the processing contents in the processing procedure of the microprocessor is performed as shown in FIG. A microprocessor has been proposed that has a function of instantaneously switching register contents by register bank switching in addition to processor configuration functions.

[0007]

In the above-described conventional microprocessor, one microprocessor can achieve both high performance and high speed by expanding flexible functions by software, which is an advantage of computer systemization of peripheral devices. In order to achieve this, the registers inside the microprocessor are banked, and by switching the register bank, the internal state of the microprocessor is instantaneously switched, and the functions of the peripheral devices to be controlled are switched. The existing terminals were made to be exactly the same as the microprocessors before that. For this reason, the printed wiring board of the CPU board can be changed minimally, but in order to make full use of this register bank switching function, it is necessary to drastically change the control program of the peripheral device and to require advanced techniques and know-how. , It was difficult to keep compatibility with existing software. It is an object of the present invention to provide a microprocessor capable of controlling peripheral devices by only changing the microprocessor while maintaining compatibility.

[0008]

SUMMARY OF THE INVENTION The present invention is directed to a register which can be rewritten without depending on a register transfer instruction of a microprocessor, a latch which is rewritten by this transfer instruction, a register and a means for rewriting the latch, a register and a register. A means for determining whether to rewrite the latch and a means for measuring the timing of rewriting the register and the latch are provided. Further, according to the present invention, means for supplying the address of the branch destination for which the register needs to be rewritten and the contents of the register to be rewritten from the outside of the microprocessor, and the rewriting control of the register and the latch are activated when this supplying means is not connected. And means for preventing the malfunction caused by the above and the malfunction caused by the activation of the rewriting control of the register and the latch even when the software for the conventional microprocessor is executed, on the hardware or the software.

[0009]

According to the present invention, when a conditional branch or the like is performed during the execution of the control program, the address of the branch destination is compared with the address on the address latch in which the address for which the register needs to be rewritten by the dedicated rewriting instruction is set in advance. Confirm whether the register needs to be rewritten, clear the instruction queue when the rewrite request is confirmed, rewrite the external register referenced by the branch destination address while prefetching the instruction to the instruction queue, and reset the software. And the rewriting of the register performed by a series of write operations is performed only by hardware without affecting the operation of a normal microprocessor.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the present invention. When a reset pulse having a length of 4 clocks or more is input from the external reset input terminal RESET1, the register rewrite control circuit 2 causes the reset signal 3 in the microprocessor to be reset.
To the register rewriting branch destination (call destination: the same applies hereinafter) from the dedicated AD bus 16 of the ROM (or RAM, the same applies below) 4 that stores the address table and register contents outside the microprocessor. RO storing address table and register contents
ROM4, which stores the register rewrite branch destination address table and register contents, is used for exclusive AD
If it is not connected to the bus 16, the flag register 5 is set to "0" in order to invalidate the register rewriting function,
Similar to a normal microprocessor, the reset signal 3 inside the microprocessor is restored, and the normal operation is started after the reset operation.

If the register rewriting destination address table and the ROM 4 storing the register contents are connected, first, the flag register 5 is set to "1" to enable the register rewriting function, and the reset signal inside the microprocessor is set. Return 3 The register rewrite branch destination address table 15 and the ROM 4 storing the register contents are connected to each other, so that the register rewrite branch destination address latch 15 does not malfunction if the transfer instruction is not executed or is not executed. Are latched when the reset signal 3 inside the microprocessor returns. After this, the microprocessor starts the operation after the reset operation in the same manner as a normal microprocessor.

The flag register 5 acts on the decoder 17 inside the execution unit 14, and when the content of the flag register 5 is "1", the "register rewriting function" is effective, so the register rewriting branch destination address is set to the register rewriting branch address. ROM storing destination address table and register contents
4 makes it possible to execute the transfer instruction from the register rewriting branch destination address latch 15. If the content of the flag register 5 is "0", the "register rewriting function" is invalid. Therefore, the register rewriting branch destination address is the ROM that stores the register rewriting branch destination address table and the register contents.
4 makes the transfer instruction from the register rewriting branch destination address latch 15 unexecutable, and if it is executed, it is executed as a no-operation instruction (MOP, NO, OPERATION), which affects the signal timing of other semiconductor integrated circuits. Don't give. To use the "register rewriting function", a microprocessor program executes a transfer instruction from the ROM 4 storing the register rewriting branch destination address and the register rewriting branch destination address table and register contents to the register rewriting branch destination address latch 15. . This transfer instruction is also executed when the register rewrite branch destination address is changed.

The address comparison circuit 6 compares the address sent to the memory interface in synchronization with the internal operation clock. When the address comparison circuit 6 detects an address equal to the address stored in the register rewrite branch destination address latch 15 in the address sent to the memory interface, it raises the register rewrite detection signal 7, clears the instruction queue 8, and sets the timing. A register rewriting request is transmitted to the control circuit 9. The register rewrite control circuit 2 receives from the address comparison circuit 6 the ROM address in which the register contents corresponding to the function of the peripheral device are registered,
The new register contents are transferred to the saving latch circuit of the register 10 in the microprocessor.

The timing control circuit 9 monitors the bus status of the microprocessor, and when the instruction being processed is completed at the time when the rewrite detection signal 7 rises, the timing control circuit 9 shifts from the saving latch circuit of the register 10 in the microprocessor to the inside of the microprocessor. The new register contents are transferred to the register 10 of. During this time, the bus control unit 11 prefetches the next instruction to be executed in the instruction queue 8. When the register contents are rewritten, the microprocessor starts executing the next instruction. In this embodiment, the register contents are directly transferred to the RO without using the register transfer instruction of the microprocessor to switch the function.
By transferring from M, the internal state can be changed in a short number of clocks by rewriting the register of the microprocessor.

FIG. 2 is a block diagram of the second embodiment of the present invention. When a reset pulse having a length of 4 clocks or more is input from the external reset terminal RESET1, the register rewrite control circuit 2 holds the reset signal 3 inside the microprocessor in the reset state, and the register rewrite branch destination (call destination: the same applies hereinafter). ) Dedicated A of ROM (or RAM, same below) that stores address table and register contents
The connection rewriting branch destination outside the microprocessor from the D bus 16 and the ROM 4 storing the address table and the register contents are tested for connection, and the ROM 4 storing the register rewriting branch destination address table and the register contents is connected to the dedicated AD bus 16. If not, the flag register 5 is set to "0" in order to invalidate the register rewriting function, the reset signal 3 inside the microprocessor is restored as in a normal microprocessor, and the normal operation is started after the reset operation. .

If the register rewriting destination address table and the ROM 4 storing the register contents are connected, first the flag register 5 is set to "1" to enable the register rewriting function, and the register rewriting branch destination address table is set. ROM which stores the register contents corresponding to the functions of the peripheral device branched or called in the control program of the peripheral device from the ROM 4 storing the register contents
The 8th to 8th register rewrite branch destination addresses in the internal address table are read out, and the register rewrite branch destination address table and the register contents are stored in the 8-stage register bank 13 corresponding to each register rewrite branch destination address through the DMA 12 for register content transfer. The contents of the eight registers at the head are transferred from the ROM 4 storing therein, and the reset signal 3 inside the microprocessor is restored.

The register rewrite branch destination address latch 15 is provided with a microprocessor so that the register rewrite branch destination address table 15 and the ROM 4 storing the register contents are connected to each other so that no malfunction occurs when the transfer instruction is not executed or is not executed. Reset address is latched when the reset signal 3 inside the microprocessor returns. After this, the microprocessor starts the operation after the reset operation in the same manner as a normal microprocessor.

The flag register 5 acts on the decoder 17 inside the execution unit 14, and when the content of the flag register 5 is "1", the "register rewriting function" is effective, so that the register rewriting branch destination address is changed to the register rewriting branch address. ROM storing destination address table and register contents
4 makes it possible to execute the transfer instruction from the register rewriting branch destination address latch 15. If the content of the flag register 5 is "0", the "register rewriting function" is invalid. Therefore, the register rewriting branch destination address is the ROM that stores the register rewriting branch destination address table and the register contents.
4 makes the transfer instruction from the register rewriting branch destination address latch 15 unexecutable, and if it is executed, it is executed as a no-operation instruction (MOP, NO, OPERATION), which affects the signal timing of other semiconductor integrated circuits. Don't give. To use the "register rewriting function", a microprocessor program executes a transfer instruction from the ROM 4 storing the register rewriting branch destination address and the register rewriting branch destination address table and register contents to the register rewriting branch destination address latch 15. . This transfer instruction is also executed when the register rewrite branch destination address is changed.

The address comparison circuit 6 compares the address sent to the memory interface in synchronization with the internal operation clock. When the address comparison circuit 6 detects an address equal to the address stored in the register rewrite branch destination address latch 15 in the address sent to the memory interface, it raises the register rewrite detection signal 7,
The instruction queue 8 is cleared and the register rewrite request is transmitted to the timing control circuit 9. The register rewrite control circuit 2 receives from the address comparison circuit 6 the address in the ROM in which the register contents corresponding to the function of the peripheral device are registered, and the address having the corresponding register contents is the register bank 13
If it exists in the data, the timing of the register bank 13 is switched in synchronization with the other unit according to the timing control circuit 9, and if there is no corresponding address, the register bank 13 in the microprocessor is currently used through the register content transfer DMA 12. The new register contents are transferred to the save latch circuit of the upper register bank with respect to the current register bank.

The timing control circuit 9 monitors the bus status of the microprocessor, and when the instruction being processed ends at the time when the rewrite detection signal 7 rises, the timing control circuit 9 shifts from the saving latch circuit of the register 10 in the microprocessor to the inside of the microprocessor. The new register contents are transferred to the register 10 of During this time, the bus control unit 11 prefetches the next instruction to be executed in the instruction queue 8. When the register contents are rewritten, the microprocessor starts executing the next instruction. In this embodiment, the register contents of the microprocessor are DMA-transferred from the ROM to the register bank and the register bank is rewritten while shifting the register bank without using the register transfer instruction of the microprocessor to switch the function. The internal state can be changed in a minimum of one clock, and the more registers are rewritten, the more registers are used in the register bank, and the loss time of register rewriting is reduced.

[0021]

As described above, according to the present invention, with respect to the microprocessor used for controlling the peripheral device used in the computer system, the register contents of the key microprocessor for setting the control condition of the peripheral device are set. By changing the efficiency of rewriting from the basic procedure of microprocessor operation, the loss time caused by register rewriting caused by using a microprocessor can be reduced, and simple hardware changes can significantly reduce the peripheral device. It can be speeded up quickly. Moreover, since software can be shared with an ordinary microprocessor, effective utilization of software assets can be expected.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of a microprocessor for controlling a peripheral device according to the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a block diagram of a conventional peripheral device control microprocessor.

[Explanation of symbols]

 1 external reset input terminal 2 register rewrite control circuit 3 reset signal 4 ROM 5 flag register 6 address comparison circuit 7 register rewrite detection signal 8 instruction queue 9 timing control circuit 10 register 11 bus control unit 12 register content transfer DMA 13 register bank

Claims (2)

[Claims] 1. A register which is provided in a circuit for controlling a peripheral device of a computer system and which can be rewritten without depending on a register transfer instruction of a microprocessor, a latch for rewriting according to the transfer instruction, and a register and a latch. A microprocessor for controlling a peripheral device, comprising: a rewriting unit, a unit for determining whether to rewrite a register and a latch, and a unit for measuring a timing for rewriting a register and a latch. 2. A means for supplying an address of a branch destination where the register needs to be rewritten and the contents of the register to be rewritten from the outside of the microprocessor, and rewriting control of the register and the latch is activated when the supplying means is not connected. 2. The peripheral device control according to claim 1, further comprising means for preventing, by hardware or software, a malfunction caused by the above and a malfunction caused by activation of the rewriting control of the register and the latch even when the software for the conventional microprocessor is executed. For microprocessor.