JPH0643581U - Semiconductor memory test equipment - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a semiconductor memory testing device that shortens the failure analysis time of a semiconductor memory. [Structure] Fail memory 4 for fetching fail data
A fail counter 50 for counting the number of failures. A second selector 20 having a plurality of bits and selecting any one bit from the output of the fail memory 4
A semiconductor memory testing device in which each of the fail counters 50 is equipped with.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a semiconductor memory test device, and more particularly to a semiconductor memory test device that shortens a failure analysis time of a semiconductor memory.

[0002]

[Prior art]

 A conventional example will be described with reference to FIG. Reference numeral 4 denotes a fail memory which is a part of the configuration of the semiconductor memory test apparatus. After the fail data is loaded into this fail memory, the content of the loaded fail data is read and the number of failures is counted by the fail counter 5. It should be noted that the semiconductor memory testing device fetches the fail data into the fail memory 4 and reads out the fetched contents of the fail data. However, since the configuration itself is not directly related to the gist of the present invention, its description will be omitted. Omit it.

Two types of addresses are supplied to the fail memory 4, one being a semiconductor memory test address for fetching fail data into the fail memory 4 and the other one being a read / write address of the fail memory 4. Any one of the addresses is switched and supplied to the fail memory 4. Since there is only one fail counter 5 that counts fail, the selector 2 selects the bit of the data to be counted according to the number of bits of the data to be counted. In this case, all bits can be ORed or any one bit can be selected.

[0004]

[Problems to be solved by the device]

 Since there is only one fail counter 5, when measuring a multi-bit semiconductor memory, it is necessary to switch the bits by the selector 2 for the number of bits of the semiconductor memory and count. A semiconductor memory having a × 4 bit configuration requires four times as long time as counting a fail as compared with a semiconductor memory having a × 1 bit configuration.

The present invention provides a semiconductor memory test apparatus that solves the above problems.

[0006]

[Means for Solving the Problems]

 A fail memory 4 for fetching fail data is provided, and a first selector 1 for switching an address at the time of a semiconductor memory test for fetching fail data to the fail memory 4 and an address at reading / writing of the fail memory 4 is provided. A semiconductor memory test apparatus is provided which includes a plurality of fail counters 50 for counting the number of fails, and each fail counter 50 has a second selector 20 for selecting an arbitrary 1 bit from the output of the fail memory 4. did.

[0007]

【Example】

 An embodiment of this invention will be described with reference to FIG. The output up to the fail memory 4 is the same as in the conventional example. That is, the selector 1 switches between an address at the time of a semiconductor memory test for fetching fail data into the fail memory 4 and an address at the time of reading / writing of the fail memory 4. This is the same as the conventional example up to the point where the contents of the fail memory 4 are read out after fetching the fail data into the fail memory 4 and the number of failures is counted by the fail counter 50.

The difference from the conventional example of the present invention is that a plurality of fail counters 50 are provided instead of one, and each of the plurality of fail counters 50 has a respective selector 20 between it and the fail memory 4. I have just equipped it. The selector 20 can select any one bit from the output data of the fail memory 4, and by selecting different bits for the fail counter 50 _{1 to the} fail counter 50 _n , a plurality of bits can be simultaneously selected. Fail data can be counted.

In the above description, the semiconductor memory test apparatus of the present invention is applied to a test of a semiconductor memory having a multi-bit configuration, but it can also be applied to a simultaneous measurement test of a semiconductor memory having a 1-bit configuration. it can. That is, the semiconductor memory test is generally performed at the same time. In this case, the fail memory is loaded with a plurality of 1-bit semiconductor memory failures that are simultaneously measured.

The first fail counter counts the fail of the semiconductor memory of the first 1-bit configuration, the second fail counter counts the fail of the semiconductor memory of the second 1-bit configuration, and the n-th fail counter. If the counter is configured to count the failures of the n-th 1-bit semiconductor memory, the same effect as in the case of testing a multi-bit semiconductor memory can be obtained.

[0011]

[Effect of device]

If, for example, nine fail counters 50 are provided, the data D ₀ to D ₈ are counted by the fail counters 50 _{1 to} 50 ₉ to read all the contents of the fail memory 4 once. Fail data can be counted. In the conventional example, all the fail data could not be counted unless the contents of the fail memory 4 were read 9 times. That is, the counting time of the file is shortened to 1/9. The fact that the fail counting time is reduced to 1/9 means that the counting operation time of the entire large-scale semiconductor memory test device is reduced to 1/9. It has great significance in improving efficiency.

[Brief description of drawings]

FIG. 1 is a diagram for explaining an embodiment of this invention.

FIG. 2 is a diagram illustrating a conventional example.

[Explanation of symbols]

 1 First Selector 4 Fail Memory 20 Second Selector 50 Fail Counter

Claims (1)

[Scope of utility model registration request] 1. A fail memory comprising a fail memory for fetching fail data, comprising: a first selector for switching an address at a semiconductor memory test fetching fail data to a fail memory and an address at a read / write operation of the fail memory 2. A semiconductor memory testing device, comprising: a plurality of fail counters for counting the number of each of the fail counters; and a second selector for selecting an arbitrary 1 bit from the output of the fail memory.