JPH0642712B2 - Image area separation device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image area separation device, and more particularly to an image for separating an image in which a halftone dot picture and a line drawing such as characters are mixed into a halftone dot picture area and a line drawing area. Area separation device.

[Conventional technology]

With the recent widespread use of facsimiles, there are increasing opportunities to transmit not only line drawings such as characters but also images including printed photographs. When printing a photograph, a halftone photograph is often used. When this halftone picture is input by facsimile, a moire pattern may occur during output. When a special binarization method for suppressing the occurrence of moire patterns is adopted, thin line breaks and unnecessary notches often appear around the line drawing portion. Therefore, in order to separate the two and apply the binarization method according to each,
Several image area separation devices for a halftone dot picture area and a line drawing area have been proposed. Conventionally, there is a method of separating a halftone picture area from a line drawing area depending on the presence or absence of an isolated area (closed area) peculiar to a halftone picture (Japanese Patent Application No. 61-070148), and two thresholds are used in this method. And processing the results separately and applying the logical sum of the results (Japanese Patent Application No. 61-174014 and Japanese Patent Application No. 6-174014).
No. 1-228609), by detecting the center position between each halftone dot and separating the halftone dot photo area from the line drawing area according to the presence or absence of its periodicity, etc. There has been proposed an image area separation device capable of performing separation with a certain degree of accuracy.

[Problems to be Solved by the Invention]

In general, the pixel densities of the image input device and the output device are not necessarily the same, and pixel density conversion is often performed. Pixel thinning is performed when the pixel density of the image input device is high,
When thinning is applied to a line drawing, a break may occur in a thin line. If the method of separating the halftone dot photo area from the line drawing area by detecting the center position between the halftone dots and the presence or absence of the periodicity is applied to this image, the halftone dots and the thin line drawing are When the thin line is cut in the adjacent portion, the line drawing area may be erroneously determined as a halftone dot area.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an image area separation device which solves the above-mentioned problems and prevents the line drawing area from being erroneously determined to be a halftone dot area even when pixels are thinned out.

[Means for Solving the Problems]

The image area separation device of the present invention secures the continuity of a binarizing unit that compares an input image signal with a threshold value and converts it into a binary image signal, and a continuous fine line drawing included in the binary image signal. Thin line drawing securing means, thinning means for thinning out the pixels of the image signal after the thin line drawing securing processing, and the center of a series of columns of black pixels and white pixels on the main scanning line from the image signal after the thinning processing. Halftone dot center detecting means for detecting, first storage means for storing the halftone dot center detection result as cycle information, and a predetermined area on the main scanning line from the cycle information stored in the first storage means. Cycle detection means for determining whether the predetermined area is a halftone dot picture area or a line drawing area according to whether or not a certain cycle exists, and a result of the judgment result being a halftone dot picture area. Is prioritized over the result of being a line drawing area and stored And a second storage unit that.

〔Example〕

 The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 10 (A) to (D) are signal pattern diagrams for explaining a process of processing an image signal in this embodiment. The image signal input from the terminal 101 is converted into a binary image signal by the binarization circuit 11. The binary image signal output from the binarization circuit 11 is, for example, 1/4 thinning with the pixel at the thinning position S as the thinning point when the thin line L is input in the pixel array as shown in FIG. 10 (A). 10B, the fine line portion having only one line of pixels cannot be reproduced when it is out of the thinning point, and a fine line break occurs. If separation is performed in this state, the portion may be erroneously determined to be a halftone dot, and the region may be mistakenly determined to be a halftone dot region. In the present embodiment, in order to prevent this error, one pixel in the sub-scanning direction is converted into two consecutive pixels so that one pixel can be reproduced without fail even after thinning. That is, as shown in FIG. 3, a thin line drawing ensuring circuit 12 provided with reference windows of 1 pixel in the main scanning direction and 2 pixels in the sub scanning direction.
When there is a level pattern of "black and white" (W1, B2, W3) using, the last "white" level (W3) is converted to "black" level (B3) (Fig. 10). Similarly, in the case of the pattern (C)) and vice versa, when there is a pattern of a level of “black and white”, the last “black” level is converted into a “white” level. Similarly, the same processing can be performed in the main scanning direction. By doing so, the signal is reduced to the thinning circuit 13
Thus, even when one pixel is thinned out in the main scanning direction and the sub-scanning direction, the fine line break does not occur (10th
(D)). After such processing, the halftone dot center detection circuit 1
According to 4, the case where both ends on one line are white pixels and all the pixels between them are black pixels, or the black pixels at both ends and all the pixels between them are white pixels,
It is determined whether or not any of the patterns shown in FIGS. (A) to (G) exists, and if there is, without distinguishing between the two,
The same information indicating the center position between both ends (hereinafter referred to as cycle information) is output. In the cycle information storage circuit 15,
The output (period information) of the halftone dot center detection circuit 14 is written in the position on the built-in image memory corresponding to the center of each halftone dot center detection pattern (FIGS. 4A to 4G). At this time, in consideration of the case where the halftone dot cycle fluctuates, the cycle information is output at two locations for all patterns other than FIG. 4 (A). By doing this, the halftone dot period becomes 4,5,4,5, ...
It becomes possible to detect the halftone dot period even with a fluctuation of about a pixel.

When viewed from one main scanning line, the cycle information written in the cycle information storage circuit 15 has a certain periodicity in a halftone dot area and does not have a certain periodicity in a line drawing area. There is a feature called. Utilizing this feature, in order to separate an image in which halftone pictures and line drawings such as characters are mixed into halftone areas and line drawing areas, as shown in FIGS. 5 (A) to (C), The period detection circuit 16 having the period detection reference pattern on one line detects whether or not there is periodicity. Here, for simplification, a case where it is determined to be a halftone dot area when there are four cycles of cycle information will be taken as an example. Of the patterns shown in FIGS. 5A to 5C, the pixels are referenced only by the period information input positions 1B to 10B, and the other unmarked portions are not referenced. The reference pixels are arranged at a constant interval with each reference pattern. Here, 6,8,1
Although three types of halftone dot intervals of 0 are performed, it is also possible to increase patterns of other periods. This makes it possible to detect whether or not halftone dots are present in the image of that area. Actually, it is detected whether or not the period information indicating the position of the halftone dot in the image exists at all positions of the reference pixels of the reference pattern, and if there is,
Since a halftone dot exists in the area in the detection pattern, "1" is output. If not, "0" is output (hereinafter, the output here is referred to as separation information). The separation information storage circuit 17 receives the output of the cycle detection circuit 16 and writes the separation information, which is the result of the cycle detection, in the corresponding position of the built-in image memory. At this time, writing is performed so that "1" has priority.
And finally, it outputs from the terminal 102.

FIG. 2 is a block diagram showing an example of the configuration of the thin line drawing ensuring circuit 12 in this embodiment, and FIG. 3 is a signal pattern diagram for explaining the operation. The binary image signal supplied from the binarization circuit 11 supplies signals for two scanning lines to the pixel column determination circuit (ROM) 92 by the one scanning line delay elements 91A and 91B. In the pixel column judging circuit 92, it is judged whether or not there is a level pattern of "black and white" or "black and white" in the reference window as shown in FIG. 3, and the judgment signal is sent to the selecting circuit 93. . In the selection circuit 93, as shown in FIG. 3, the third line of the reference window is converted from “white” to “black” or “black” to “white” according to the determination signal and output to the thinning circuit 13. Similarly, the same processing can be performed in the main scanning direction.

FIG. 6 is a block diagram showing an example of the configuration of the halftone dot center detection circuit 14 in this embodiment, and FIGS. 4A to 4G are signal pattern diagrams for explaining the operation. Here, for simplification, there are seven types of halftone dot center detection patterns used to know the halftone dot center position, as shown in FIGS. 4 (A) to (G). Of course, it is possible to increase the number of patterns beyond this. Two
The value image signal is supplied from the terminal 401. The signals output in parallel from the taps of the 1-pixel delay elements 41A to 41I connected in cascade are supplied to a read-only memory (ROM) 42. Here, the respective outputs of the one-pixel delay elements 41A to 41I correspond to 41A, 41B ... 41I in order from the leftmost pixel of each pattern in FIGS. 4 (A) to (G). ROM4
In Fig. 4, when both ends on one line are white pixels and all the pixels between them are black pixels, or when both ends are black pixels and all the pixels between them are white pixels, FIG. It is determined whether or not the pattern shown in (G) exists, and if it exists, "1" is output as the cycle information from the cycle information output position of the pattern among the terminals 1A to 5A.

FIG. 7 is a block diagram showing a configuration example of the cycle information storage circuit 15 in this embodiment. The terminals 1A to 5A shown in FIG.
The output terminal of the halftone dot center detection circuit 14 and the input terminal of the period information storage circuit 15 are connected to each other with the same reference symbols. Further, 0 is always supplied from the terminal 501. Period information is written from the input terminals of the OR gates 52A, 52B, 52C, 52D, and 52E to the image memory including the one-pixel delay elements 51A to 51O. This result is output from terminals 1B to 10B.

FIG. 6 is a block diagram showing an example of the configuration of the cycle detection circuit 16 in this embodiment, and FIGS. 5 (A) to 5 (C) are signal pattern diagrams for explaining the operation. Here, for simplification, there are three types of period detection reference patterns used to know the period of the halftone dots, as shown in FIGS. 5 (A) to (C). Of course, it is possible to increase the number of patterns beyond this. Terminal 1B-10
The output of the cycle information storage circuit 15 is supplied from B. At this time, the output terminals of the cycle information storage circuit 15 and the input terminals of the cycle detection circuit 16 are connected to each other with the same reference numbers. Further, FIGS. 5A to 5C show the positional relationship of pixels in the cycle detection reference pattern corresponding to the terminals 1B to 10B. In the ROM 71, it is judged whether or not there are 4 cycles of cycle information in the cycle detection reference pattern,
When it exists, it is regarded as a halftone dot area and "1" is output. At this time, the ROM 71 outputs the detection result of each cycle detection reference pattern separately from the terminals 703, 704, 705.
On the other hand, each output from the ROM 71 is given to an OR gate 72, and the OR gate 72 outputs "1" when at least one of the three types of period detection reference patterns is present. Output from 702.

FIG. 9 is a block diagram showing an example of the configuration of the separation information storage circuit 17 in this embodiment. Terminals 702 to 7 in this block diagram
From 05, the output of the cycle detection circuit 16 is supplied. At this time, the output terminal of the cycle detection circuit 16 and the separation information storage circuit 1
Input terminals 7 having the same reference number are connected to each other. Here, for the sake of simplicity, when the period is detected by the period detection circuit 16, the (length of the pattern in which the period is detected × 5) lines is set as a halftone dot area. Of course, the same can be done with other lengths and other numbers of lines. RO
From the input terminal of M81, refer to the cycle detection reference pattern (Fig. 5).
The detection results of (A) to (C)) are input separately.
Then, of the cycle detection reference patterns, the length of the cycle-detected pattern is output from the output terminal of the ROM 81 in pixel units. At this time, if a period is detected simultaneously by two or three types of period detection reference patterns, the one with a long pattern length is output. down·
When 1 is input to the terminal 702, the counter 82 outputs "1" by the number of pixels corresponding to the length of the cycle detection reference pattern given by the ROM 81 from that point. Terminal 80
0 is always supplied from 1 and 1 scanning line delay elements 83A to 83D
The image memory consisting of is stored with the result of cycle detection, that is, separation information. Each output of the image memory and the output of the down counter 82 are logically OR gated.
By connecting to each of 84A to 84E, "1" is written in the area of (length of period detection reference pattern x 5) lines. That is, the information of the halftone dot area is written with priority over the information of the line drawing area. The result is output from the terminal 802.

〔The invention's effect〕

As described above, the present invention effectively conveys the separation between the halftone dot area and the line drawing area even if the halftone dot photograph and the line drawing having an unpredictable number of lines and angles are mixed. By performing the thin line drawing securing process, which is a pre-process, there is an effect that the thin line in the character is not broken and the error in the line drawing area can be significantly reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1, FIG. 2, FIG. 6 to FIG. 9 are block diagrams showing one embodiment of the present invention, FIG. 3, FIG. 4 (A) to (G), and FIG. Fig. 5 (A)
(C) and FIG. 10 (A) to (D) are signal pattern diagrams for explaining the embodiment of the present invention. 11 ... Binarization circuit, 12 ... Thin line drawing securing circuit, 13
... thinning circuit, 14 ... halftone dot center detection circuit, 15 ...
Period information storage circuit, 16 ... Period detection circuit, 17 ... Separation information storage circuit, 41A to 41I, 51A to 51O ... 1 pixel delay element, 42, 71, 81 ... ROM (read-only memory), 52
A-52E, 72,84A-84E …… OR gate, 82 …… Down
Counter, 83A to 83D, 91A, 91B ... 1 scanning line delay element, 9
2 ... Pixel column determination circuit (ROM), 93 ... Selection circuit.

Claims (1)

[Claims] 1. A binarizing means for comparing an input image signal with a threshold value to convert it into a binary image signal, and a thin line drawing ensuring for ensuring continuity of unbroken thin line drawing included in the binary image signal. Means, thinning means for thinning out the pixels of the image signal after the thin line drawing ensuring processing, and halftone dot for detecting the center of a series of black and white pixels on the main scanning line from the image signal after the thinning processing A center detection unit, a first storage unit that stores the halftone dot center detection result as period information, and a certain period exists in a predetermined area on the period information main scanning line stored in the first storage unit. Depending on whether or not the predetermined area is a halftone dot picture area or a line drawing area, a cycle detecting means, and a result of the judgment result being a halftone dot picture area is a line drawing area. The second memorizing hand that stores it with priority over the result Image-area separation apparatus characterized by comprising and.