JPH0642558B2 - High-speed diode manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION With the recent rapid progress in the power semiconductor industry, a thyristor with a turn-off time of 5 μsec or less is emerging. When applied to a voltage source inverter, it is common to use a thyristor with a diode connected in antiparallel.
A diode used in antiparallel connection with a thyristor having a small turn-off time is required to have an element (element having a small reverse recovery charge) having a high-speed current interruption ability corresponding to the turn-off time ability of the thyristor. Reverse recovery charge
Since it is expressed by Qr = Tr x irp / 2, the following two characteristics are required for high speed diodes. Note that Tr is the reverse recovery time,
irp is the peak current during reverse recovery.

(1) Short reverse recovery time. That is, the peak voltage reapplied to the thyristor side during commutation is affected by the reverse recovery charge of the diode, and increases as the reverse recovery charge of the diode increases.Thus, a thyristor with a higher rated voltage is required. However, a diode having a large reverse recovery charge is not preferable.

(2) The peak current during reverse recovery is small and the di / dt is gentle (Soft Recovery). That is, when the diode has a steep di / dt characteristic during reverse recovery (Snap-off), the voltage re-applied to the thyristor during commutation is a voltage with a high dv / dt, and the thyristor dv / dt characteristic Therefore, a diode having a snap-off characteristic is not preferable in terms of thyristor application technology.

For the above reasons, it is desirable that the high speed diode used for the above-mentioned purpose has a soft recovery characteristic of di / dt at the time of reverse recovery and a short reverse recovery time.

The present invention has been made for the above purpose, and one embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is an explanatory diagram of a current waveform during reverse recovery of a diode having a snap-off characteristic, and FIG. 2 is an explanatory diagram of a current waveform during reverse recovery of a diode having a soft recovery characteristic.

Regarding the reverse recovery characteristics of the diode, the snap-off characteristics showing a short and steep change of the reverse recovery time Tr as shown in Fig. 1 and the long and gentle di of the reverse recovery time Tr as shown in Fig. 2. /
The difference in Soft Recovery characteristics, which indicates the change in dt, is related to the lifetime of the diode base material layer. For example, in the case of P-Ni-N ⁺ junction, the shorter the lifetime of the Ni layer, the shorter the reverse recovery time is, and the shorter the recovery time, the longer the recovery time of the Ni layer is. can get.

The present invention provides a region having a Snap-off characteristic in the thickness direction of a diode wafer made of a single silicon disk and a Soft Rec.
A diode region in which regions having overy characteristics are combined in series and a transistor region having Soft Recovery characteristics in parallel are further combined in this combined region in series, and a cathode short circuit, that is, lateral direction P ⁺ -N ⁺ provided on the cathode side By eliminating the carrier in the neutral region by using the junction potential difference of the junction, the reverse recovery time and the reverse recovery peak current are small.
This is a diode with ft Recovery characteristics.

This technical idea is disclosed in Japanese Patent Laid-Open No. 58-114467 by the present inventor. Since this diode does not have the buffer layer of the medium resistance layer, it cannot be made into the Pin structure and 2500V
It is disadvantageous to the above high-speed diodes. The present application is a fast diode that remedies this drawback.

FIG. 3 is a partial vertical sectional view of a high speed diode showing an embodiment of the present invention.

Reference numeral 1 is an anode electrode formed by aluminum vapor deposition, and 3 is P formed by diffusing P-type impurity gallium or aluminum.
Layer 4 is a high resistance Ni layer, 4'is a medium resistance N layer, 5 is a low resistance N ⁺ layer formed by selectively diffusing N-type impurity phosphorus, and arranging them in a distributed manner, 6 P ⁺ layer formed by diffusing Figure 7 (a) P-type multiple boron into N layer 4 "as shown in the later surrounded by N ⁺ layers 7 brazing metal, reinforcing support electrode 8 And 2 is a P ⁺ layer formed by diffusing P-type impurity boron into the P-layer 3. Here, the necessity of providing an N-type medium resistance layer will be described.

In FIG. 3, when there is no N-type medium resistance layer, there is a P-Ni-P ⁺ junction structure between the anode and the cathode, so the depletion layer is
When it spreads over the entire Ni layer, punch-through occurs and the pressure resistance is limited. This is a breakdown voltage in a general P-N junction structure. When the breakdown voltage is constant, comparing the P-N and P-N-N ⁺ junction structures, the thickness ratio of the N layer required when the specific resistance is the same is known to be 1 for the former and 0.7 for the latter, as is well known. Is.

That is, in the P-N-N ⁺ (pinned) structure, the N layer thickness is reduced by 30%. This reduction in thickness is a very advantageous method in terms of speeding up the high breakdown voltage element, and FIG. 3 shows a high speed diode utilizing this effect.

Figure 4 is a third i in the anode electrode vertical direction in FIG diode region ~ Lee sectional i.e. P ⁺ layer 2, P layer 3, Ni layer 4, N layer
It is explanatory drawing which showed the concentration distribution of the lifetime killer (Au) of each layer of 4 ', N ⁺ layer 5.

The concentration of the lifetime killer is near the P ⁺ -P-Ni layer (A in the figure)
Area is the largest, and then the central part of the Ni layer (area B in the figure)
There are many, and the least is near the N ⁺ -Ni layer (C region in the figure). FIG. 5 is a cross section taken along the line perpendicular to the anode electrode in the transistor region of FIG. 3, that is, P ⁺ layer 2, P layer 3, Ni.
It is explanatory drawing which showed the concentration distribution of the lifetime killer of each layer of layer 4, N layer 4 ', and P ⁺ layer 6. The concentration of lifetime killer is almost equal in the P ⁺ -P-NiN-P ⁺ layer. The high speed diode of the present invention is also characterized in that the concentration distribution of the lifetime killer shown in FIGS. 4 and 5 can be easily obtained by forming it with the configuration shown in FIG.

Next, the reverse recovery characteristics of the diode having the cathode short circuit shown in FIG. 3 and having the lifetime killer concentration distribution shown in FIGS. 4 and 5 will be described.

First, when a reverse voltage is applied to the diode region in the conducting state, the carriers in the conducting state move holes toward the anode electrode 1 and electrons toward the cathode electrode 8 around the P-Ni junction. On the other hand, recombination is performed depending on the lifetime killer concentration near the P-Ni junction and the carrier concentration decreases, and the vicinity of the P-Ni junction is depleted with a thickness according to the value of the reverse voltage. .

At this time, the thickness of the depletion layer expands from the joining surface of the P-Ni junction toward the Ni layer. Generally, the reverse voltage applied to the diode during switching is 1/5 to 1 of the rated voltage.
Since it is about / 20, it can be considered that the depletion layer thickness generated by the reverse voltage application conceptually extends to the central portion of the Ni layer or less.

Therefore, as the lifetime killer concentration in the depletion layer thickness is higher, the carrier in the depletion layer changes more rapidly, and the reverse recovery current also changes more rapidly.

The carrier that has moved to the outside of the depletion layer (from the center of the Ni layer to the N layer) moves to the region where the concentration of the lifetime killer is low, so at this location the carrier is gradually attenuated by recombination and the reverse recovery current is also gentle. The reverse recovery current becomes zero as time passes and the reverse recovery current becomes zero, and the reverse recovery time is determined through this process.

Next, the effect of the transistor region will be described.

Since the transistor region is a transistor having a P ⁺ -P-Ni-N-P ⁺ junction structure, a transistor current having a low current density flows in the ON state. When the reverse voltage is applied, the depletion layer spreads in the same manner as the diode.
As shown in Fig. 5, the transistor region has a low lifetime killer level and its area is small, so the reverse recovery current in this region shows a soft recovery characteristic with a small peak value, and the di ₂ / dt in the diode region is more moderate. Then Soft
Indicates the role that helps recovery.

Finally, the effect of cathode short circuit will be described.

It is a general method to control the lifetime to be small in order to speed up the diode. However, if this method is adopted, there is a drawback in that the device has a large ON current and a large current. As a method of improving this, the cathode short circuit (junction potential difference of the P-N junction formed in the lateral direction) of the present invention is used to promote the recombination of carriers, and the shortage caused by this is soft-doping of the lifetime killer. I have an idea to make up for it. If this is used, even a diode having the same reverse recovery time will have a smaller on-voltage and a smaller leakage current than a diode made mainly for lifetime killer control.

Since the short circuit of the cathode brings about the above-mentioned effect, it becomes a fast diode with improved on-voltage and leakage current.

Explaining the state of the reverse recovery current of the high speed diode of the present invention in some detail, the reverse recovery current at the time of switching in the diode region having the lifetime killer concentration distribution shown in FIG. 4 is the peak of the reverse recovery current when the reverse recovery current starts to flow. Snap-off characteristics that show a sudden change in current appear in the first half after the value has passed,
In the latter half of the period, a soft recovery characteristic showing a gradual current change appears, and a reverse recovery characteristic showing a two-step current change as shown by the solid line in FIG. 6 (a) can be obtained.

On the other hand, since the transistor region has a small current density in the ON state and a long lifetime, it exhibits a soft recovery characteristic with a small peak current value as shown by the broken line in FIG. 6 (a). The combined waveform of the reverse recovery currents in the diode and transistor regions is as shown in FIG. 6 (b).

The diode reverse recovery characteristic shows a snap-off characteristic di ₁ / dt
Region 9 having a large value and a region 9 ′ having a small di ₂ / dt exhibiting the Soft Recovery characteristic appear. The present application can suppress the di ₂ / dt of the region 9 ', which is particularly important in high-speed diodes, to be small.

Next, a manufacturing process of an embodiment of a method for manufacturing a high speed diode according to the present invention will be described with reference to FIGS. 7 (a), (b), (c) and (d).

The same reference numerals as in FIG. 3 indicate the same or corresponding parts.

Figure 7 (a) shows a silicon substrate with a specific resistance of 120 Ωcm (4 x
10 ¹³ atoms / cc) N-type silicon with a thickness of 0.27 mm and a diameter of 23 mm
Is used. P on one side of the silicon substrate in advance by diffusion method
The P layer 3 is formed with a surface concentration of about 5 × 10 ¹⁷ atoms / cc and a thickness of 50 μm using gallium or aluminium, which is an N-type impurity, and vapor-phase growth using phosphorus, which is an N-type impurity, as a dopant on the other surface. Resistivity of 1 Ω-cm (5 × 10 ¹⁵ atoms / c
c), N-type 4 ′ formed with a thickness of 20 μm is provided, and phosphorus of N-type impurity is used for the surface of the vapor phase growth method to obtain a surface concentration of about 1 × 10 ²¹ atoms / cc and a thickness of 15 μm of N. ^{The +} layer 5 is formed using a known oxide film and a selective diffusion technique using a photoresist technique, the Ni layer 4 has a thickness of 200 μm, and N ⁺
A silicon disk having an oxide film 10 selectively on the surface of layer 5 and on the outer periphery of the silicon substrate is prepared by using a known photoresist technique. When the degree of disorder of the crystal structure of the Ni layer was examined by a rocking curve by the X-ray two-crystal method with respect to the silicon disk at this point, almost no disorder of the crystal structure was observed in the Ni layer. The reason for this is that the atomic radius of silicon on one side of the Ni layer is 1.17Å, while the atomic radius of 107%.
It has a P layer in which gallium or aluminum having 1.26Å is diffused, and the other surface has an atomic radius of silicon.
Since 94% of the atomic radius of 1.10Å phosphorus forms a Ni layer in which phosphorus is selectively diffused, it is presumed that the crystal structure is not disturbed by absorbing the difference in atomic radius between both diffusion layers. It

Thus, it is impossible to obtain the concentration distribution of gold as shown in FIG. 4 even if the lifetime killer of gold is thermally diffused to a silicon disk that is almost a perfect crystal.

According to the present invention, in order to obtain a gold concentration distribution as shown in FIG. 4 by one thermal diffusion of gold at the time of forming a bond, a crystal structure disorder corresponding to the gold concentration distribution is previously induced in the thickness direction of the silicon disk. Then, it is intended to obtain the above-mentioned concentration distribution of gold by utilizing the property that many gold atoms are accumulated in the disordered portion of the crystal structure.

First, for the purpose of obtaining the gold concentration distribution in Fig. 4, the atomic radius is 1.
Boron (0.88Å) with a small atomic radius is deposited on the surface of the P layer formed with a low surface concentration (5 × 10 ¹⁷ atoms / cc) by diffusion of gallium or aluminum having 26 Å and a high surface concentration (about 10 ²⁰ atoms / cc). In order to diffuse, the influence of the boron atom is strengthened in terms of crystal structure, and it becomes easier to induce disorder of the crystal structure in the direction of the Ni layer than in the case of gallium or aluminum alone. However, if the P ⁺ layer is made too thick, the crystal structure is disturbed throughout the Ni layer, so it is necessary to harmonize the thickness relationship between the P ⁺ layer and the P layer.

Due to the above-mentioned reason, boron is formed at a surface concentration of 5 × 10 ²⁰ atoms / cc from the surface of the P layer 3 in FIG.
Diffusion of less than 1/3 of the layer, that is, about 15 μm, and P ^{+ in} Fig. 7 (b)
Formed 2.

Next, for the purpose of obtaining the gold concentration distribution of FIG. 5, FIG.
As shown in Fig. 7 (a), the N layer 4 "surrounded by the N ⁺ layer 5 faces P of Fig. 7 (b).
At the same time as the ⁺ layer 2 is formed, the surface concentration of boron is 5 × 10 ²⁰ atoms / cc.
Then, diffusion of about 15 μm was performed to form the P ⁺ layer 6 of FIG. 7 (b). The area ratio of N ⁺ 5 and P ⁺ layer 6 is designed to be P ⁺ / N ⁺ = 15%. Due to this boron diffusion, the final thickness relationship is 15 μm for the P ⁺ layer, 45 μm for the P layer, 180 μm for the Ni layer, and N
The layer is 30 μm and the N ⁺ layer is 25 μm. A new oxide film 10 is formed on the surfaces of P ⁺ layer 2 and P ⁺ layer 6 by the above-mentioned boron diffusion.

The degree of disorder of the crystal structure of the P layer 3 and the Ni layer 4, and the P ⁺ layer 6 and the Ni layer 4 was measured by the X-ray 2 measurement with respect to the silicon disk of FIG.
A rocking curve by the crystal method shows that the P ⁺ layer 2
It was found that a strong crystal disorder occurs from the P ⁺ layer 6 toward the Ni layer 4 and from the P ⁺ layer 6 toward the Ni layer 4. This crystal disorder is due to the diode region a in FIG.
In the cross section, it appears strongly near the P-Ni junction, and the Ni layer 4 causes N ⁺
It was found to decrease towards layer 5. On the other hand, the third
In the transistor region B to B cross section shown in the figure, it strongly appears near the P-Ni junction and decreases toward the Ni layer 4, and P ⁺ -Ni
It was also found that the junction strongly appeared near the junction and decreased from the P ⁺ layer 6 to the Ni layer 4.

The tendency of disorder of the crystal structure in the thickness direction of the silicon disk corresponds to the A and B regions of the gold concentration distribution of FIG. 4 in the cross section of FIGS.

Next, in order to shorten the reverse recovery time of the diode wafer of FIG. 7 (c), the oxide film 10 is selectively removed, and gold is vacuum-deposited on one side 2 (P ⁺ ) of the diode wafer. Is vapor-deposited, and selective diffusion of gold is performed by heat treatment at a temperature of 820 ° C. for 30 minutes. As a result of this heat treatment, the concentration distribution of gold in the portion corresponding to the cross section in FIGS. 3A to 3B is A, B, C shown in FIG.
An area is formed, and the concentration distribution of gold in the portion corresponding to the cross section of FIG. 3B shows a concentration distribution of less gold.

The reason why the regions A, B, and C in FIG. 4 appear in one thermal diffusion of gold corresponds to the above tendency of disorder of the crystal structure.
The reason for the decrease in area is that gold is gettered by the N ⁺ layer 5. Gold getter effect was formed by diffusing phosphorus
The N ⁺ layer is particularly effective and is one of the features of the present invention. Further, the reason why the distribution of FIG. 5 is obtained by one thermal diffusion of gold can be understood from the effect of preventing the diffusion of gold by the oxide film.

Since the lifetime killer concentration distribution in Fig. 5 is about 15% with respect to the area of the N ⁺ layer 5, the reverse recovery time can be shortened without impairing the effect of the lifetime killer concentration distribution in Fig. 4. it can.

Through the manufacturing process as described above, the gold concentration distribution showing three regions such as A, B and C shown in FIG. 4 and the gold concentration distribution shown in FIG. 5 can be realized.

After this heat treatment, as shown in FIG. 7 (d), a supporting electrode 8 made of tungsten and having the same diameter as the diode wafer is formed on the surfaces of the N ⁺ layer 5 and the P ⁺ layer 6 by using a metal braze 7 containing aluminum as a main component. It is placed via a heat treatment in an inert gas and fixed integrally. As a result, the N ⁺ layer 5 and the P ⁺ layer 6 are short-circuited with aluminum to form a cathode short-circuit structure. After that, with respect to the surface of the P ⁺ layer 2, the diameter of the anode electrode 1 becomes 15
An aluminum vapor deposition electrode having a thickness of 10 mm and a thickness of 10 mm is formed.

After the fixing is completed, the P-Ni junction, which is a voltage blocking junction, is shaped into a negative bevel by a spherical polishing method or the like, and then the bevel surface is chemically polished, a surface protective film is formed, and the like to complete a diode.

The diode thus manufactured has a rating of 150 A, 2
At 500 V, first, the reverse recovery time is about 1 μsec, and the current waveform at the time of the reverse recovery is a device showing two-stage di / dt characteristics as shown in FIG. 6 (b). I was able to.

The conditions for measuring the reverse recovery charge were a forward current of 300 A and a forward current drop rate of 50 A / μsec.

Table 1 compares the device manufactured according to this example with the device of the same rating which has been manufactured conventionally. As can be seen from Table 1, the device according to the present invention has a small reverse recovery charge despite having a high breakdown voltage of 2500 V, and dv / dt applied to the thyristor used in antiparallel connection with the diode.
It has become possible to manufacture excellent high-speed diodes with di ₂ / dt, which has a large influence on the withstand capability, reduced compared to conventional devices. Therefore, the effect of contributing to the application technology of thyristor is extremely large.

Next, when the on-voltages of the device of the present invention and the conventional device at a current of 150 A are compared, the former shows a value 0.7 V lower than the latter. When the same comparison was made for the leakage current at a withstand voltage of 2500 V, the former showed a value 15 mA lower than the latter.

In the present embodiment, the description has been given of the diode alone, but in other semiconductor devices in which the diode is compounded, for example, in a reverse reverse thyristor or a reverse reverse blocking thyristor in which the reverse conductive thyristor wafer and the diode wafer are integrated. It can be easily guessed by those skilled in the art that the above can also be used.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory diagram of a current waveform during reverse recovery of a diode having a snap-off characteristic, and FIG. 2 is an explanatory diagram of a current waveform during reverse recovery of a diode having a soft recovery characteristic. FIG. 3 is a partial sectional view of a high speed diode showing one embodiment of the present invention,
FIG. 4 is an explanatory diagram showing the gold concentration distribution in the cross section of the diode of the present invention in FIG. 3, and FIG. 5 shows the gold concentration distribution in the cross section of the diode of the present invention in FIG. Explanatory diagram shown,
FIG. 6 (a) is an explanatory diagram showing current waveforms during reverse recovery of the diode region and the transistor region, and FIG. 6 (b) is explanatory diagram showing current waveforms during reverse recovery of the present diode, FIG. FIG. 6 is a vertical sectional view showing a manufacturing process of an embodiment of the high speed diode of the present invention. 1 ... Anode electrode, 2,6 ... P ⁺ layer, 3 ... P layer, 4
... Ni layer, 4 ', 4 "... N layer, 5 ... N ⁺ layer, 6 ... P
⁺ Layer, 7 ... metal brazing material, 8 ... supporting electrode, 9 ... large area, 9 '... small area, 10 ... oxide film.

Claims (1)

[Claims] 1. A silicon substrate Ni made of a high-resistance N-type base material.
A P layer formed by diffusing P-type impurity gallium or aluminum is formed on one surface of the layer, and an N-type buffer layer of medium resistance is provided on the other surface. P having a low resistance N ⁺ layer which is a diode region formed by selectively diffusing
-Ni-N-N ⁺ junction and a plurality of small regions of P-Ni-N- which become a transistor region surrounded by the dispersedly arranged N ⁺ layers.
By diffusing P-type impurity boron on the P layer of the junction which has the P ⁺ junction and becomes the anode side of the diode wafer.
By providing a P ⁺ layer, P ⁺ -P-Ni-N-N ⁺ and P ⁺ -P-Ni-N-P ⁺
For the diode wafer with the junction formed, a lifetime killer is introduced from the P ⁺ layer surface of the diode region to reduce the reverse recovery charge, and a high concentration distribution of the lifetime killer is formed near the P-Ni junction in the diode region. and, and as lifetime killer concentration diode region than lifetime killer concentrations of the transistor region increases provided the concentration distribution difference between them, the cathode-side N ⁺ layer and the P ⁺
A method of manufacturing a high speed diode, characterized in that the layers are electrically shorted.