JPH0642539B2 - Logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to a logic circuit, and more particularly to a logic circuit including CMOS transistors and bipolar transistors.

(Prior Art) FIG. 8 shows a 2-input NAND circuit including a conventional CMOS transistor and a bipolar transistor (hereinafter referred to as Bi-CMOS transistor).

This 2-input NAND circuit has a first signal input terminal 1
Signal input terminal 3, output signal output terminal 5, first MOS
The transistor 7, the second MOS transistor 9, and the third
MOS transistor 11 and fourth MOS transistor 1
3, the first bipolar transistor 15, the second bipolar transistor 17, the first resistor 19, and the second resistor 2
1 (see Japanese Patent Application No. 63-35171 and Japanese Patent Application Laid-Open No. 59-11034).

The first MOS transistor and the second MOS transistor 9 are P-channel transistors, and
The OS transistor 11 and the fourth MOS transistor 13 are N-channel transistors, and the first bipolar transistor 11 and the second bipolar transistor 17 are NPN transistors.

The source of the first MOS transistor 7, the second MO
The source of the S transistor 9 and the collector of the first bipolar transistor 15 are connected to the positive power supply potential 22.

The drain of the first MOS transistor 7, the second M
The drain of the OS transistor 9, the base of the first bipolar transistor 15, and one end of the first resistor 19 are connected to each other.

The gate of the first MOS transistor 7 and the third M
The gate of the OS transistor 11 is connected to the first signal input terminal 1.

The gate of the second MOS transistor 9 and the fourth
The gate of the MOS transistor 13 is connected to the second signal input terminal 3.

The emitter of the first bipolar transistor 15, the other end of the first resistor 19, the third MOS transistor 11
And the collector of the second bipolar transistor 17 are connected to the output signal output terminal 5.

The source of the third MOS transistor 11 is the fourth M
It is connected to the drain of the OS transistor 13.

The source of the fourth MOS transistor 13 and the base of the second bipolar transistor 17 are the second resistor 21.
Are connected to one end of each.

The emitter of the second bipolar transistor 17 and the other end of the second resistor 21 are connected to the ground potential 24.

Table 1 below shows the logical operation of the gate shown in this conventional example.

The operation of Table 1 will be described below.

First, when either the first input signal or the second input signal is at the second potential level, either the first MOS transistor 7 or the second MOS transistor 9 is turned on, and the third MOS transistor is turned on. 11 or the fourth MOS transistor 14 is turned off.
As a result, the first MOS transistor 7 or the second MOS transistor
Through the transistor 9, the first bipolar transistor 1
A current flows through the base of No. 5 and the first resistor 19. Third MO
Since no current flows in the direction of the S transistor 11 and the fourth MOS transistor 14, these currents flow to the output terminal 5. Here, a potential difference is generated across the first resistor 19, which is the base of the first bipolar transistor 15.
When the built-in potential between the emitters is reached, the first
The bipolar transistor 15 is turned on, the collector current corresponding to the increased base current passes through the emitter and rapidly charges the load capacitance attached to the output terminal, while the second
Since the base accumulated charge of the bipolar transistor 17 is rapidly extracted by the second resistance and the second bipolar transistor 17 is rapidly turned off, no current flows between the collector and the emitter of the second bipolar transistor 17, and the output potential rapidly rises. To do. First bipolar transistor 1
When the base-emitter voltage of 5 becomes smaller than the built-in potential, the first bipolar transistor 1
5 turns off, but the first MOS transistor or the second M
The OS transistor 9 raises the output potential to the first power supply potential.

When the first input signal and the second input signal are both at the second potential level, both the first MOS transistor 7 and the second MOS transistor 9 are turned on, and the third MOS transistor 11 and the fourth MOS transistor are turned on. Since 14 is turned off, as the circuit operation, one of the first input signal and the second input signal is the second input signal.
The output becomes the first power supply potential, exactly as in the case of the potential level.

Both the first input signal and the second input signal are first
At the potential level, the first MOS transistor 7 and the second MOS transistor 9 are turned off, and the third MOS transistor 11 and the fourth MOS transistor 13 are turned on. As a result, when the output potential is at the first potential level, the accumulated charge of the load capacitance passes through the third MOS transistor 11 and the fourth MOS transistor 13,
The base of the bipolar transistor 17 and the second resistor 21
Flows to. When the potential difference across the second resistor 21 reaches the built-in potential between the base and the emitter of the second bipolar transistor 17, the second bipolar transistor 17 is turned on, and the load capacitance is rapidly discharged by the base current and the increased cotter current. To do. At this time, the first bipolar transistor 15 draws out the base accumulated charge by the first resistor 19 and turns off rapidly, so that no current flows between the collector and the emitter of the first bipolar transistor 15 and the output potential drops rapidly. When the base-emitter voltage of the second bipolar transistor 17 becomes equal to or lower than the built-in potential, the second bipolar transistor 17 turns off, but the third MOS transistor 11 and the fourth M transistor
The OS transistor 13 reduces the output potential to the second potential level through the second resistor 21.

FIG. 5 shows a Bi-CMOS two-input NAND of this conventional example.
It is a basic cell pattern top view of a logic circuit.

This basic cell pattern plan is for one input signal,
It is configured by using two MOS transistors. Hereinafter, this configuration is referred to as a double gate configuration.

The first MOS transistor is formed by a first aluminum wiring shown by a dotted line, a second aluminum wiring shown by a two-dot broken line, a contact hole that is a shaded portion in a square, and a via hole that is a double shaded portion in the square. 7, the second MOS transistor 9, the third MOS transistor 11, the fourth MOS transistor 13, the first bipolar transistor 15, the second bipolar transistor 17,
The first resistor 19 and the second resistor 21 are connected.

The first signal is transmitted through the via hole 23 corresponding to the first signal input terminal 1 through the second aluminum wiring to the first signal.
It is input to the MOS transistor 7 and the third MOS transistor 11.

The second signal passes through the via hole 25 corresponding to the second signal input terminal 3 and is connected to the second signal via the second aluminum wiring.
It is input to the MOS transistor 9 and the fourth MOS transistor 13.

The output signal is output by the second aluminum wiring through the via hole 27 corresponding to the output signal output terminal 5.

The first aluminum wiring 29 on the left side of the figure is a power supply line, and the first aluminum wiring 31 on the right side of the figure is a ground line.

The power supply line is connected to the well contact region 33, and N
The well is set to the power supply potential.

The ground line is connected to the substrate contact region 35 to bring the substrate to the ground potential.

(Problems to be Solved by the Invention) As described above, in the logic circuit using the conventional Bi-CMOS transistor, in the circuit operation, the source potential of the MOS transistor on the ground potential side involved in the fall operation is the ground potential. Since it is connected to the base potential of the side bipolar transistor, the potential rises by the built-in potential when the bipolar transistor is turned on. Therefore, the back gate bias effect on the MOS transistor between the output terminal and the ground potential and between the gate and the source are generated. Due to the voltage drop, the double gate structure, which should operate at a high speed, should not be used.

An object of the present invention is to provide a logic circuit using a Bi-CMOS transistor, which has a double gate structure and has a high-speed falling operation, which has two MOS transistors per input.

[Configuration of the Invention] (Means for Solving the Problems) The present invention relates to a Bi-CMOS circuit in which a plurality of MOS transistors are connected in parallel to form a logic gate.
Corresponding between the output signal output terminal and the ground potential in parallel with the ground potential side MOS transistor, the bipolar transistor and the impedance element involved in the fall of the totem pole type Bi-CMOS gate in which two bipolar transistors are connected in series. M of CMOS gate
Connect the OS transistor.

(Operation) With the above-described configuration of the present invention, the base potential of the bipolar transistor on the ground potential side rises above the ground potential, and the MOS transistor connected between the base and collector is connected.
The decrease in driving force due to the substrate bias effect of the transistor is reduced, and the logic circuit has a high-speed fall.

Embodiments Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of the first embodiment of the present invention. Here, a logic gate in a gate array is taken as an example. This circuit is an inverter, and has an input terminal 37 and an output terminal 3
9, a first MOS transistor 41, a first bipolar transistor 43, a first impedance element 45,
The second MOS transistor 47, the third MOS transistor 49, the second bipolar transistor 51, and the second impedance element 53 are provided.

The input signal of the first potential level (here, high potential level) or the second potential level (here, low potential level) is input to the input terminal 37.

The output signal of the first potential level or the second potential level is output from the output terminal 39.

The source of the first MOS transistor 41 is connected to the first power supply potential (here, the positive power supply potential) 22, and the gate is connected to the input terminal 37.

The collector of the first bipolar transistor 43 is connected to the positive power supply potential 22, and the emitter of the first bipolar transistor 43 is the output terminal 39.
And the base is connected to the first MOS transistor 41.
Of the first impedance element 45 and the drain of the first impedance element 45.

The second MOS transistor 47 has a drain connected to the output terminal 39, an emitter of the first bipolar transistor 43 and the other end of the first impedance element 45, and a gate connected to the input terminal 37 and the first MOS.
It is connected to the gate of the transistor 41.

The drain of the third MOS transistor 49 is the second
It is connected to the drain of the MOS transistor 47, the gate is connected to the gate of the second MOS transistor 47, and the source is the second power supply potential (here, low power supply potential) 24.
Connected to.

The second bipolar transistor 51 has a collector connected to the output terminal 39, an emitter connected to the ground potential, and a base connected to the source of the second MOS transistor 47.

Here, the first MOS transistor 41 is a first conductivity type MOS transistor (here, P channel MOS transistor), and the second MOS transistor 47 and the third MOS transistor 49 are second conductivity type MOS transistor (here, N channel). MOS transistor)
The first bipolar transistor 43 and the second bipolar transistor 51 are NPN transistors.

The first bipolar transistor 43 connected in series
And the second bipolar transistor 51 are referred to as a totem pole output stage.

Next, the operation of this circuit will be described using Table 2 below.

First, when the input terminal 37 is at the second potential level (low potential level), that is, at the time of rising, the first MOS transistor 41 is turned on, and the second MOS transistor 47 and the third MOS transistor 49 are both turned off. The first bipolar transistor 43 is turned on, the emitter current charges the load, and the output terminal becomes the first potential level. The second bipolar transistor 51 is off, while the base accumulated charge of the second bipolar transistor 51 is rapidly extracted through the second impedance element 53 and rapidly turned off, so that a through current flows to the totem pole output stage. Does not flow.
As a result, power consumption is suppressed.

When the input terminal 37 falls at the first level, the first MOS transistor 41 is turned off. Meanwhile, the second MOS transistor 47 and the third M
The OS transistor 49 is turned on. As a result, the load capacitance of the output terminal 39 is discharged. The charge stored in the base of the first bipolar transistor 43 is rapidly extracted between the base and the emitter by the first impedance element 45, the first bipolar transistor 43 is rapidly turned off, and a current flows to the totem pole output stage. Since there is no power consumption, power consumption is suppressed.

The second MOS transistor 47 is provided between the base and collector of the second bipolar transistor 51,
A current is supplied to the base of the second bipolar transistor 51 from the output terminal 39, and the second bipolar transistor 51 is turned on. Further, the load capacitance is discharged through the third MOS transistor 49, and the output terminal 39 rapidly becomes the second potential level.

In the present embodiment, since a current path is formed through the third MOS transistor 49 in the previous term, a back gate bias effect for increasing the potential by the built-in potential and a voltage drop between the gate and the source when the second bipolar transistor 51 in the previous term is turned on. It can be mitigated to achieve a faster fall operation.

That is, by using the conventional Bi-CMOS IC having the double gate structure, the driving force does not increase so much, and the use of the falling current path using the MOS transistor makes it possible to speed up the falling operation.

Further, since there is a MOS transistor which is not connected to the base of the second bipolar transistor 51 in the previous period, even if the power supply voltage is lowered due to the noise on the current line, it is possible to suppress the increase in the delay time at the rising / falling operation.

In the first embodiment, especially when the load of the output terminal 39 is a standard load (fanout number is about 6), the falling operation can be speeded up.

In the first embodiment, the third MOS transistor 49 is provided to perform CMOS operation to suppress power consumption,
Achieves high-speed fall operation and double gate MO
The falling characteristic of the Bi-CMOS gate including the S transistor is improved.

FIG. 2 is a basic cell pattern plan view of the inverter circuit of the first embodiment. In FIG. 2 showing this basic cell, a double gate structure is adopted, and a bipolar transistor can be shared with an adjacent basic cell.
3 shows a gate array in which a wiring region is specially provided.

The first MOS transistor is formed by a first aluminum wiring shown by a dotted line, a second aluminum wiring shown by a two-dot broken line, a contact hole in a hatched portion of a rectangle, and a via hole that is a double hatched portion in the rectangle. 41, the second MOS
A transistor 47, the third MOS transistor 49,
The first bipolar transistor 43, the second bipolar transistor 51, the first impedance element 4
5 and the second impedance element 53 are connected.

The input signal is transmitted through the via hole 55 corresponding to the input terminal 37 through the second aluminum wiring to the first MOS transistor.
It is input to the transistor 41, the second MOS transistor 47, and the third MOS transistor 49.

The output signal is output by the second aluminum wiring through the via hole 57 corresponding to the output terminal 39.

The first aluminum wiring on the left side of the figure is the power supply line 59, and the first aluminum wiring on the right side of the figure is the ground line 61.

The power supply line 59 is connected to the well contact region 63 and sets the M well at the power supply potential.

The ground line 61 is connected to the substrate contact region 65,
The substrate is at ground potential.

By configuring the inverter circuit as the front-side tight gate type gate array in this way, a Bi-CMOS gate array can be obtained which can form a logic circuit having a short layout wiring and a high degree of integration.

Further, the first impedance element 45 and the second impedance element 53 are diffused resistors in this case, and have an inverse L
It has a letter shape, and it is 2 depending on how to make a contact hole.
It is possible to take the resistance value of a step.

A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a circuit diagram of the second embodiment of the present invention. Here, a double-gate logic gate in a gate array is taken as an example. This circuit is a 2-input NAND circuit, and has a first signal input terminal 67, a second signal input terminal 69, and an output terminal 7.
1, a first MOS transistor 73, a second MOS transistor 75, a first bipolar transistor 77,
First impedance element 79, third MOS transistor 81, fourth MOS transistor 83, fifth MOS
The transistor 85 and the sixth MOS transistor 87,
It has a second bipolar transistor 89 and a second impedance element 91.

The first signal input terminal 67 has a first potential level or a second potential level.
The first signal of the potential level is input.

A signal of the first potential level or the second potential level is input to the second signal input terminal 69.

The output signal of the first potential level or the second potential level is output from the output terminal 71.

The first MOS transistor 73 has a source connected to the positive power supply potential 22 and a gate connected to the first signal input terminal 67.

The second MOS transistor 75 has a source connected to the positive power supply potential 22 and a gate connected to the second signal input terminal 69.

The collector of the first bipolar transistor 77 is connected to the positive power supply potential 22, the emitter is connected to the output terminal 71, and the base is connected to the drain of the first MOS transistor 73 and the drain of the second MOS transistor 75.

One end of the first impedance element 79 has the first MO
The drain of the S transistor 73, the drain of the second MOS transistor 75 and the base of the first bipolar transistor 77 are connected, and the other end is connected to the emitter of the first bipolar transistor 77 and the output terminal 71.

A drain of the third MOS transistor 81 is connected to the output terminal 71, an emitter of the first bipolar transistor 77 and the other end of the first impedance element 79, and a gate thereof is connected to the first signal input terminal 67 and the first MOS transistor. It is connected to the gate of 73.

The drain of the fourth MOS transistor 83 is connected to the third MOS transistor 81, and the gate thereof is the second signal input terminal 69 and the second MOS transistor 7.
5 gate. The drain of the fifth MOS transistor 85 is the output terminal 71, the emitter of the first bipolar transistor 77, the other end of the first impedance element 79, and the third MOS transistor 8.
The first signal input terminal 67, the gate of the first MOS transistor 73 and the gate of the third MOS transistor 81 are connected to the drain of the first MOS transistor 73.

The drain of the sixth MOS transistor 87 is the fifth
The source is connected to the source of the MOS transistor 85, the source is connected to the second power supply potential, and the gate is connected to the second signal input terminal 69, the gate of the second MOS transistor 75 and the gate of the fourth MOS transistor 83.

The second bipolar transistor 89 has a collector having the output terminal 71 and the first bipolar transistor 77.
The emitter of the first impedance element 79, the other end of the first impedance element 79,
The drain of the third transistor 81 and the fifth MO
It is connected to the drain of the S transistor 85, the emitter is connected to the ground potential 24 and the source of the fifth MOS transistor 87, and the base is connected to the source of the fourth MOS transistor 83.

One end of the second impedance element 91 has the fourth M
The source of the OS transistor 83 is connected to the base of the second bipolar transistor 89, and the other end is connected to the ground potential 24, the source of the sixth MOS transistor 87 and the emitter of the second bipolar transistor 89.

Here, the first MOS transistor 73 and the second MOS transistor 75 are P-channel transistors, and the third MOS transistor 81 and the fourth MO transistor are used.
S transistor 83, the fifth MOS transistor 85
And the sixth MOS transistor 87 is an N-channel transistor, and the first bipolar transistor 77
The second bipolar transistor 89 is an NPN transistor.

The first bipolar transistor 77 connected in series
And the second bipolar transistor 89 are referred to as a totem pole output stage.

Next, the operation of this circuit will be described using the following elements.

First, when one of the first signal and the second signal is at the second potential level, either the first MOS transistor 73 or the second MOS transistor 75 is turned on, and the third MOS transistor 81 and the One of the respective combinations of the fifth MOS transistor 85, the fourth MOS transistor 83, and the sixth MOS transistor 87 is turned off. Since the first bipolar transistor 77 is turned on and the second bipolar transistor 89 is turned off, the emitter current of the first bipolar transistor 77 charges the load and the output signal becomes the first potential level.

Since the base current of the first bipolar transistor 77 exists, a large collector current is generated, the load capacitance attached to the output terminal 71 is rapidly charged, and the output potential becomes the first potential level. On the other hand, the base accumulated charge of the second bipolar transistor 89 is equal to the second accumulated charge.
Since it is rapidly pulled out through the impedance element 89 and turned off rapidly, a through current does not flow in the totem pole output stage, so that power consumption is suppressed.

When both the first signal and the second signal are at the second potential level, both the first MOS transistor 73 and the second MOS transistor 75 are turned on, and the third MOS transistor 81, the fifth MOS transistor 85 and the Since the fourth MOS transistor 83 and the sixth MOS transistor 87 are all turned off,
The emitter current of the first bipolar transistor 77 charges the load capacitance and becomes the output signal first potential level.

When both the first signal and the second signal are at the first potential level, that is, at the time of rising, both the first MOS transistor 73 and the second MOS transistor 75 are turned off. The third MOS transistor 81, the fourth MOS transistor 83, the fifth MOS transistor 85, and the sixth MOS transistor 87 are all turned on, and the load capacitance of the output terminal 71 is discharged.
The base and emitter of the first bipolar transistor 77 are short-circuited via the first impedance element 79, the electric charge accumulated in the base is rapidly extracted, the first bipolar transistor 77 is rapidly turned off, and the totem pole output stage is formed. Since a through current does not flow into the device, power consumption is suppressed.

The third MOS transistor 81 and the fourth M transistor are provided between the base and collector of the second bipolar transistor 89.
A current is supplied to the base of the second bipolar transistor 89 through the OS transistor 83 by discharging the load capacitance, the second bipolar transistor 89 is turned on, and the output signal becomes the second potential.

In the second embodiment, the second bipolar transistor 8 is provided by providing a current path passing through the fifth MOS transistor 85 and the sixth MOS transistor 87.
The potential of the back gate bias of the third MOS transistor 81 and the fourth MOS transistor 83, which occurs because the potential rises by the built-in potential when 9 is turned on, and the potential drop between the gate and the source are alleviated, and the fall operation is accelerated. it can.

That is, since the driving force does not increase so much by using the Bi-CMOS IC having the dull gate structure, the fall operation can be speeded up by providing the fall current path using the MOS transistor.

Further, since there is a current path by the MOS transistor which is not connected to the base of the second bipolar transistor 89 but is connected to the ground potential, the delay time at the fall operation even if the power supply voltage is lowered due to the noise of the current source. The increase can be suppressed.

In this embodiment, particularly when the load of the output terminal 71 is a standard load (fanout number is about 6), the effect of speeding up the falling operation is great.

In the present embodiment, by providing the fifth MOS transistor 85 and the sixth MOS transistor 87 to perform CMOS operation, power consumption is suppressed, the fall operation is speeded up, and a Bi transistor having a four-transistor MOS transistor configuration is achieved. -Improving the falling characteristics of the CMOS gate.

Although the NAND circuit corresponding to the 2-input signal is described in the present embodiment, the NAND circuit corresponding to the 3-input signal is input in parallel with the ground side bipolar transistor as shown in FIG. By providing N-channel MOS transistors according to the number of signal input terminals,
The same effect as the second embodiment can be obtained.

That is, the third signal input terminal 93 to which the third signal is input
And each gate has the third signal input terminal 93
MOS transistor 95 and eighth MOS connected to
A transistor 97 and a ninth MOS transistor 99 are newly provided. The seventh MOS transistor 95 is connected in parallel to the first MOS transistor 73 and the second MOS transistor 75. The eighth MOS
The transistor 97 is connected in series with the fourth MOS transistor 83. The ninth MOS transistor 9
9 is connected in series to the sixth MOS transistor 87.

In this embodiment, the number of input terminals is not limited to two or three. That is, the first bipolar transistor 77
Depending on the number of input terminals between the base and collector of
A MOS transistor in which each gate is connected to each input terminal is provided in parallel, and a MOS transistor in which each gate is connected to each input terminal is provided between the base and collector of the second bipolar transistor 89 depending on the number of input terminals. Transistors are provided in series, and each gate is connected to each input terminal depending on the number of input terminals between the collector and emitter of the second bipolar transistor 89.
By providing S transistors in series, it is possible to obtain the same effect as in the case where there are two or three input terminals.

FIG. 5 is a basic cell pattern plan view of the 2-input NAND circuit of the first embodiment. FIG. 5 showing this basic cell shows a full gate type gate array which has a double gate structure and can share a bipolar transistor with an adjacent basic cell.

The first MOS transistor is formed by a first aluminum wiring shown by a dotted line, a second aluminum wiring shown by a two-dot broken line, a contact hole that is a shaded portion in a square, and a via that is a double line portion in the square. 73, the second MOS transistor 75, the third MOS transistor 81, the fourth
The MOS transistor 83, the fifth MOS transistor 85, the sixth MOS transistor 87, the first bipolar transistor 77, the second bipolar transistor 89, the first impedance element 79 and the second impedance element 91 are connected.

The first-order signal is input to the first MOS transistor 73, the third MOS transistor 81, and the fifth MOS transistor 85 through the second aluminum wiring through the via hole 101 corresponding to the first signal input terminal 67.

The second signal is input to the second MOS transistor 75, the fourth MOS transistor 83, and the sixth MOS transistor 87 via the second aluminum wiring through the via hole 103 corresponding to the second signal input terminal 69.

Through the via hole 105 corresponding to the output terminal 71,
It is output by the second aluminum wiring.

The first aluminum wiring 107 on the left side of the figure is a power supply line, and the first aluminum wiring 109 on the right side of the figure is a ground line.

The power supply line 107 is connected to the well contact region 111,
The N well is set to the power supply potential.

The ground line 109 is connected to the substrate contact region 113 to bring the substrate to the ground potential.

However, in the substrate gate structure, a 3-gate NAND circuit having a double gate structure cannot be considered, and therefore it is not shown in the layout diagram.

In this way, by constructing the 2-input NAND circuit in the full-tightness gate array, the Bi-CMO which can configure a logic circuit having a short layout wiring and a high degree of integration.
An S-gate array is obtained.

Further, the diffused resistors, which are the first impedance element 79 and the second impedance element 91, have an inverted L shape. Therefore, here, the first impedance element 79 has a lateral portion used as an impedance element in order to adjust the impedance value to half. For example, a plurality of impedance elements may be formed in the basic cell in which the impedance elements are arranged, and the impedance value may be adjusted by devising the connection method of these elements. When the resistance value of the first impedance element 79 is lower, the operation speed of the theoretical circuit is substantially the same, moreover, the efficiency of extracting the base charge is good and the power consumption can be reduced, and the resistance value of the second impedance element 91 is low. The higher the power consumption is, the more the power consumption is almost the same, and the operating speed of the logic circuit can be improved. Therefore, here, the resistance value of the first impedance element 79 is set to the second impedance 9
It is lower than the resistance value of 1.

Next, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 6 is a circuit diagram of the third embodiment of the present invention. Here is a 2-input NOR of a duffle gate in the gate array.
Take the gate as an example. In this circuit, the first signal input terminal 115
And the second signal input terminal 117 and the first MOS transistor 1
19, the second MOS transistor 121, the first bipolar transistor 123, the first impedance element 125, the third MOS transistor 127, and the fourth MOS transistor 1
29, a fifth MOS transistor 131, a sixth MOS transistor 133, a second bipolar transistor 135, and a second impedance element 137.

The first signal input terminal 115 has a first potential level or a second potential level.
The first signal at the potential level is input.

The second signal input terminal 117 has a first potential level or a second potential level.
The second signal at the potential level is output.

The first MOS transistor 119 has a source connected to the positive power supply potential 22 and a gate connected to the first signal input terminal 115.

The source of the first MOS transistor 121 has the first M
It is connected to the drain of the OS transistor 119 and its gate is connected to the second signal input terminal 117.

The first bipolar transistor 123 has a collector connected to the positive power supply potential 22 and an emitter connected to the output terminal.
119, the base of which is the second MOS transistor 1
Connected to the drain of 21.

One end of the first impedance element 125 has the second MO.
The drain of the S-transistor 121 and the base of the first bipolar transistor 123 are connected, and the other end is connected to the first bipolar transistor 123.
It is connected to the emitter of the bipolar transistor 123 and the output terminal 119.

The drain of the third MOS transistor 127 is connected to the output terminal 119, the emitter of the first bipolar transistor 123 and the other end of the first impedance element 125, and the gate is connected to the second signal input terminal 117.

The fourth MOS transistor 129 has a drain connected to the drain of the third MOS transistor 127 and a gate connected to the first signal input terminal 115.

The drain of the fifth MOS transistor 131 has the drain of the third MOS transistor 127 and the fourth MO transistor 127.
It is connected to the drain of the S transistor 129, the gate is connected to the second signal input terminal 117, and the source is connected to the ground potential 24.

The sixth MOS transistor 133 has a drain that is the drain of the third MOS transistor 127 and the fourth MOS transistor 127.
The drain of the transistor 129 and the drain of the fifth MOS transistor 131 are connected, the gate is connected to the first signal input terminal 115, and the source is the ground potential 24.
Connected to.

The second bipolar transistor 135 has a collector connected to the output terminal 119 and an emitter connected to the ground potential 2
4 and the base is the third MOS transistor 12
7 and the source of the fourth MOS transistor 129.

One end of the second impedance element 137 has the third MO
The source of the S transistor 127, the source of the fourth MOS transistor 129 and the second bipolar transistor 1
It is connected to the base of 35 and the other end is connected to the source of the fifth MOS transistor 131, the source of the sixth MOS transistor 133, the emitter of the second bipolar transistor 135 and the ground potential 24.

Here, the first MOS transistor 119 and the second MOS transistor 121 are P-channel transistors, and the third MOS transistor 127 and the fourth MO transistor are
The S-transistor 129, the fifth MOS transistor 131 and the sixth MOS transistor 133, and an N-channel transistor, and the first bipolar transistor 123.
Also, the second bipolar transistor 135 is an NPN transistor.

The first bipolar transistor 123 connected in series
And the second bipolar transistor 135 are collectively referred to as a totem pole output stage.

Next, the operation of this circuit will be described with reference to Table 4 below.

First, when one of the first signal and the second signal is at the second potential level, that is, when the signal falls, the first M
OS transistor 119 and the second MOS transistor 121
Is turned off, and the third MOS transistor 127, the fifth MOS transistor 131, and the fourth MOS transistor 127
Either one of the respective combinations of the MOS transistor 129 and the sixth MOS transistor 133 is turned off.
At this time, the first bipolar transistor 123 is turned off, the second bipolar transistor 135 is turned on, and the third MOS transistor is provided between the base and the collector.
A current is supplied to the base from the output terminal 119 by the 127 or the fourth MOS transistor 129, the second bipolar transistor 135 is turned on, and the output signal is the second signal.
It becomes the potential level.

When both the first signal and the second signal are at the second potential level, that is, at the time of rising, both the first MOS transistor 119 and the second MOS transistor 121 are turned on, and the third MOS transistor 127 and the third MOS transistor 127. The fourth MOS transistor 129, the fifth MOS transistor 131, and the sixth MOS transistor 133 are all turned off, and the first bipolar transistor 123 is turned on,
The load is charged by the emitter current of the first bipolar transistor 123, while the base accumulated charge of the second bipolar transistor 135 is charged by the second impedance element 1.
The second bipolar transistor extracted through 37
Since 135 turns off rapidly, the output signal is at the first potential level.

Both the first MOS transistor 119 and the second MOS transistor 121 are turned off when the first signal and the second signal both fall at the first potential level. The third MOS transistor 127, the fourth M
OS transistor 129, the sixth MOS transistor 131
And the sixth MOS transistor 133 is turned on, the second bipolar transistor 135 is turned on, the load capacitance of the output terminal 119 is discharged together with the fifth MOS transistor 131 and the sixth MOS transistor 133, and the second bipolar transistor 135 is turned on. Is turned on, and the output signal becomes the second potential level. On the other hand, in the first bipolar transistor 123, the base accumulated charge is rapidly extracted between the base and the emitter via the first impedance element 125, the first bipolar transistor 123 is rapidly turned off, and the totem pole output is generated. Since no penetrating current flows through the stage, power consumption is suppressed.

In the present embodiment, since a current path is formed through the fifth MOS transistor 131 and the sixth MOS transistor 133, when the second bipolar transistor 135 is turned on, the potential rises by the built-in potential, and the third MOS transistor 127 and The fourth MO
The back gate bias effect of the S transistor 129 and the gate-source voltage drop can be mitigated, and the fall operation can be speeded up.

That is, when the Bi-CMOS IC having the double gate structure is used, the driving force does not increase so much as expected, so that the fall operation can be speeded up by providing the fall current path using the MOS transistor.

Further, even if the power supply voltage is lowered due to the noise in the current path, the delay time at the time of rising / falling operation is reduced because the MOS transistor is not connected to the base of the second bipolar transistor 135 but is connected to the emitter. The increase can be suppressed.

In the third embodiment, especially when the load of the output terminal 119 is about the standard load (the fan-out number is about 6),
It is possible to speed up the falling operation.

In the third embodiment, the fifth MOS transistor 131 and the sixth MOS transistor 133 are provided, and the CMOS
By performing the operation, the power consumption is suppressed, the fall operation is accelerated, and the fall characteristic of the Bi-CMOS gate including the double-gate MOS transistor is improved.

Although this embodiment shows the case where the number of input terminals is two, the number of input terminals is not limited to two. That is, MOS transistors are connected in series between the base and collector of the first bipolar transistor 123 and each gate is connected to each input terminal in accordance with the number of input terminals, and between the base and collector of the second bipolar transistor 135. MOS with each gate connected to each input terminal according to the number of input terminals
Transistors are provided in parallel, and each gate is connected to each input terminal according to the number of input terminals between the collector and emitter of the second bipolar transistor 135.
By installing the OS transistor in parallel, the input terminal is
The same effect as in the case of individual pieces can be obtained.

FIG. 7 is a basic cell pattern plan view of the 2-input NOR circuit according to the third embodiment. FIG. 7 showing this basic cell shows a full gate type gate array which has a double gate structure and can share a bipolar transistor with an adjacent basic cell. Here, the impedance element is realized by a diffused resistor.

The first MOS transistor is formed by a first aluminum wiring shown by a dotted line, a second aluminum wiring shown by a two-dot broken line, a contact hole that is a shaded portion in a square, and a via hole that is a double line portion in the square. 119, the second MOS
Transistor 121, the third MOS transistor 127, the fourth MOS transistor 129, the fifth MOS transistor 131, the sixth MOS transistor 133, the first
The bipolar transistor 123, the second bipolar transistor 135, the first impedance element 125 and the second impedance element 137 are connected.

The first signal is input to the first MOS transistor 119, the fourth MOS transistor 129, and the sixth MOS transistor 133 through the second aluminum wiring through the via hole 139 corresponding to the first signal input terminal 115.

The second signal is input to the second MOS transistor 121, the third MOS transistor 127, and the fifth MOS transistor 131 via the second aluminum wiring through the via hole 141 corresponding to the second signal input terminal 117.

The output signal is the via hole 1 corresponding to the output terminal 119.
It is output through the second aluminum wiring through 43.

The first aluminum wiring on the left side of the figure is the power supply line 145, and the first aluminum wiring on the right side of the figure is the ground line 147.

The power line 145 is connected to the well contact region 149,
The N well is set to the ground potential.

However, in this basic gate structure, since a NOR circuit having a double gate structure and having three or more inputs is not considered, it is not shown in the layout diagram.

In this way, a 2-input N is used as a full-tightened gate array.
By forming an OR circuit, the wiring of the layout is short, and a Bi-CMOS capable of forming a highly integrated logic circuit.
A gate array is obtained.

The first impedance element 125 and the second impedance element 137 have an inverted L shape.

By configuring the inverter circuit, the NAND circuit, and the NOR circuit as described above, high-speed fall operation can be achieved.

[Effects of the Invention] As described above, according to the present invention, in a logic circuit using Bi-CMOS transistors, two MOSs are provided for each input.
It is possible to provide a high-speed logic circuit having a falling operation when a double gate structure including a transistor is used.

[Brief description of drawings]

1 is a circuit diagram of the first embodiment of the present invention, FIG. 2 is a plan view of a basic cell pattern of the first embodiment of the present invention, FIG. 3 is a circuit diagram of the second embodiment of the present invention, and FIG. FIG. 6 is a circuit diagram of a modification of the second embodiment of the present invention, FIG. 5 is a plan view of a basic cell pattern of the second embodiment of the present invention, and FIG. 6 is a circuit diagram of the third embodiment of the present invention. 7 is a basic cell pattern plan view of the third embodiment of the present invention, FIG. 8 is a circuit diagram of a conventional logic circuit, and FIG. 9 is a conventional basic cell pattern plan view. 1, 67, 115 ... First signal input terminal, 3, 67, 117 ...
... second signal input terminal, 5,39,71,119 ... output terminal, 7,9,41,73,75,95,119,121 ... first MOS transistor section 11,13,47,81,8
3,97,127,129 ... Second MOS transistor section, 4
9,85,87,99,131,133 ... Third MOS transistor section, 15,43,77,123 ... First bipolar transistor, 45,79,125 ... Second impedance element, 53,91,137. 2 impedance element, 22 ... first power source potential, 24 ... second power source potential, 3
7 ... input terminal, 93 ... third signal input terminal.

Claims (4)

[Claims] 1. A first conductive type first MOS transistor having an input terminal, an output terminal, a source connected to a first power supply potential, and a gate connected to an input terminal, and a collector connected to the first power supply potential. The emitter is connected to the output terminal, and the base is the first conductivity type first
A first bipolar transistor connected to the drain of the MOS transistor; a first impedance element having one end connected to the base of the first bipolar transistor and the other end connected to the emitter of the first bipolar transistor; A second conductive type second MOS transistor connected to the output terminal and having a gate connected to the input terminal; a drain connected to the output terminal, a gate connected to the input terminal, and a source connected to a second power supply potential. A second MOS transistor of the second conductivity type to be connected, a collector connected to the output terminal, an emitter connected to the second power supply potential, and a second base of the second conductivity type.
A second bipolar transistor connected to the source of the MOS transistor, one end connected to the source of the second conductivity type second MOS transistor and the base of the second bipolar transistor, and the other end connected to the second power supply potential And a second impedance element. 2. A k number of input terminals to which k number of signals (k ≧ 2) are input, an output terminal from which an output signal is output, a source is connected to a first power supply potential, and a gate is connected to the k number of K MOs of the first conductivity type connected to the input terminals respectively
A first MOS transistor portion having an S transistor, a collector connected to the first power supply potential, an emitter connected to the output terminal, and a base connected to the drains of the k first MOS transistors of the first conductivity type. First
A bipolar transistor, a first impedance element having one end connected to the base of the first bipolar transistor and the other end connected to the emitter of the first bipolar transistor, a collector connected to the output terminal, and an emitter connected to the second A second bipolar transistor connected to a power supply potential; a gate connected to the k input terminals which are different from each other, and a drain and a source connected to the emitter of the first bipolar transistor and the base of the second bipolar transistor. A second MOS transistor portion having k second MOS transistors of the second conductivity type connected in series between the gates, each gate being connected to the corresponding k different input terminals, and each drain and source being the output terminal And a second conductive material connected in series between the second power supply potential and A third MOS transistor portion having k type MOS transistors, and a second impedance element having one end connected to the base of the second bipolar transistor and the other end connected to the emitter of the second bipolar transistor. A logic circuit characterized by. 3. K input terminals to which k (k ≧ 2) signals are input, output terminals to which an output signal is output, a collector is connected to a first power supply potential, and an emitter is the output. A first bipolar transistor connected to the terminal, each gate connected to the different k input terminals, and each drain and each source connected in series between the first power supply potential and the base of the first bipolar transistor. A first MOS transistor portion having k MOS transistors of the first conductivity type connected to the first bipolar transistor, one end of which is connected to the base of the first bipolar transistor and the other end of which is connected to the emitter of the first bipolar transistor. A first impedance transistor, a second bipolar transistor having a collector connected to the output terminal and an emitter connected to the second power supply potential A second conductivity type in which each gate is connected to the k different input terminals, and each drain and each source are connected in parallel between the emitter of the first bipolar transistor and the base of the second bipolar transistor. Second MOS transistor portion having k MOS transistors, each gate is connected to the corresponding k different input terminals, and each drain and each source are connected to the output terminal and the second power supply potential. Second conductivity type k MO
A third MOS transistor portion having an S transistor, and a second impedance element having one end connected to the base of the second bipolar transistor and the other end connected to the emitter of the second bipolar transistor. circuit. 4. The invention as claimed in claim 1, which is configured as an all-in-one-type bipolar CMOS gate array, or (2) or when k = 2. 3) The described logic circuit.