JP2524027B2 - Semiconductor integrated circuit device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a high speed, low power consumption gate array L composed of MOS transistors and bipolar transistors.
The present invention relates to a semi-custom LSI including SI.

[0002]

2. Description of the Related Art A gate array LSI is used to manufacture an LSI having a desired electric circuit operation by making only a mask corresponding to a wiring out of a dozen or more photomasks used when manufacturing the LSI according to the development type. To do. It is said that the concept of this master slice method has been around since the 1960s.

The structure of the gate array LSI is shown in FIG.
The LSI chip 10 has a bonding pad and an input / output circuit area 14 on the outer periphery thereof, and inside the LSI chip 10, a basic cell row 12 in which basic cells 11 composed of elements such as transistors are arranged in the x-axis direction is repeatedly arranged across a wiring area 13. It has adopted the configuration. In order to obtain a desired electric circuit operation, one or several adjacent basic cells 11 are connected to form a NAND.
Form gates, flip-flops, etc. Then, one LSI is configured by wiring various logic gates formed by the plurality of basic cells 11 according to a logic diagram.

[0004]

In the conventional CMOS gate array LSI, the basic cell 11 is composed of a CMOS transistor. The CMOS circuit has a feature of low power consumption, but since the transfer conductance of the MOS transistor is small, there is a drawback that charging and discharging takes a long time and the speed becomes slow when the load capacitance is large.

In addition, the conventional bipolar gate array LS
In I, the basic cell 11 is composed of a bipolar transistor and a resistor. The bipolar circuit has a characteristic that the transfer conductance of the bipolar transistor is larger than that of the MOS transistor, and thus the speed is hard to decrease even if the load capacitance becomes large, but a large current is supplied to the low impedance circuit, There is a drawback that it consumes a large amount of electricity because it flows out.

To compensate for these drawbacks, bipolar
A MOS composite circuit has been proposed. Here, the layout of the inverter circuit of the bipolar / MOS composite circuit is IE
EETransactions on Electron Devices, Vol. ED-1
6, No. 11, 1969, p. 951. In this layout, there is no means for extracting the bipolar transistor, so that the circuit consumes a large amount of power and is not practical. Further, this layout is a layout of an inverter circuit alone, and is not used for a semi-custom LSI including a gate array LSI.

An object of the present invention is to provide an optimum layout of bipolar transistors and MOS transistors in a basic cell of a semi-custom LSI including a gate array LSI.

Another object of the present invention is DA (Design Automa).
The present invention provides a semi-custom LSI including a gate array LSI having a layout that facilitates automatic wiring processing.

[0009]

In order to achieve the above object, in a basic cell in which an output stage is composed of a bipolar transistor and a circuit for driving a logic and the bipolar transistor is composed of a MOS transistor, the longitudinal length of the gate of the MOS transistor is increased. It is characterized in that the bipolar transistor is arranged in the extension direction of the direction, or the bipolar transistor and the base charge extracting means are arranged.

Further, in order to achieve the above object, in the basic cell, the source of the MOS transistor or
Drain region and base region of the bipolar transistor
Area and the bipolar transistor is arranged in a direction perpendicular to the longitudinal direction of the gate of the MOS transistor, or the bipolar transistor and the base extracting means.
And wherein the placing and.

[0011]

Operation: Focusing on the low power consumption characteristics of MOS devices and the high speed characteristics of bipolar devices, a composite circuit is formed by combining both devices. That is, an output stage is composed of bipolar transistors, a logic circuit is composed of MOS transistors, and a circuit for driving the bipolar transistors is composed, and the composite circuit of the bipolar MOS and the means for extracting the base charge of the bipolar transistors. It is a basic cell. In this basic cell, by arranging the bipolar transistor in the longitudinal extension of the gate of the MOS transistor, the unused bipolar transistor can be effectively quoted as an internal wiring region for the configuration of the logic circuit. It is possible to minimize the increase in area due to the addition of. Further, when the bipolar transistor is arranged in the direction perpendicular to the longitudinal direction of the gate of the MOS transistor,
BiCMOS gate and CMO when constructing a logic circuit
Since the heights of the cells of the S gate can be made uniform, there is no unevenness in the wiring region, and automatic wiring processing in a DA (Design Automation) system becomes easy. Here, the cell height is the length in the vertical direction of the plan view of the wiring layout.

[0012]

EXAMPLES The present invention will be described in detail below with reference to examples.

FIG. 2 shows a totem pole output type 2-input NAN.
A D circuit is shown.

In FIG. 2, reference numeral 20 denotes a first NPN transistor (hereinafter abbreviated as NPN) 21 whose collector is connected to the power supply terminal 203 and whose emitter is connected to the output terminal 202.
Is a second NPN whose collector is connected to the output terminal 202 and whose emitter is connected to a fixed potential terminal having the ground potential GND,
201 is two input terminals, 22 and 23 are PMOSs whose gates are respectively different input terminals 201, and whose sources and drains are connected in parallel between the collector and base of the first NPN 20, respectively. 26 and 27 are
NMOSs 210 and 2 in which gates are connected to different input terminals 201, drains and sources are connected in series between the collector and the base of the second NPN 21, respectively.
Reference numeral 11 is a resistor provided between the base and the emitter of the first and second NPNs 20 and 21.

FIG. 12 shows the logical operation of this circuit.

First, when one of the inputs 201 is at "0" level, one of the PMOSs 22 and 23 is turned on and N
Either of the MOSs 26 and 27 is turned off. Therefore, the base potential of the first NPN 20 rises, and the first NPN 20
20 is turned on and the second NPN 21 is turned off by short-circuiting the base and the emitter via the resistor 211.
NPN20 emitter current charges the load and outputs 202
Becomes "1" level.

When both inputs 201 are at "0" level, P
Both the MOS 22 and 23 are turned on, and the NMOS 26,
Both 27 are turned off. Therefore, the operation is the same as the above, and the output 202 becomes "1".

On the other hand, when both of the inputs 201 are at "1" level, both the PMOS 22 and 23 are turned off and the NMOS
Both 26 and 27 are turned on. Therefore, the first NP
Since the base and the emitter of N20 are short-circuited via the resistor 210 to be turned off, and the base and the collector of the second NPN21 are short-circuited via the NMOSs 26 and 27, the second
A current is supplied to the base of the NPN 21 from the output 202, the second NPN 21 is turned on, and the output 202 becomes the “0” level. The resistors 210 and 211 shunt the base current when the NPN transistor is turned on, but function to extract the accumulated charge when the NPN transistor is turned off.

According to this circuit, a 2-input NAND circuit can be realized with a minimum configuration of CMOS and bipolar transistors. In addition, this circuit enables the NP with excellent high frequency characteristics.
Since N bipolar transistors are used, ultra high speed operation is possible.

Further, according to this circuit, a high input impedance and low output impedance circuit can be realized, and the power source 20
Since no conductive path is formed from 3 to ground, low power consumption characteristics can be realized.

FIG. 1 shows a layout pattern capable of suitably forming the bipolar / CMOS composite circuit, and FIG. 4 shows a vertical structure for facilitating understanding. 4 shows an inverter circuit, the common concept is represented by the same reference numeral as that in FIG.

The pattern of the buried layer 227 of FIG. 4 is omitted in FIG. 1 for simplicity. PMOSs 22 and 23, NPN 20, resistors 210 and 21 are provided in the isolation 212.
1 and the NMOSs 26 and 27, and the NPN 21 in the isolation 213. Gate electrode 2 of FIG.
The numbers of MOS transistors corresponding to FIG. P + region 219 and gate electrodes 220, 22
1 to PMOS 22 and 23, P well 214
N + region 223 and gate electrodes 221 and 220 to NM
The OS 26 and 27 are configured. N area 20 is P area 21
7, the N + region 218 in the P region 217 is the emitter, and the N + region 215 is the collector. The resistors 210 and 211 are composed of P regions 216 and 222, respectively. The NPN 21 is based on the P region 225 in the isolation 213 and has N + in the P region 225 as a base.
Region 226 serves as the emitter and N + region 224 serves as the collector.

Next, the connection between the respective elements will be described. N
The collector 215 of PN20 and the sources of PMOS22,23 are A
It is connected to the power supply by the I wiring 42. The mark x indicates the contact between the Al wiring and each element. The drains of the PMOS 22 and 23, the base of the NPN 20, and one end of the resistor 210 are A
They are connected to each other by the I wiring 228. The other end of the resistor 210 and the emitter 218 of the NPN 20 are Al wiring 229.
Connected by. The emitter 226 of the NPN 21, the one end of the resistor 211 and the P well 214 are connected to the ground potential by the Al wiring 43. The other end of the resistor 211 and NM
The source of OS27 and the base of NPN21 are Al wiring 23
Connected by 0 respectively. The drain of the NMOS 26 and the collector 224 of the NPN 21 are connected by the Al wiring 231. Although not shown, the emitter 218 of the NPN 20 and the collector 224 of the NPN 21 are connected by the Al wiring of the second layer.

From the layout pattern shown in FIG.
The pattern excluding the wiring and contacts is shown in FIG. That is, if the pattern of FIG. 5 is contacted with the Al wiring of FIG. 1, it becomes a 2-input NAND circuit, and if it is contacted with other Al wiring, an inverter or a 2-input NOR circuit can be constituted. Further, when forming a flip-flop or the like, the required number of patterns shown in FIG.
Therefore, by arranging FIG. 5 as a basic cell as shown in FIG. 3, a basic cell column of the gate array can be formed.

According to this embodiment, the basic cell is a composite circuit in which an output stage is composed of bipolar transistors and a circuit for driving logic and bipolar transistors is composed of MOS transistors and a means for extracting the base charge of the bipolar transistors. In this case, since the bipolar transistor is arranged on the extension of the gate of the MOS transistor in the longitudinal direction, or the bipolar transistor and the resistor 210 which is the base charge extracting means are arranged, the problem that occurs when a complicated logic circuit is formed The used bipolar transistor area or the base charge extracting means area can be effectively utilized as an internal wiring area for the logic circuit configuration. That is, an increase in area due to the addition of bipolar transistors can be substantially reduced, and a high-speed, low power consumption, high-density gate array LSI can be configured.

FIG. 6 shows a totem pole output type 2-input NAN.
Another example of the D circuit is shown. In the example of FIG. 2, the resistor 210 is the NMOS 240 and the PMOS 242, and the resistor 211 is the NM.
In this example, the OS 241 is used. The gate of the NMOS 240 is connected to the power supply terminal 203, and the drain and source thereof are connected to the base and emitter of the NPN 20, respectively.

The gate of the NMOS 241 has a power supply terminal 203.
In addition, the drain and the source are respectively connected to the base and the emitter of the NPN 21. The gate of the PMOS 242 is connected to the ground potential, and the drain and source thereof are connected to the emitter and base of the NPN 20, respectively. The same parts as those in FIG. 2 are indicated by the same numbers. The operation is almost the same as in FIG. NMOS 24
1 always operates in the non-saturated region and substitutes for the resistor 211. The PMOS 242 works to raise the output 202 to the power supply voltage when either of the inputs 201 is at "0" level, and the NMOS 240 operates when the output 202 is at "0" level.
Short the base and emitter of NPN20,
Is turned off to eliminate the through current and reduce the power consumption. According to this example, since the MOS transistor having a small channel width is used instead of the resistor, the degree of integration can be further improved.

FIG. 7 shows a layout pattern capable of suitably constructing this bipolar / CMOS composite circuit. In FIG. 7, the pattern of the buried layer and the like are omitted for simplicity. In the isolation 243, the PMOS 22, 23, 242,
The NPN 20 and the NMOSs 26, 27, 240, and 241 are configured, and the NPN 21 is configured in the isolation 244. The numbers of the MOS transistors corresponding to FIG. 6 are shown on the gate electrodes 253, 254, 255, 256. P +
PM from the region 249 and the gate electrodes 253, 254 and 255
The OSs 242, 23 and 22 are constructed, and the N + region 250 in the P well 245 and the gate electrodes 254 and 255 are connected to NMO.
S26 and 27 are configured. Also, the N + regions 251 and 252 in the P well 245 and the NMO from the gate electrode 256 are removed.
S240 and 241 are configured. NPN20 is P area 2
47 is the base, the N + region 248 in the P region 247 is the emitter, and the N + region 246 is the collector.

The NPN 21 is based on the P region 258 in the isolation 244, and N + in the P region 258 is used.
Region 259 serves as an emitter and N + region 257 serves as a collector.

Next, the connection between the respective elements will be described. N
The collector 246 of PN20, the sources of PMOS22,23 and N
The gates 256 of the MOSs 240 and 241 are connected to the power source by the Al wiring 42. In the figure, the mark x indicates the contact between the Al wiring and each element.

Drains of PMOS 22 and 23 and NPN2
The base 247 of 0 and the source of the PMOS 242 are connected by an Al wiring 260. The emitter 248 of the NPN 20 and the drain of the PMOS 242 are connected by the Al wiring 261. Drain of PMOS 242 and NMO
The drain of S26 and the source of the NMOS 240 are connected by the Al wiring 262. The drain of the NMOS 26 and the collector 257 of the NPN 21 are connected by the Al wiring 263. The source of the NMOS 27, the drain of the NMOS 241, and the base 258 of the NPN 21 are Al wiring 264.
Connected by each. NPN21 emitter 259
And the source of NMOS 241 and the gate 2 of PMOS 242
53 and the P well 245 are connected to the ground potential by the Al wiring 43.

From the layout pattern shown in FIG.
The pattern excluding the wiring and contacts is shown in FIG. That is, if the pattern of FIG. 8 is contacted with the Al wiring of FIG. 7, it becomes a 2-input NAND circuit, and if it is contacted with another Al wiring, an inverter or a 2-input NOR circuit can be constituted. Further, when forming a flip-flop or the like, the required number of patterns shown in FIG. Therefore, by arranging FIG. 8 as a basic cell as shown in FIG. 3, a basic cell column of the gate array can be formed.

According to the present embodiment, in a basic cell of a composite circuit in which an output stage is composed of bipolar transistors and a circuit for driving logic and bipolar transistors is composed of MOS transistors, the longitudinal direction of the gates of the MOS transistors is considered. Since the bipolar transistor is arranged on the extension of, the unused bipolar transistor region generated when forming a complicated logic circuit can be effectively used as an internal wiring region for the logic circuit configuration. That is, an increase in area due to the addition of bipolar transistors can be substantially reduced, and a high-density gate array LSI with high speed and low power consumption can be configured.

Two-input N with complementary output stage shown in FIG.
Another embodiment of the present invention in which an AND circuit can be suitably constructed is shown in FIG. 10, and a vertical structure is shown in FIG. 11 to facilitate understanding. First, the operation of FIG. 9 will be described. First, when either input 86 is at "0" level, either PMOS 82 or 83 is turned on and either NMOS 84 or 85 is turned off.
Therefore, the base potentials of NPN 80 and PNP 81 rise, NPN 80 turns on, and PNP 81 turns off, so the emitter current of NPN 80 charges the load and output 87 becomes "1" level. Next, when both inputs 86 are at "0" level, both PMOS 82 and 86 are turned on, and NM
Both the OSs 84 and 85 are turned off. Therefore, the operation is the same as the above, and the output 87 becomes the "1" level. On the other hand, when both inputs 86 are at "1" level, PMOSs 82 and 83
Both are turned off, and both the NMOSs 84 and 85 are turned on. Therefore, the base potentials of the NPN 80 and PNP 81 drop, the NPN 80 turns off, and the PNP 81 turns on, so that the output 87 becomes the "0" level. FIG.
Shows a layout pattern that can suitably configure FIG.
FIG. 11 shows the vertical structure. 11 shows an inverter circuit, the common concept is represented by the same reference numeral as that in FIG. FIG.
The numbers of the MOS transistors corresponding to FIG. 9 are shown on the gate electrodes 93 and 94 of FIG. P + region 91 and gate electrode 9
3, 94 form PMOSs 83 and 82, and N @ + region 92 and gate electrodes 93 and 94 form NMOSs 84 and 85. The NPN 80 has an N + region 96 as an emitter, a P region 95 as a base, and an N + region 99 as a collector. The PNP 81 uses the P + region 98 as an emitter, the N region 97 as a base, and the P + region 100 as a collector. Sources of PMOS 82 and 83 and NPN
The collector 99 of 80 is connected to the power supply by the VCC power supply line 101. Drains of PMOS 82 and 83, NPN 80 and P
An Al wiring 102 connects the bases 95 and 97 of the NP 81 and the drain of the NMOS 84. The collector 100 of the PNP 81 and the source of the NMOS 85 are connected to the GND by the GND power supply line 103. NPN80 emitter 9
6 and the emitter 98 of the PNP 81 are connected by an Al wiring 104, which serves as the output 87. Input 86 is gate electrodes 93, 94.

By using the required number of layout patterns shown in FIG. 10 and changing the Al wiring layer and the contact layer for each logic gate, an inverter or a NAND circuit can be constructed. Therefore, by arranging as shown in FIG. 3 the basic cell without the Al wiring layer and the contact layer as a basic cell, a basic cell column of the gate array is formed.

According to the present embodiment, in the basic cell of a composite circuit in which an output stage is composed of bipolar transistors and a circuit for driving logic and bipolar transistors is composed of MOS transistors, the longitudinal direction of the gate of the MOS transistor is considered. Since the bipolar transistors are arranged at a right angle to the cell, the heights of the cells of the bipolar gate and the MOS gate can be made uniform even when forming a complicated logic circuit, so that there is no unevenness in the wiring area.
In the DA (Design Automation) system, automatic wiring processing becomes easy.

The cell height is the BiCMOS gate C
The same effect can be achieved by using a MOS gate.

[0038]

As described above, according to the present invention, a composite circuit in which the low power consumption characteristics of a MOS device and the high speed characteristics of a bipolar device are combined, that is, an output stage is composed of bipolar transistors, and logic and bipolar transistors are composed of MOS transistors. In the basic cell that constitutes the circuit for driving the bipolar transistor, since the bipolar transistor or the bipolar transistor and the base charge extracting means are arranged in the extension direction of the longitudinal direction of the gate of the MOS transistor,
When constructing a logic circuit, an unused bipolar transistor region can be effectively used as an internal wiring region for constructing a logic circuit. Further, in the above basic cell, by disposing the bipolar transistor in a direction perpendicular to the longitudinal direction of the MOS transistor, the cell height of the gate can be made uniform to a predetermined height.

Therefore, it is possible to achieve a high-speed, low-power-consumption, high-density gate array LSI, and to construct a gate array LSI with a DA system that facilitates automatic wiring.

[Brief description of drawings]

FIG. 1 is a layout diagram of a basic cell showing an embodiment of the present invention.

FIG. 2 is a bipolar / CMOS composite 2-input NAND circuit diagram.

FIG. 3 is a schematic diagram of a gate array LSI chip.

FIG. 4 is a vertical structural view of FIG.

FIG. 5 is a layout diagram of a basic cell showing another embodiment of the present invention.

FIG. 6 is a bipolar / CMOS composite 2-input NAND circuit diagram.

FIG. 7 is a layout diagram of a basic cell showing another embodiment of the present invention.

FIG. 8 is a layout diagram of a basic cell showing another embodiment of the present invention.

FIG. 9 is a bipolar / CMOS composite 2-input NAND circuit diagram.

FIG. 10 is a layout diagram of a basic cell showing another embodiment of the present invention.

11 is a vertical structural view of FIG.

12 is a diagram showing a logical operation of the circuit of FIG.

[Explanation of symbols]

11 ... Basic cell, 20, 21 ... NPN transistor, 2
2, 23, 242 ... PMOS transistor, 26, 2
7, 240, 241 ... NMOS transistor, 210,
211 ... Resistance.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Ikuro Masuda Inventor Ikuro Masuda 3-1-1, Sachimachi, Hitachi City, Ibaraki Hitachi Ltd. Hitachi Research Laboratory (56) Reference JP-A-57-55776 (JP, A)

Claims (7)

(57) [Claims] 1. A bipolar transistor forming an output stage of the logic gate in at least one cell forming the logic gate, and an MO driving the bipolar transistor.
A semiconductor integrated circuit device having an S transistor and a means for extracting a base charge of the bipolar transistor, wherein the bipolar transistor is arranged in an extension direction of a gate of the MOS transistor in a longitudinal direction. 2. The MOS transistor according to claim 1.
Source or drain region and the bipolar transistor
A semiconductor integrated circuit device characterized in that it is arranged separately from the base region of the transistor. 3. The M according to claim 1 or 2,
In the extension direction of the gate of the OS transistor in the longitudinal direction,
A means to extract the base charge of the bipolar transistor
A semiconductor integrated circuit device characterized by being arranged. 4. At least one cell forming a logic gate.
The bipolar transistor that forms the output stage of the logic gate.
Transistor and MO for driving the bipolar transistor
In a semiconductor integrated circuit device having an S transistor
Te, the MOS transistor of the above-mentioned bipolar transistor
At the position perpendicular to the longitudinal direction of the gate of
The source or drain region of the S transistor and the above
Separated from the base area of the polar transistor
A semiconductor integrated circuit device characterized by the above. 5. At least one cell forming a logic gate.
The bipolar transistor that forms the output stage of the logic gate.
Transistor and MO for driving the bipolar transistor
The base of the S transistor and the bipolar transistor
To a semiconductor integrated circuit device having a means for extracting electric charge
Where the bipolar transistor is the MOS transistor
At the position perpendicular to the longitudinal direction of the gate of
The source or drain region of the S transistor and the above
Separated from the base area of the polar transistor
A semiconductor integrated circuit device characterized by the above. 6. The gate transistor according to claim 5, wherein the gate of the MOS transistor is straight with respect to the longitudinal direction.
The base charge of the bipolar transistor is pulled in the angular direction.
Semiconductor integrated circuit characterized by arranging punching means
apparatus. 7. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a gate array LSI.
And a semiconductor integrated circuit device.