JPH0642319B2 - Semiconductor memory - Google Patents

Description

The present invention relates to a semiconductor memory, and more particularly to a bit line load and a dummy bit line load in a memory having a single bit line structure.

(Prior Art) FIG. 4 shows a part of an ultraviolet erasable rewritable read-only memory (hereinafter abbreviated as EPROM) as an example of a semiconductor memory having a single bit line structure. Here, BL ... selects bit lines, MC ... selects a plurality of memory cell transistors connected to each bit line, and WL ... selects a plurality of memory cells in the same row in the array of memory cell transistors MC. , Column selection transistors connected in series to the bit lines BL, SLs being sense lines commonly connected to a plurality of bit lines BL via the transistors CS, and CL being CL. A potential clamping transistor inserted and connected to the sense line SL, LD is a bit line load transistor connected between the sense line SL and the V _DD power supply terminal, d ₀ , d ₁ ... Are column selection signals, and w ₀ , w ₁ ... Is a word line selection signal.

On the other hand, a dummy cell transistor DMC and a dummy cell selection transistor DCS are connected to the dummy bit line DBL, and a dummy potential clamping transistor DCL and a dummy bit line load transistor DLD are connected to the dummy cell line DSL. Then, one end of the sense line SL and one end of the dummy sense line DSL are connected to the differential input end of the bit line sense up (differential amplifier circuit) SA. Also,
A predetermined bias voltage is supplied from the bias circuit VB to the gates of the potential clamping transistor CL and the dummy potential clamping transistor DCL when reading data.

Note that V _DD is a power supply voltage and V _SS is a ground voltage.

At the time of data reading, one column selection transistor CS is selected, and one word line WL is selected and becomes high level, so that one memory cell M is selected.
Suppose C is selected. In this case, if the threshold voltage V _th of the selected cell MC is low, the potential of the sense line SL becomes lower than the potential of the dummy sense line DSL on the dummy cell DMC side, and the potential difference between the both potentials is amplified by the sense amplifier SA and sensed. High level is output as amplifier output. On the other hand, if V _{th of the} selected cell MC is high, the sense line SL
Becomes higher than the potential of the dummy sense line DSL, and the low level is output as the output of the sense amplifier SA. The potential clamping transistor CL is for maintaining the bit line potential at a relatively low potential in order to prevent erroneous writing in the memory cell when reading data. Usually, the dummy cell transistor DMC having the same size as the memory cell transistor MC is used, and the dummy cell DMC is set to have the same conductance as the memory cell MC when V _th is low. Since the sense line potential becomes lower than the dummy cell line potential when V _{th of the} selected cell MC is low, the bit line load L
It is necessary to design the conductance gm ₁ of D smaller than the conductance gm ₂ of the dummy bit line load DLD. However, if the difference in conductance is too large, the difference between the sense line potential and the dummy sense line potential becomes small when V _{th of the} selected cell MC is high, and the sense margin becomes small.

Next, the bit line load LD and the dummy bit line load DLD
Changes in the load ratio between, i.e., consider the change of the operating speed of the circuit of the fourth diagram of gm ₂ / gm _1. Assuming that the data read when the V _{th of} the selected cell is low is “1”,
If the data read when _Vth is high is defined as "0" read, the operating speed of the circuit depends on the load ratio as shown in FIG. That is, the operation speed for reading "1" is
The load ratio increases as the load ratio decreases, and becomes infinite at a load ratio of 1. On the other hand, the operation speed for "0" reading increases as the load ratio increases. As a result, in order to minimize the memory access time of FIG.
It is necessary to compare the load ratios at the intersections of the curves of the two operating characteristics. According to the experiment, this value is around 2.5, although it depends on the characteristics of the device. On the other hand, the time required for the sense operation of the sense amplifier SA is the sense line SL.
In order to speed up the sensing operation, it is necessary to reduce the above capacitance depending on the parasitic additional capacitance of. For this reason, the bit line load LD is designed to have the channel length of the minimum design rule, and further, the conductance needs to be reduced in consideration of the matching with the conductance of the memory cell, so that the channel width is also reduced. It is designed to be small, and the pattern layout of this bit line load transistor DL is formed as shown in FIG. 6 (a). Further, the pattern layout of the dummy bit line load transistor DLD is formed as shown in FIG. 6 (b), and the first transistor QA corresponding to the bit line load transistor and the additional second transistor QB are added. It is connected in parallel. In FIGS. 6A and 6B, S is a source region, G is a gate electrode, D is a drain region, 61 is a source contact, 62 is a source wiring, and 63 is a source line.
Is a drain contact, 64 is a drain wiring, and L is a channel length.

However, with the miniaturization of the element, the cell is miniaturized, and as the load is miniaturized, the channel width W of the element is
The linearity with respect to the channel length L cannot be maintained, and the error has come to vary between manufacturing lots and memory chips. The cause of this is the short channel effect due to the channel length variation ΔL, and the narrow channel effect due to the pattern conversion difference ΔW and the channel width variation ΔW 'which are shown by the dotted lines in FIGS. 6 (a) and 6 (b). To be As a result, the linearity of the W / L of the additional load transistor QB with respect to the W / L of the transistor QA corresponding to the bit line load transistor disappears, and the load ratio g
There is a problem that m ₂ / gm ₁ deviates from the optimum design value, and this load ratio varies between lots and chips, and the "1" reading speed and the "0" reading speed become unbalanced. Has occurred.

In order to correct the imbalance of the operating speeds of the "1" reading and the "0" reading, the values of L and W that are sufficiently large so that the ΔL, ΔW, and ΔW 'can be ignored, that is, 1.0 μm design rule, for example. In that case, a load transistor having L and W of about 4.0 μm may be used, but with this, the parasitic capacitance of the sense line and the dummy sense line increases, which essentially causes deterioration of access time.

(Problems to be Solved by the Invention) As described above, according to the present invention, the load ratio between the bit line and the dummy bit line varies from lot to lot or from chip to chip and deviates from the optimum design value. It was made to solve the problem that the operation speed becomes unbalanced with 0 "reading, and the variation of the load ratio is small, and" 1 "reading,
It is an object of the present invention to provide a semiconductor memory in which an imbalance in the operation speed of "0" reading is unlikely to occur, and an increase in parasitic capacitance due to a bit line load is small, and an adverse effect on the operation speed due to the increase is not substantially caused. To do.

[Structure of Invention]

(Means for Solving the Problem) According to the present invention, data reading is performed by sense amplification of a potential difference between a read potential from a memory cell connected to a bit line and a read potential from a dummy cell connected to a dummy bit line. In the semiconductor memory for carrying out the above, a plurality of transistors are respectively connected in parallel as a load of the bit line and a load of the dummy bit line, and a plurality of transistors for the bit line load and a plurality of dummy bit line loads are formed. It is characterized in that each transistor is formed of one or more kinds of transistors which are the same.

(Operation) According to the bit line load transistor and the dummy bit line load transistor formed as described above, even if the pattern conversion difference, the channel length variation, and the channel width variation occur due to the miniaturization of the element, The load ratio as a whole is always constant, and the imbalance of the operating speed between "1" reading and "0" reading is unlikely to occur. Moreover, the size of the load transistor does not need to be particularly large in order to reduce the influence of the above variations, and the bit line load capacitance does not unnecessarily increase, so that the operating speed is hardly adversely affected.

Embodiment An embodiment of the present invention will be described in detail below with reference to the drawings.

FIGS. 1 (a) and 1 (b) show pattern layouts of the bit line load transistor LD and the dummy bit line load transistor DLD used in the EPROM as shown in FIG. The bit line load transistor LD and the dummy bit line load transistor DLD each include a plurality of MOS transistors connected in parallel, and are each formed of the same one type or two or more types of transistors. Here, the transistors LD and DLD have exactly the same channel length L, channel width W, contact size,
The pattern layout is shown in the case where the load ratio gm ₂ / gm ₁ consists of one type of transistor having a transistor size and orientation and is 2.5. That is, the bit line load transistor LD includes two P-channel transistors P1 and P2.
Are connected in parallel, and the dummy bit line load transistor DLD has five P-channel transistors P3 to P7 connected in parallel. Here, S is a source region, G is a gate electrode, D is a drain region, 11 is a source contact,
Reference numeral 12 is a source wiring, 13 is a drain contact, and 14 is a drain broken line.

According to the pattern layout as described above, the pattern exchange difference, the variation in the channel length due to the miniaturization of the element,
Even if channel width variations occur in individual devices,
The overall load ratio is always 5/2 (= 2.5). In this case, since the number of dummy bit line load transistors DLD is large, the dummy bit line DBL in FIG.
However, since the potential of the dummy bit line hardly changes during the operation of the memory, the access time of the memory does not decrease. Further, the increase in the load capacitance by the bit line load transistor LD is small, and the adverse effect on the operation speed is hardly caused by this.

When the load ratio in the above embodiment is set to 233, for example, the number of bit line load transistors should be three and the number of dummy bit line load transistors should be seven.

Further, if the bit line load transistor LD and the dummy bit line load transistor DLD are formed of the same two or more types of transistors, the number of elements required to obtain a desired load ratio may be small. For example, load ratio 4/3 is 1
In the case of realizing with a kind of transistor, a total of seven transistors are required for the bit line load and four transistors for the dummy bit line load.
As shown in (a) and (b), as the bit line load LD, one P-channel transistor P11 having a channel width of 2W and one P-channel transistor P having a channel width of 4W are used.
12 are connected in parallel, and two P-channel transistors P13 having a channel width of 2 W are provided as dummy bit line loads DLD,
If P14 and one P-channel transistor P15 having a channel width of 4 W are connected in parallel, the number of transistors used will be five.

In an actual EPROM, as shown in FIG. 3, between the bit line load transistor LD and the V _DD power supply end and between the dummy bit line load transistors DLD and V D in order to prevent consumption of the bit line current in the standby state. P-channel transistors P31 and P3 for switching, which are gate-controlled by the chip enable signal ▲ ▼ with the _DD power supply terminal
2 is often inserted. In addition, the sense lines SL and V _SS
An N-channel transistor N for pull-down (for preventing floating), which is gate-controlled by the signal ▼ described above, between the end and between the dummy sense line DSL and V _SS.
31 and N32 are inserted. Therefore, when the ▲ ▼ signal is at high level (standby state), the transistor P
31 and P32 are turned off, the load current is turned off, the transistors N31 and N32 are turned on, and the sense line SL is turned on.
And the dummy sense line DSL becomes the ground potential. Also,
When the signal is low level (active state), the transistors P31 and P32 are turned on, the load current can flow, and the transistors N31 and N32 are turned off. In this case, since the conductances of the transistors P31 and P32 are designed to be sufficiently larger than the equivalent conductances of the load transistors LD and DLD, it is the load transistors LD and DLD that actually act as loads on the bit lines and the dummy bit lines. However, it is not the switching transistors P31 and P32. Therefore, the switching transistors P31 and P32 are connected to the load transistor L.
Unless the required gm ratio of D and DLD is maintained, it is not always necessary to design according to this gm ratio.

Note that the present invention is not limited to the EPROM of the above-described embodiment, and has a single bit line structure for reading cell data by comparing the potential read from the memory cell to the single bit line with the potential read from the dummy cell. It is generally applicable to a semiconductor memory having the same.

〔The invention's effect〕

As described above, according to the semiconductor memory of the present invention, the variation in the load ratio between the bit line and the dummy bit line is small,
Since there is little imbalance in the operating speed of "1" reading and "0" reading, and the increase of the parasitic capacitance due to the bit line load is small, there is almost no adverse effect on the operating speed. It is effective when applied to. In addition, it is possible to insert and connect in series a transistor for standby control, which has a sufficiently large conductance with respect to the load of the bit line and the load of the dummy bit line, thereby preventing the bit line current consumption during standby. You can

[Brief description of drawings]

1 (a) and 1 (b) are diagrams showing an example of a pattern layout of a bit line load transistor and a dummy bit line load transistor in an EPROM according to an embodiment of the present invention, and FIGS. 2 (a) and 2 (b). Shows another example of the pattern layout, FIG. 3 is a circuit diagram showing an example of actual use of the load transistors of FIGS. 1 (a) and (b), and FIG. 4 is a circuit showing a part of EPROM. 5 and 5 are characteristic diagrams showing the relationship between the circuit operation speed and the load ratio between the bit line and the dummy bit line in the EPROM of FIG. 4, and FIGS. 6 (a) and 6 (b) are the bit lines of the conventional EPROM. It is a figure which shows the pattern layout of a load transistor and a dummy bit line load transistor. MC: memory cell, DMC: dummy memory cell, BL
... bit line, DBL ... dummy bit line, SL ... sense line, DSL ... dummy sense line, LD ... bit line load, DLD ... dummy bit line load, SA ... sense amplifier, P1 to P7, P11-P15, P31, P32 ...
P-channel transistor.

Claims (2)

[Claims] 1. A semiconductor memory that sense-amplifies a potential difference between a potential read from a memory cell on a bit line and a potential read from a dummy cell on a dummy bit line to read data. A plurality of transistors are connected in parallel as the load of the dummy bit line, and the plurality of transistors for the bit line load and the plurality of transistors for the dummy bit line load are the same type or two or more types respectively. A semiconductor memory characterized by being formed by. 2. A standby control switch transistor having a conductance sufficiently larger than the equivalent conductance of the entire transistor with respect to the load of the bit line is connected in series, and the entire transistor with respect to the load of the dummy bit line. 2. The semiconductor memory according to claim 1, wherein a switching transistor for standby control having a conductance sufficiently larger than the equivalent conductance of is connected in series.