JPH0642234B2 - Parallel processing system - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processing system capable of handling intelligent processing based on a distributed knowledge base and control elements that perform advanced motion control arithmetic processing, and more particularly, human-type intelligent processing. The present invention relates to a parallel processing system suitable for intelligent control of an intelligent mechanical system including a plurality of control elements such as a robot.

[Background of the Invention]

A conventional parallel processing system, as shown in pages 105 to 126 of the April 11, 1983 issue of the Nikkei Electronics magazine, is a vector processor dedicated to scientific and technological calculations and a multi-instrument dedicated to special purpose applications. Relaxation stream multi data stream MIMD (Multi
-It is currently in practical use as a dedicated system for very limited purposes such as an instruction stream (multi-data stream) type parallel processing system. In addition, in order to significantly improve the parallel processing performance, it is considered essential for a technique to efficiently combine a large number of processor elements and perform parallel processing efficiently. However, conventional systems
Parallel processing as shown in MPP (FIG. 18) for satellite image processing and PAXS-129 (FIG. 19) for simulation of continuums and fields shown on pages 122 to 124 of the above-mentioned literature example. The processor elements that make up the system consist of one processor, and the connection of the processor elements is fixed according to the processing target, and a dedicated coupling configuration is adopted. Other processor elements output from each processor element Since the number of communication joints for connecting to and from is limited to two or four, it is considered that it can only communicate with related processor elements in the surroundings, and is not suitable for global and general-purpose processing. . However,
The parallel processing system for intelligent processing that will be required in the future has a complicated and diverse content of processing, so that it is a general-purpose MIMD.
It is necessary to have a hardware architecture capable of parallel processing by the method. In addition, most conventional systems perform repeated calculations of scientific calculations, simulations, and a large amount of similar processing, and perform advanced control calculation processing based on knowledge and intelligence desired in the future in real time, and intelligent control. Considering to control the target,
At present, there is no intelligent parallel processing system for control.

[Object of the Invention]

An object of the present invention is to provide an intelligent mechanical system composed of a plurality of control elements with the support of intelligent processing based on knowledge base,
An object of the present invention is to provide a highly efficient intelligent control parallel processing system for controlling in real time by performing high-speed interlocking control calculation.

[Outline of Invention]

The present invention relates to an intelligent machine composed of a plurality of control elements, for example,
An intelligent parallel processing system for highly efficient control for performing intelligent control in real time by performing high-speed motion control arithmetic on a human-type intelligent robot, etc. with the support of intelligent processing based on a knowledge base. As a means for that, a multi-micro processor that is a component of a parallel processing system and is a core of the system. The configuration inside the module (configuration processor element), and the method of distributing the functions corresponding to each control element and connecting them densely, and the overall system configuration constructed by it and controlling each control element In order to improve the real-time processing performance, highly efficient parallel processing is performed within the multi-micro processor module that is in charge of motion control calculation for And MIMD type full parallel processing system is divided into a shared knowledge and distributed knowledge depth knowledge related to the control element as a shared knowledge base shared knowledge shared main storage, the multi-micro-processor-responsible for control of the element
A function-distributed knowledge structure of a method that is distributed in modules and held as a distributed knowledge base, and based on these knowledge bases, intelligent processing of a method that performs intelligent processing in the background of motion control arithmetic processing and supports control, A knowledge processing method is proposed to provide an intelligent parallel processing system for control, which is suitable for a large-scale intelligent controlled object and has high versatility and real-time processability.

Example of Invention

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a multi-processor system which constitutes the parallel processing system of the present invention.
1 shows a hardware configuration of a Micro Processor Module (MMPM). The multi-micro processor module (MMPM) is composed of 13 base processors (BP) 1 to 13. Each of the base processors (BP) 1 to 13 further manages two numerical operation processors APU and numerical data processing processors NDP which can operate in parallel and manages them in an integrated manner, and also performs data processing such as knowledge processing and judgment processing and various parallel processing. It consists of a main processor CPU which supports functions and communication functions and plays a central role of the base processor BP. These processors constituting the base processor will be described later. The 13 base processors (BP) 1-13 are
It is connected by three independent high-speed shared memory buses 53, 54, 55 which are internal communication buses, and shared memories (SCM, DCM) 47, 48, 4 are provided on the respective shared memory buses.
9 is connected. The access control to each shared memory 47, 48, 49 is a highly efficient bus arbiter (DC) 44,
45 and 46, each base processor BP
Can access these shared memories at high speed and almost equally without any inconsistency, as in normal memory access. The total communication throughput of these shared memories 47 to 49 in this embodiment is 24M under random access.
reaches bytes / s. In addition, the base processor (BP)
The bus 56 controlled by the bus arbiter 50 is supported as a general-purpose shared bus accessible between 1 to 13, and mainly includes the base processor (BP) 1-1.
Three common shared I / Os 51 are connected. In addition to these shared resources, each base processor (BP) 1-13
Has local memories and local I / Os 17 to 29 accessible only by themselves on the local buses 57 to 69, and normal programs are placed on the local memories. Furthermore, as a major feature of this embodiment, 13
13 so that the base processors (BP) 1 to 13 of the base can perform tightly coupled type complete parallel processing efficiently and mechanically.
A group of base processors BP that execute deeply related processing in accordance with the relay of parallel processing tasks that are divided into groups. Combining comrades to form a group and synchronizing them to create a data path like a critical path. In-group processor synchronization mechanism that can execute pre-scheduled parallel processing with the best parallel processing time close to the processing time,
A high-speed random task can be performed by enabling interrupt service between any main processor (BP) with high efficiency to start any service task at high speed at any time, and to manage and monitor the start status. An instruction transmission mechanism between processors that enables loosely coupled parallel processing in intelligent processing and sudden random normal processing is provided as a communication unit controller (CC) 30-4.
The dedicated and common bus 52 is provided in the second bus so that a sufficient throughput can be obtained as a hardware mechanism for parallel processing.
Therefore, it is exclusively connected independently of other common buses. In the instruction transfer sequence in the inter-processor instruction transfer mechanism, it is desired to activate the service task of the interrupt register table which enables the interrupt from the arbitrary main processor provided on the status shared memory (SCM) 47 to the arbitrary main processor. It suffices to perform the operation of writing the start address of the service task to a predetermined address corresponding to the processor. When the operation is executed, the common interrupt control circuit (CINTC) 43 that monitors the status shared memory 47 is connected to the main processor that gives an instruction from the written address and the main processor that is requested to process the service task. Analyze the processor, interrupt the target processor, transfer the interrupt vector to the main processor when it is accepted, refer to the necessary interrupt vector register, and jump directly to the start address of the service task. Let The shared interrupt control circuit 43 knows that the service task has been activated by seeing the processor that has received the request for service task processing from the interrupt register on the shared memory 47, and sets the service task activation flag. The main processor which has instructed the instruction knows that the instruction is transmitted by checking the flag and the next instruction can be instructed. The synchronization mechanism between processors within a group corresponds to the set bit simply by setting a predetermined bit in the group register (16 bits) in each of the communication unit controllers (CC) 30 to 42 and loading the value. A group has been configured between the processors, and the task processing up to that point has been jointly executed by that group, and the task processing of that processor has been completed, and the task processing of other processors belonging to the group is waiting for completion. To show that. The inter-processor synchronization mechanism checks the contents of the group register specified for each processor with the processor that has finished the task processing, so that the synchronization is achieved when the task processing of all the processors in the group is completed. If the synchronous interrupt is permitted, an interrupt is generated to the main processor to notify the end of synchronous processing. If the synchronous interrupt is used, the play time of the main processor until the synchronization is achieved can be effectively used by assigning it to the background operation. With the above parallel processing hardware mechanism, highly versatile parallel processing can be supported with a minimal software overhead.

The above is the multi-micro processor module (M
It is a major mechanism within MPM)
In the present invention for operating like one processor, the base processor (BP) 11, 12, 13 is provided with a function as a processor for external communication, and by using it, a plurality of multi-micro processors are used.・ The module (MMPM) can be combined. Base processor (BP) 11, 12, with external communication function
13 has two external communication mechanisms. One is multiple other multi-micro processor modules (MMPs).
System bus (SYSBUS) that is a shared bus that can be shared with M)
A system bus buffer (SBB) 70, 71, 72 that provides address output, data input / output, and system bus control input / output signals connectable to 73, 74, 75, and a base processor (BP) for external communication. 11, 12, 13
Three system buses 73, 7 provided corresponding to each
Shared resources such as shared main memory on 4,75
It can be accessed from Micro Processor Modules (MMPM). The other external communication mechanism is a multi-micro processor module (MMPM) that performs a one-to-one dedicated connection with another multi-micro processor module (MMPM) and a dual-port RAM to perform related control. (MMP
External communication joint mechanism (EC) 1 for tightly coupling M)
4, 15 and 16 are also provided corresponding to the external communication base processors (BP) 11, 12 and 13, respectively. Details of this communication mechanism will be described later.

FIG. 2 illustrates the inside of the base processor (BP). As described above, the base processor (BP) manages two numerical arithmetic processors (APU) 78 and 79, one numerical data processor (NDP) 77 and those in an integrated manner, and controls the entire system. And a main processor (CPU) 76 which participates in and performs various parallel processing, communication processing, and intelligent processing.
In the present embodiment, the numerical operation processors 78 and 79 mainly perform control operations, and are interfaced with the main processor 76 by the reference numeral 80.
It operates in parallel with the numerical data processor 77. The main processor 76 operates the numerical operation processors 78 and 79 to execute the algorithm of the control operation by its own opcode, and controls the flow of the control operation together with other base processors BP to perform the complete parallel processing. The idle time of the main processor 76, such as the free time until synchronization is achieved and the free time after requesting arithmetic processing from the numerical processing processors 78 and 79, is, so to speak, a synchronous interrupt or the numerical processing processor 7.
With the support of processing end interrupts 8 and 79, it can be effectively used for background operation. In this embodiment, intelligent processing is considered as the background operation, and the main processor 76 uses the external information from the knowledge base and the sensor together with the numerical data processor 77 to perform the intelligent processing in the background. The result is reflected in the control calculation executed in the main.

FIG. 3 shows a state of parallel processing operation of the numerical operation processor APU and the main processor CPU. Arrow 85
The upper part shows the control ground processing, and the lower part from the arrow 84 shows the main control calculation processing. The main processor CPU executing the back ground job 81 such as intelligent processing is operated by the numerical processing processor APU.
3 is completed, and when the processing end interrupt 86 of the numerical processor APU is applied to the main processor CPU, the current register state is saved in the stack as much as necessary, and then the main job 82 is forcibly pulled back by the reference numeral 87. After preparing for the synchronous processing and the next operation, the numerical operation processor APU is requested to perform the operation processing again at 88, the register is returned to the original state at 89, and the back ground job 81 is called again. Run. By this method, the processing indicated by reference numeral 82 is completed in a sufficiently short time, so that the main processor CPU can allocate most of the processing capacity to the background operation such as the intelligent processing. The effective use of the idle time of the main processor CPU until the synchronization is achieved when using the synchronous interrupt is realized in the same manner as in the case of the processing end interrupt of the multiple arithmetic processor APU.

By the above method, the back ground operation can be described in the same manner as a normal program without paying attention to control calculation.

FIG. 4 is a schematic diagram showing the relationship between a control operation which is processed in parallel in the multi-micro processor module (MMPM) 90 and the intelligent processing which is executed in the background and supports the control operation, and the state of the processing. It is a representation. Multi Micro Processor Module (MM
The control operation represented by the reference numeral 94, which is processed by the respective base processors (BP) 1 to 13 in the PM) 90, is shown in the reference numeral 97, while closely communicating with the respective base processors (BP) 1 to 13. Processed in parallel. The tasks shared by the respective base processors (BP) 1 to 13 are distributed so that control operations can be decomposed into primitive operation levels such as addition, subtraction, multiplication and division and processed in parallel as much as possible. Is preliminarily scheduled and assigned to each base processor (BP) 1 to 13 so that the best parallel processing close to the processing time can be performed. The intelligent processing has a knowledge base in units of 1 to 13 of each base processor (BP), and the intelligent processing is divided for each function and represented by reference numeral 93. It is executed by distributed parallel processing while slowly transmitting information between the processors. In addition, each multi-micro processor (MMP
M) holds knowledge deeply related to the controlled object in charge in the knowledge base of each base processor (BP) 1 to 13,
It is devised so that most of the intelligent processing can be performed without using the knowledge of other multi-micro processors (MMPM). Specific examples of these intelligent processes will be described later. In this figure, reference numeral 95 represents the entire control operation which is completely parallel processed. The intelligent processing is represented by reference numeral 98, and the entire control device 95
Influences various parameters of, and controls the flow of control calculation and various controlled variables. Further, in the intelligent processing, not only the knowledge base but also the processing of information from the sensor that is closely related to the controlled object represented by the reference numeral 99 is performed.
Use as one of the knowledge. As for the knowledge common to the system, it is possible to take out the knowledge through the system buses 73 to 75 and to newly store or change the knowledge as indicated by reference numeral 100.

FIG. 5 shows a state where the entire control calculation is executed by completely parallel processing. A downward arrow typified by reference numeral 103 indicates a portion where the base processor (BP) is executing a control operation, and the operation processing is in principle performed with the passage of time (exceptions include branch processing). ) Is performed from top to bottom in the figure. In such tightly-coupled complete parallel processing, since the relay between tasks is complicated, it is necessary to exchange information closely between tasks, and between tasks, which tasks can be executed after which tasks are completed. It is necessary to synchronize so that the preceding relationship does not conflict. Conventionally, in such complete parallel processing, data dependent parallel processing control represented by a data flow has been generally used. The data flow type control is effective because it can be realized by hardware, etc., although it is limited to a dedicated system when the relay between tasks is simple and there is no general-purpose processing such as branch processing. However, if the number of tasks becomes huge and the relay between tasks becomes complicated and versatility that can be applied to various jobs is required, it is necessary to control the synchronous processing itself dynamically by the program, and Branch processing must be able to be executed freely, and since many synchronization flags and a large software overhead for synchronization processing are involved, tasks cannot be subdivided and programs become complicated. There was a problem that it was not possible to improve the processing efficiency. Therefore, in this embodiment, a processor is regarded as a process, a processor control method for controlling the process is performed by an inter-processor synchronization mechanism in the group, and a parallel processing method is proposed and adopted. In this method, base processors (BPs) that process related tasks are grouped and the processors belonging to the group perform processing in synchronization with each other.
It does not exceed 3 processes. Therefore, since the synchronous processing is always completed by the data processing of 1 word (16 bits), the software overhead can be minimized. In FIG. 5, the synchronization processing is performed by the horizontal line represented by reference numeral 105. In the reference numeral 105, the base processors (BP0) 1 and (BP1) 2 form a group, and task processing is completed together and necessary data are available between the base processors (BP0) 1 and (BP1) 2. Since it is possible to exchange information, the base processor (BP0) 1
And the base processor (BP1) 2 are synchronized with each other to confirm the facts. Since the group can be freely changed to the best one by relaying the tasks, if the synchronization mechanism between processors in the group is fully utilized, the best complete parallel processing close to the processing time of the critical path can be easily supported. it can. Further, due to the control of the process, the conditional branch processing as shown by reference numeral 106 between the synchronous processing units can be supported relatively easily. The symbol 104 represents the idle time until synchronization is established between the processors, that is, the idle time of the processor. During this time, when the synchronous processing is completed, an interrupt is sent to the main processor (CPU) to notify the main processor (CPU) of the synchronous processing by the synchronous end interrupt function of the processor synchronization mechanism within the group, and the background processing such as intelligent processing can be performed. The surplus processing capacity of the main processor (CPU) can be assigned. Further, in the control calculation, since there are many numerical calculation processes, most of the processes are executed by the numerical calculation processor APU. Therefore, even when the base processor (BP) is executing the control operation, the free time of the main processor CPU after the main processor CPU requests the numerical operation processor APU to perform the numerical operation is the same as the synchronous interrupt function. Numerical arithmetic processor APU
Since it can be effectively used for the back ground job by the processing end interrupt function, the processing capacity of most of the main processor CPU can be assigned to the intelligent processing in this embodiment.

FIG. 6 shows a system bus 7 which is a common bus for the entire system.
A plurality of multi-micro processor modules (MMPM) represented by reference numeral 90, 3, 74 and 75 (128 modules at maximum in this embodiment).
Shared main memory 100, 10 with shared database
1 and 102 are shared. In addition to shared data, shared programs also reside in the shared main memory, and each multi-micro processor module (MMPM)
Processes the shared data or shared program in its own shared memory or local memory. By providing three system buses 73, 74, and 75 independently, contention for system bus access due to a large number of modules is mitigated. Each system bus 73,
As described above, the access to the 74, 75 is based on the external communication base processor (BP) 11, 12, 13 of each multi-micro processor module (MMPM).
System bus buffers (SBB) 70, 71, 72 of. In this way, by having a system bus accessible from all the multi-micro processor modules (MMPM) that make up the entire system and a shared main memory provided thereon, even if it is not so fast as a whole, There are many deficiencies in the dedicated combination, and there is a general lack of versatility.
You can add great versatility to your processor system.

However, the system buses 73, 74, 75 and the shared main memory 1
Reliance on only 00, 101, and 102 will result in insufficient efficiency due to access competition. Therefore, in the present embodiment, as described above, the external communication base processor (BP) 11, 12, 13 of each multi-micro processor module (MMPM) is connected to the external communication joint mechanism (EC) 14, 15. , 16 are provided respectively, and a multi
Most of the knowledge is obtained by connecting the Micro Processor Modules (MMPM) exclusively with their communication joints.
PM) to reduce the dependency on the shared main memory and minimize the access contention to the system bus.

FIG. 7 shows a joint mechanism (EC) 14, 15, 1 for external communication.
6 shows an example in which a control system for a human-type intelligent robot is configured by using a multi-micro processor module (MMPM) by utilizing the method described in FIG. Multi Micro Processor Module (MMPM) 103, 104, 1
05 is connected in a ring to form a brain part that controls and manages the entire system. From there, each multi-micro processor module that is in charge of total control and management of the visual part, arm part, and foot part ( MMPM) 106, 11
It is connected to 0 and 109. Further, the multi-micro processor module (MMPM) 106, which performs total control of the head, communicates with each multi-micro processor module (MMPM) 107, 108 in charge of left and right visual control. There is. Similarly, the multi-micro processor module (MMPM) 110 that performs total control of the arms is a multi-micro processor module (MMPM) 113 and 114, and the multi-micro processor module that performs total control of the foot. The (MMPM) 109 communicates with the multi-micro processor modules (MMPM) 111 and 112, respectively, and forms a function distribution and a hierarchical structure as a whole. Constituting this functionally distributed and hierarchical system 12
Multi Micro Processor Module (MM
PM) is also connected by the three system buses 73, 74, 75, but the related control elements are exclusively connected by the external communication joint mechanism (EC), so that the head, the visual part, and the arm part are connected. , A large number of multi-micro processor modules (MMPM), since most relevant and necessary knowledge for each control part of the foot is available from the knowledge base in the nearby multi-micro processor module (MMPM). ), The problem of processing capacity loss due to system bus access contention is considered to virtually disappear.

FIG. 8 shows a multi-micro processor module (MMPM) 103, 10 by means of an external communication joint mechanism (EC) from the brain to the visual control system in FIG.
The state of communication between 4, 107 and 108 is enlarged and shown. Communication between the multi-micro processor module (MMPM) by the external communication joint mechanism (EC) represented by reference numeral 115 in the figure intervenes the dual port RAM as described above, and interrupts if necessary by the communication partners. Is carried out by handshake and the data on the dual port RAM is exchanged appropriately, and the mechanical characteristics are similar to the inter-processor command transmission mechanism described above.

FIG. 9 shows a multi-micro processor module (MMPM) 104 and a multi-micro processor module.
The communication 115 by the external communication joint mechanism (EC) with the module (MMPM) 108 is further expanded and shown in detail. 116 and 117 are multi-micro processor modules (MMPM) 1 respectively.
04 and multi-micro processor module (MMPM) 108 for external communication base processor (B
P) 126, 127 showing the joint mechanism (EC) for external communication. External communication joint mechanism (E
C) 116 and 117 support address output for accessing the dual port RAM 118, data input / output, signal input / output for controlling the dual port RAM 118, and interrupt receiving function. Dual Port RA
When the interrupt vector denoted by reference numerals 121 and 123 is written from the base processor (BP) 127, 126 to a predetermined address on the dual port RAM 118, the M118 outputs from the base processor (BP) 127 to the base processor 126. Interrupt instruction 121 to the base processor (BP) 126, and an interrupt instruction 123 from the base processor (BP) 126 to the base processor 127, the base processor (BP) 126. An interrupt generation function is provided on the dual port RAM 118 so as to generate an interrupt 124 to the 127. The interrupted base processor (BP) refers to the interrupt vector written in the dual port RAM 118, and shifts to the process of the interrupt service routine designated by the interrupt vector. Dual port RAM 118 denoted by reference numerals 119 and 120
The above-mentioned general data input / output processing can be freely performed in the area other than the address area supporting the interrupt vector as in the normal memory access.

FIG. 10 shows a system bus 73, 74, 75 for supporting communication between the above-mentioned multi-micro processor module (MMPM) and a joint mechanism (E) for external communication.
C) Using 14, 15 and 16, reference numerals 130 and 132 between the database and the intelligent processing software that the base processors (BP) in each multi-micro processor module (MMPM) have in a distributed manner. A typical multi-micro processor module (MM
PM) Exchange of information between inside and outside, exchange of information represented by reference numeral 131 using three shared main memories 100, 101, 102 having shared knowledge bases provided on three system buses and from the outside world. A state in which sensor information represented by reference numeral 132 is acquired as knowledge information is schematically shown. Multi-micro processor module (MMPM) 103, 104, 1 shown in the figure
As described above, the reference numerals 07 and 108 indicate 13 base processors (BP) in this embodiment, as shown in FIG.
1 to 13, of which three base processors (BP) 11 to 13 have a mechanism EC for external communication and a system bus buffer SBB. In this figure, a mechanism for external communication represented by reference numeral 129. A general base processor (BP) represented by the reference numeral 128 other than the base processor (BP) having the above is omitted for simplicity. In this system, a huge intelligent parallel processing system having such a function-distributed and hierarchical structure is used as a multi-micro processor module (MM) as shown in FIG.
It can be easily realized by a dense and highly versatile communication network between PMs. According to the communication network method which constitutes the present invention, even if various parallel processing or distributed processing having various communication amounts such as tightly coupled parallel processing, loosely coupled parallel processing or distributed parallel processing are mixed, -By connecting with an appropriate communication mechanism in the Micro Processor Module (MMPM) and performing processing using an appropriate processing mechanism, it is possible to provide normal throughput corresponding to the data communication amount, so that parallel processing can be performed. It is possible to solve the problem of the parallel processing efficiency deterioration due to the communication overhead, which is the biggest difficulty. In FIG. 6 described above, the states of the intelligence processing and the knowledge processing based on the main knowledge base and the sensor information are well represented. In this embodiment, such knowledge processing is naturally executed in the background of the control calculation for performing motion control of the controlled object, etc., and affects various control amounts and control flows based on the processing result. It is characterized in that it is given to control the control arithmetic processing itself.

According to the embodiment of the present invention, the control operation is completed mainly by the numerical operation processor APU under the support of the parallel processing hardware such as the high-speed shared memory communication mechanism, the inter-processor instruction transfer mechanism, and the inter-processor synchronization mechanism. The parallel processing enables high-speed processing, enables complex motion control, etc. to be executed in real time, and the processing capacity of most of the main processor CPU that operates in parallel with the numerical processing processor APU is controlled by the back ground of the control processing. It is possible to allocate to intelligent processing based on the knowledge base executed by the computer and the external information from the sensor, and the result of the intelligent processing is reflected in various parameters of the control operation. Provides a multi-micro processor module MMPM, which is a dynamic parallel processing module. · A system bus punishment Hua and external communication joint mechanism is an external communication hardware provided in the micro-processor-modules MMPM, a plurality of multi-micro-processor-module M by the former
A multi-micro processor module MM that supports shared resources such as a system bus that can be shared by MPM and sharing on that system bus
Supports dedicated one-to-one tight coupling with PM, function distribution,
Providing a hierarchical connection structure, by which multiple multi-micro processor modules MMPM can be efficiently and universally combined to construct a network, and as a result, an intelligent parallel processing system for huge control can be constructed. be able to.

〔The invention's effect〕

According to the present invention, complex and sophisticated motion control calculations can be executed in real time at high speed, and the intelligent processing and knowledge processing that support these control calculations can also be processed at high speed.

[Brief description of drawings]

The drawings show one embodiment of the system of the present invention.
The figure shows the hardware configuration of the multi-micro processor module. Fig. 2 shows the configuration of the base processor.
Fig. 3 is a diagram showing the parallel operation of the numerical processing processor and the main processor, Fig. 4 is a schematic diagram of parallel processing in the multi-micro processor module, and Fig. 5 uses the synchronization mechanism between the processors in the group. FIG. 6 is a diagram showing the flow of complete parallel processing, FIG. 6 is a diagram showing how shared main memory is shared by the system bus, and FIG. 7 is a system in which a multi-micro processor module is applied to a human-type intelligent robot. FIG. 8 is a diagram showing a configuration example, FIG. 8 is an enlarged view of a connection using an external communication joint mechanism, FIG. 9 is a view showing details of the external communication joint mechanism, and FIG. 10 is a knowledge-based processor network. It is a work figure. 1 to 13 ... Base processor (BP), 47 to 49 ...
... Shared memory, 30-42 ... Communication controller (CC), 70-72 ... System bus buffer, 73-75 ... System bus, 14-16 ... External communication joint mechanism, 76 ... Main Processor (CP
U), 77 ... Numerical data processor (NDP), 78
~ 79 ... Numerical operation processor (APU), 93 ... Background ground job (intelligent processing), 94 ... Control operation, 95 ... Overall control operation, 100-102 ... Shared main memory, 118 ... Dual port RAM, 99 and 13
2 ... Sensor information.

Claims (9)

[Claims] 1. A parallel processing system for an intelligent controlled object which needs to be controlled with the support of knowledge or intelligence, wherein a plurality of base processors (1 to 13) are connected to a high speed shared memory communication mechanism (44). ~ 46, 47-49, 53-55)
And an inter-processor instruction transfer mechanism (30) for exchanging instructions and information between arbitrary processors to form a module, and the plurality of multi-microprocessor modules (MMPM) are the intelligent control targets. Of a plurality of multi-micro processor modules (MMPM), and an inter-module communication mechanism (14-16,
70-72), and a parallel processing system. 2. The parallel processing system according to claim 1, wherein the multi-microprocessor module (MM).
The base processors (1 to 13) forming the PM include a main processor (76) and the main processor (7).
Under the control of 6), the main processor (76) and a plurality of arithmetic processing processors (78, 79) capable of operating in parallel are provided, and the main processor (76) performs arithmetic processing on the arithmetic processing processors (78, 79). Of the main processor (76) until the request is sent to the main processor (76) or until the control calculation is synchronized between the main processors (76) in the background. A parallel processing system characterized by being assigned to a process for supporting a control operation as a parallel process. 3. The parallel processing system according to claim 2, wherein the main processor (76) executes a main operation that is a processing operation for supporting intelligent processing during processing. (78, 79) A function of calling and executing an intelligent process as a background process in the play time generated by requesting the arithmetic processor (7).
8, 79) when the execution of the operation is completed, or when another base processor completes the necessary processing, an interrupt is generated to the main processor (76) to make the main processor (76) the main processor. A parallel processing system having a synchronous processing function for returning to arithmetic processing. 4. A parallel processing system according to claim 1, wherein one or more of the base processors (11 to 13) constituting the multi-micro processor module is provided with each multi-micro processor. A parallel processing system comprising means (70 to 72) for performing communication between processor modules and connecting the communication means (70 to 72) to buses (73 to 75). 5. The parallel processing system according to claim 1, wherein one or more of the base processors (11 to 13) constituting the multi-micro processor module are provided with the multi-micro processor. A parallel processing system comprising one or more external communication mechanisms (14 to 16) which can be directly connected to another multi-microprocessor module under the control of the processor module. 6. The parallel processing system according to claim 3, wherein the main processor (76) constituting each of the multi-microprocessor modules has knowledge deeply related to each control element to be controlled. A parallel processing system comprising distributed knowledge bases that function under the control of a main processor. 7. The parallel processing system according to claim 1 or 4, wherein a shared main memory is provided on a common bus (73 to 75) commonly connecting the multi-microprocessor modules. (100 to 102), and a shared knowledge base for holding common knowledge among the multi-microprocessor modules is provided in the shared main memory (1
00-102) provided on the parallel processing system. 8. The parallel processing system according to claim 1 or 5, wherein one of the multi-microprocessor modules and the other one are hard-wired between the multi-microprocessor modules. A parallel processing system, characterized in that they are connected by means (118) having a function of causing wear interrupts. 9. The parallel processing system according to claim 1, wherein the plurality of multi-microprocessor modules are tightly coupled to each other in a one-to-one relationship, and the functions are distributed to support the coupling. Alternatively, a parallel processing system characterized by being connected in a hierarchical manner.