JPS58154058A - Executing system of os - Google Patents

Abstract

PURPOSE:To attain a parallel operation, by cutting off a part that is capable of a parallel operation as an independent program in an operating system and then allotting a working processor to every program. CONSTITUTION:An operating system OS is roughly provided with an SVC process routine group 420, an interruption process routine group 410, an OS process dispatcher 431, a task dispatcher 441, an idle routine 450 and an OS process group 436. The group 420 serves as an OS service counter to a task group 442. The group 410 processes an interruption.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic computer, and more particularly, to an execution method of an operating system (hereinafter abbreviated as O8).

In conventional computer systems, multi-computer systems composed of multiple computers have improved reliability9.
VC was used to achieve vI-requirements such as function distribution and load distribution. These requirements were mainly set for the future tasks of the system b), and were realized within the computer in the form of distributed arrangement of application programs.

Therefore, 08, which is the core of the computer Not-Air, has neither the above requirements nor any examples.

However, in recent years, device technology has made remarkable progress, and it has become possible to realize a compact, inexpensive and high-speed 7-system system, and it has become possible to configure one computer with a plurality of processing units (processors). Therefore, the above-mentioned demands have become stronger for 2008 as well. However, when trying to meet all of these requirements using the conventional method, there was a problem of performance deterioration.

Hereinafter, the conventional technology will be explained using figures.

FIG. 1 shows a configuration diagram of a conventional multi-computer system.

Computers A and B that make up the system are each connected to a main storage device (hereinafter abbreviated as MS), and the two computers are connected to the global memory (MS) via a memory data bus.
Hereinafter, it will be abbreviated as GM. ), you can now end and write. Also, each computer can interrupt the other computer via an interrupt bus. Each computer has a number (referred to as a computer number) and is identified by the number. ``With this system configuration as the premise, an example of communication between computers in a multi-computer system will be explained using FIG. 2.

For computer people, application program 2 is task α.
is registered as. Similarly, computer BK has task β
is registered. On the other hand, 08 is thicker and SVC processed O8
And interrupt processing j! It consists of 08. 8vC processing 08
ri is activated by the svC command issued by the task, and performs the processing specified by the task. Interrupt processing O8 is started by an interrupt that occurs inside or outside the computer,
Perform processing corresponding to the interrupt factor.

A communication block of the computing engine is placed in the shared memory GM of the computing engine. This communication block contains the sending t-requested computer number, the processing code indicating the type of processing, and the process to be processed by the other computer! Set the parameters necessary to perform.

For example, when starting task l of computer B from task α of computer A, an SvC command is first issued to start task /l'' from task α.

As a result, svc processing O8 is activated. 8VC processing 08 executes - Computer B according to the parameters specified by the task.
Knowing that this is a task activation request, the GM writes the necessary information to the GM's communication block. in this case,
As the processing request computer number, a code indicating task activation is set as the previous t1 processing code of computer A, and the task number of task β is further set as a parameter. After setting this information, computer B is sent via the interrupt bus.
Interrupt the contact. Finally, the process ends with task α waiting for a response.

In computer B that received the communication interrupt, interrupt processing 08 is activated and refers to the GM communication block. In this case, the communication block includes ′ task β
``Startup request'' is written, so start task β.

Thereafter, response information is written to the GM communication block in order to return a response to computer A. That is, the number of the calculation WAB is set as the transmission request computer, the code indicating the response report is set as the processing code, and the return code indicating the result of the processing is set as the parameter. Finally, a communication interrupt is sent to computer A and the interrupt processing is completed.
Transfer control to task β.

On the other hand, in the calculation 1kA that received the communication interrupt, interrupt processing 08
is activated, the task α is released from waiting for a response, and returns to task α.

In conventional systems, each computer has the same OSF:
Distributed deployment of the p1 application program was realized by arranging the maze and matching nine mazes between the O8 of each 'Ji machine. However, there was no idea of distributing each O8t function, and the performance improvement due to parallel processing in 08 was small.

An object of the present invention is to provide O8
The objective is to improve the performance of 08 by providing a mechanism for operating them in parallel.

0.0 due to advances in element technology. For configuring one computer system with multiple processors 1. :And price chart.

It has become possible in terms of performance. Therefore, performance improvement through parallel operation of programs is required.

However, in the past, application programs were only processed in parallel, and 08 was basically based on sequential processing. The present invention separates a part of O8 that can operate in parallel as an independent program called the t-08 process, and allocates an operating processor to each OS process, thereby allowing O8 to operate in parallel if possible. It is something to tighten.

Hereinafter, practical example #A of the present invention will be explained with reference to the drawings.

FIG. 3 shows a calculation 11t composed of multiple processors.
- It is a system configuration diagram of a multi-computer system in which two computers are combined.

The first computer system includes an M8101 and a memory control unit (hereinafter referred to as MCU) 301 for controlling the M8.4 processors (hereinafter referred to as P) 3
21,322. ．． 323°324, and the above MCU,
It consists of a system bus 311 to which P is connected. Each processor has a processor number 1.11 and is identified by line number.

In addition, a link processor (hereinafter abbreviated as LINK), which is a processor for connecting two computer systems At, is also used.
) 3; 10, and memory G shared by the two-hand counting system
Configure the Simalte computer system using MIIG. As in the prior art, each computer is classified by computer number.

08, application programs and data are stored in the M8101 mentioned in 1, and each processor P32.
1 to a24&c are executed.

P321 to P324 can be operated independently, and when the data in the memory is tIjlPIIL, the address where the cough data is stored is sent to the MCυ301.

MC0301 reads the data on M8101 at the specified address and sends it to the processor. For example, P321
When a certain program is executed and φ is executed, P321 sends the address where the cough program command is stored to MCU301.
Send to. The MCU 301 issues the instruction t-in from the designated address 9 and sends it to P321. The P321 that the command receiver took interprets and executes the command, and when the command processing of 1":) is completed, it sends the MCU again to issue the next command sr.
The command address is sent to 301. In this way, J armji M
Collects the instructions on 8101, interprets and executes the program t
-It makes it work. In order to perform this series of processing independently in each processor, the M8101t may be accessed simultaneously from two or more processors. Therefore, the system bus 311 has a sequence control function f:!
D. Prevent requests from two or more processors from being sent to the MC0301 at the same time.

Also, communication between two processors is carried out between MC0301 and M
8101t-. For example, P32
1 and P322, set the area for communication on M8101, and P321 sets the communication information t in the cough area.
After setting, a communication interrupt t-P322 is applied via the system bus 311.

At P322, which receives the interrupt, communication information is extracted from the communication area and processing is performed according to the information. Setting and retrieval of the communication information of the user is realized by sending the address or data of the communication area to the MCU 301. Furthermore, the system bus 311 has an interrupt function for the above-mentioned communication interrupt.

Furthermore, communication between two computer systems is performed using LINK.
330, GM 110t-.

LINK330 d, GMIIO Be aa/W
7N is used for interrupt function 1 to r ite and other computer systems. Now, consider communication between P321 and P325. A communication area (communication block in conventional technology FIG. 2) is provided on GMIIO, and P321 sends communication information to this area. This is done by sending the address of the scissor area and setting information to 'tLINK 330. After setting communication information, P321 is LIN
Interrupt P325 via K330. P325r
In order to read the communication area on 0M110, the address of the communication area is sent to LINK33G. L
INK330 reads data on GMIIO from the specified address and sends it to P325. P325 interprets the data, that is, the communication information, and performs processing according to the information.
t-do.

FIG. 4 is an overall configuration diagram of the program of the present invention.

08 is a thick svc processing routine group 4201 interrupt processing routine group 410.08 process dispatcher (hereinafter referred to as 0
81) Abbreviated as ISF. ) 431, task dispatcher (hereinafter abbreviated as TKDISF) 441, idle routine (hereinafter abbreviated as IDLE) 450, and 0
It is composed of eight process groups 436. The 5vcl & filler group 420 is a window for the 08 services for the task group 442, and provides, for example, an svc processing routine for starting other tasks, an svc processing routine for accessing the disk, etc. ing. Further, the interrupt processing routine group 410 is a routine 69 for processing interrupts from inside or outside the computer, and is prepared corresponding to the interrupt cause. For example, there are routines for processing end interrupts from the disk, routines for processing timer interrupts, and the like.

The flow of processing in step 08 is shown using FIG.

Suppose now that one task in task group 4-'2 operates and issues a certain 8VC instruction. In order to process the 8vc instruction, control is transferred to the corresponding svcJAIm routine of the 8vc processing routine #42°. 5vcI6a
In the t routine, the 08 process startup routine 432tC
Click ALL to start the 08 process. When the processing of the 8vC processing routine is completed, the control rjO8DI8P431
Move to. 08DIRP 431-t" selects the executable 08 process t-1 from the 08 process group 436 and transfers control to the corresponding OS process. In this case, the OS process started by the SvC processing routine will be selected. In the 08 Pro 7th, the resource occupancy routine 434, !j source release # -f74 will be selected as necessary.
CALL 35 to execute a certain predetermined process.

08 When the process ends, the OS process end routine 4
33 t CALL. The routine/433 terminates the corresponding osya process and links to the 08DI8P431 in order to select the OS process to be executed next.

08DI8P selects an executable 08 process in the same way as described above, but if there is no executable OS process, it links to TKDI8P441. TKDI8P44
1, the executable tasks of the task group 442 are set to 1.
Select one and transfer control to that task. In this case, the above-mentioned 8VC instruction issuing task is selected and returns to that task, but if there is no executable task, IDLE
Link to 450. IDLE450 is a program that loops in all interrupt-enabled states.

If an interrupt occurs during IDIJ:450 operation,
Control is transferred to an interrupt processing routine among the interrupt processing routine group 410 that corresponds to the interrupt cause.

In the interrupt processing routine, 08 process startup routine 43
2t-CALL to start the 087o process.

When the processing of the interrupt processing routine is completed, 08DI8P4
Control is transferred to 31. After that, the KO8 process and tasks are selected in the same manner as in the SvC processing described above, and finally linked to the IDLE 45G.

The flow of O8 processing using the OS process has been explained above, but now let's learn more about the mechanism for controlling the KO8 process! Explain lal.

FIG. 5 shows a configuration diagram of the OS process management table.

In order to fill in the 08 process tf, one management table OS process control block (hereinafter abbreviated as 08PCB) 500 is prepared for one OS process.

08PCB500 has a lock area 510. pointer 1
Area 520. Pointer 2 area 530. Execution processor number 540. Status information showing the status of the OS process @550. Program start address of OS process 560. Other control information area 570 and OS
jD and MS from the process work area 580.

The lock area is used for exclusive control of the 08PCB500. In other words, a processor processes 08PCBSOO, processes the data in 08PCB, and processes the data in 08PCB.
tel, while another processor is working on the PCB
Data t-read/write L: (This is a flag for each processor to read/write data on the 08PCB
Prior to data manipulation, all processor numbers must be set in this area 510. Therefore, when this area 510 is 0, it means that the corresponding 08 PCB is not being processed by any processor, and when a value other than 0, that is, the previous processor number is set, the corresponding number is marked *. It means that the processor is processing the 08 PCB.

The pointer area 520 indicates that when executing an OS process, if more OS processes than the number of processors configuring the system are started, all OS processes are executed at the same time.
Unable to run S process, it is necessary to create a queue. This queue is called an execution queue. When creating the queue, the next 08 PCB address t is set in this pointer area 520 to store the j-order of execution.

When the pointer 2 area 530 occupies an area 7-,
If 8 processes are occupying the resource, create a queue for occupying the other resource. This parallel queue is called a resource queue, and as in the case of the execution queue, the resource queue is formed by storing the address of the next 08 PCB in the pointer 2 area 530.

Set the execution processor number 540U and the gross number f of the processor that is executing the corresponding 08 process.

Status information 55 (Hat, status of the applicable OS process)
1t - This is an area for storing the BυN bit 551, which indicates which OS process is being executed on a certain processor. The state of the OS process, such as the ENQ bit 552 indicating that it is waiting for resource occupancy, is stored in bit correspondence. For example, when 551 and 552 are 1, it indicates that the program is being executed or waiting for resource occupancy, and when it is 0, it indicates that they are not.

The program start address 560 indicates the destination jjiM19 address of the program A of the OS process.
Used when linking from DISP431 to the OS process.

Regarding other control information 570, processing of the OS process may be interrupted due to an interrupt during execution of the 08 process. At this time, it is used to save the registers used by the 08 process so that the 08 process can resume processing from the interrupted point after the interrupt processing fee has expired.

The OS process work area 580 is a work area for temporarily storing information during OS process processing.

Next, the OS process queue management method will be explained.

Figure +iI6 shows the queue with 08PCB.

Generally, queue management in 77 Towa Air is realized in the form of table order management. To manage the order of tables, the first table address of the table forming the queue tm is stored in the pointer area corresponding to the resource, and the next table address is stored in the queue pointer area of each table. Let's do one ordering.

In FIG. 6, the execution queue pointer (hereinafter abbreviated as RQP B) 61Q of the 08 process and the resource queue pointer (hereinafter abbreviated as BSQB) 620 are filled with 08P.
The case where CB is connected and fc is shown.

The RQPB 610 stores the start address of 08PCB 500 and stores the pointer area 52 of the 08PCB 500.
0 stores the start address of the next 08 PCB. Thereafter, an execution queue is formed by storing the start address of the next 08 PCB in the same manner.

08PCB500 is connected to the execution queue by the OS
When a process is started, that is, in the OS process start processing routine, connection to the execution queue is made. The connection continues until the 08 process ends. Detaching 08PCB500 from the execution queue is O
This is done in the S process termination processing routine.

The 08DISP sequentially searches the execution queue starting from the head 08PCB of the execution queue, and selects the OS process corresponding to the first 08PCB found in an executable state.

-"・Re'-3 Samurai Matrix,..., R8QB620"
7- Store the start address of the 08 PCB at the beginning of the space queue,
The next 08 PC is placed in the pointer 2 area 530 of the 08 PCB.
It is formed by storing the start address of B. If it is connected to a resource queue, it must also be connected to an execution queue.

Registration in the resource queue is performed when the 08 process selected by 08DI8P operates and attempts to occupy a certain resource, but the resource is already occupied by another OS process. At that time, the program is not separated from the execution queue.

Detachment from the resource queue is performed at the timing when the occupied resource is released and becomes usable.

During resource queue connection, the 08PCB oENQ bit is 552rtl. That is, the bit 552 is set to 1 when the resource queue is registered, and set to 0 when the resource queue is disconnected.

The present invention is characterized in that the execution queue has 1 gA common to all processors. 081) of each processor
When I8F is activated, it searches the main execution queue 4, selects one executable 087' process, and executes the process described above.
N pick) 551 to 1, the execution processor number 540
Set the own processor number to , and run the OS process. When the OS process is waiting for resources or has finished, the execution queue is referred to again and the next OS process is executed.
Select a process.

However, in the case of this method, there is no executable 08 process.
, there is a possibility that the start of execution of the newly activated 7' COS process will be delayed. In other words, even if another processor connects a new 08PCB to the execution queue when a processor is in an idle state (processing an IDLE run), the idle processor
Unable to select the corresponding OS process.

Therefore, in the present invention, the tz, os process dispatch request interrupt, and processor status register (hereinafter referred to as PS
Abbreviated as B. ), this prevents delays in the OS process selection process.

FIG. 7 is a configuration diagram of the PAB.

The P8R700U is a 16-bit register, and one pit is allocated to each processor.

In the figure, P1 is assigned to one processor, P2 is assigned to processor 2, and bits up to P16, that is, up to 16 processors, are assigned.

When each bit is 0, it indicates that the OS process is not being executed on the corresponding processor, and when it is 10 o'clock, it indicates that the OS process is being executed on the corresponding processor. Ot-set when the process exists.

FIG. 8 is a system configuration diagram showing the arrangement of P8H.

The P8R700 is mounted inside the MCU 301 and can be set and reset by each processor.

Currently, aS process is running on P321, 322.323,
Assuming that the OS process is not running in P324, P8
The bits corresponding to P321 to P323 of R700 are set to 1, and the bits corresponding to fi and P324 are set to 0. In this state, if a request to start a new 08 process occurs in P321 and fc, P8R700 is referenced from P321 and a processor whose bit is set to O is found. In this example, since the bit of P324 is 0, P32
08 process disbunch request interrupt is applied from 1 to P324. This interrupt is performed using the interrupt function of the system bus 311 described above. That is, a communication area 800t is provided on the MS 101, communication information, that is, an OS process dispatch request message is set in the area 800, and a communication interrupt is generated.

FIG. 9 shows a schematic flow of 08 process dispatch request interrupt processing.

The OS process dispatch request interrupt saturation process 00 first refers to P8R700 to detect a processor that is not executing an OS process (block 901). If all processors are executing OS processes, the process returns without doing anything (block 902). This is because 08PCB of the newly started fcos process i'' is already connected to the execution queue, so it will eventually be selected by one of the processors. As a result of the P88700t check, the OSS process If there is a processor that is not executing, a contact interrupt is issued to that processor (block 903).

The mechanism for controlling the OS process has been explained above, and next, the general flow of the program for controlling the OS process will be explained using diagrams. OSS process control program, shown in Figure 4, fcla, 08DISP, O
S process startup routine.

087' Process termination routine, resource occupation routine,
Consists of resource release routines.

FIG. 10 shows a schematic processing flow of 08DI8P431.

First, 008 PCB from the top of the OS process execution queue.
is searched and an executable 08 process is selected (block 1001). If there are no executable OS processes, proceed to block 1004.

(Block 1002). If there is an executable 087' process (block 1002), set the RUN bit of the 08PCB to 1 and set the execution process number, then 08P.
The program start address of the CB is captured and jumps to the address (block 1003).

- In block 1004, the bit corresponding to the own processor of the ps 700 is set to 0 and linked to the TKDI8P.

FIG. 11 shows a schematic flow of the 08 process startup process.

In the startup process 432, parameters are taken in at block 1101. As a parameter for the startup process, a number indicating which OS process is to be started is passed.

The number tOi is called a process number, and the ninth number that identifies the OS process is numbered in a one-to-one correspondence with the 08 PCB. Therefore, depending on the OS process number, the corresponding ospca
address can be calculated. Next, connect to the corresponding 08PCB t-execution queue (block 1102). After that, O
Apply S process die punch cost water interruption (block 1
103). As already explained using FIG. 9, this process refers to the PS8 and interrupts the i-processor that is not executing the OS process.

FIG. 12 shows an outline 70- of the OS process termination process.

The termination process 433 first selects the corresponding 08 PCB from the execution queue.
(block 1201). Next, the status area of 08PCB is cleared to 0 (block 1202).

After that, link to 08DISP and run the next OS
Move on to process selection processing.

The end processing causes the B bit in ospca to become 0.

FIG. 13 shows a schematic flow of resource waiting processing of the OS process.

The resource waiting process 434 consists of a status operation (block 1301) and a queue operation (block 1302). At block 1301, t! , by setting the ENQ bit in the 08 PCB to 1, thereby placing the #08 process in a resource waiting state. Next, it is registered in the resource queue using the pointer 2 area in the 08 PCB. The address of the resource queue pointer 8QB is taken as a parameter of this routine and will be added to the queue connected to the address 08PCBd.

The 14th @ is the general flow of resource release processing. 69, 08P from the R8QB address given as a parameter
Search the CB queue until 08PCB is exhausted.
08 Returns 9 to delete the PCB from the queue. That is,
Check whether there is a queue for 08PC13 in the corresponding resource (block 1401), and if so, the first 08PC
B is deleted from the queue (block 1402). next,
ENQ bits 1-0 in the status area of the 08 PCB
and clears the waiting display (block 1403). Finally, a dispatch request interrupt is issued to the OS file (block 14G4), and this process is realized by linking to the routine shown in FIG. And next 08P
Check CB and return if not found.

When the OS process control mechanism according to the present invention is used as described above,
Communication between computers in the conventional multi-computer system shown in FIG. 2 is as shown in FIG. 15.

In this figure, computer A has processor A1. A2:.

Computer B is composed of processors B1 and B2. OS for communication between computers
If we look at the program in detail, it can be divided into several parts and processed in parallel. In other words, on the computer A side, the process of making task α wait for a response communication and the process of writing communication information @ to GMIIO and issuing a communication interrupt to computer B can be performed in parallel, and on the computer B side, task β can be processed in parallel. The process of activating and the process of writing response information to GMllo and issuing a communication interrupt to computer A can be processed in parallel. Therefore, each of these processes is registered as one OS process.

The flow of processing will be explained below using figures.

When task α of computer A issues a startup request for task α of computer B, task startup SVC processing 082
31KfllJ control is transferred. In 08231, the process ends by simply starting the OS process a1501 and the OS process b1502. The launched OS processes a and b are
Procera? A1. When the task .alpha. starts operating independently at A2, and the task .alpha. is placed in the state of waiting for a response, a communication interrupt is sent to the computer B at the same time. On the computer B side, interrupt processing 08233 is performed according to the communication interrupt.
is started. In 08233, 08 process C15
03 and OS process d 1504 are activated. The activated OS processes c and d start operating independently on the processors Bl and B2, and the 08 process 01503 starts operating on the processors B1 and B2.
Referring to the communication block of M, task β
Start.

On the other hand, the OS process 41504Fi issues a communication interrupt to computer A and returns a response.

As mentioned above, part of 08? By registering it as an OS process, it is possible to improve performance by enabling parallel processing of the OS.

This is an evening time chart of the 161st iAti, computing institution communication in a multi-computer system.

In the figure, (x) shows the case using the conventional O8, and (b) shows the case according to the present invention.

In the case of the present invention, both the time from when task α issues a start request to task β until it starts operating again, and the time from when task α issues a start request to task β until task β starts operating, are better. It has been shortened and the responsiveness of O8 has been improved.

According to the present invention, in a system composed of multiple processors, a part of 08 can be realized as an OS process,
Each OS process runs in parallel on multiple processors, and
8's responsiveness and, by extension, the system's performance Ir! It becomes possible to improve the

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram of a conventional multi-computer system, FIG. 2 is an overall processing diagram of conventional inter-computer communication, FIG. 3 is a system configuration diagram of a multi-computer system that implements the present invention, and FIG. The figure is an overall program configuration diagram of O8 according to the present invention, the A8s diagram is a table configuration diagram of 08PCB, and Figure 6 is a diagram of the 08PCB table configuration.
FIG. 7 is a configuration diagram of PAB, FIG. 8 is a system configuration diagram showing the arrangement of PAB, and FIG. 9 is an OS process dispatch request interrupt processing flow.
g1(1+d, 08DISP O treatment N7o-1aII
Figure 1 shows the startup processing flow of the OS process, and Figure 12 shows the
FIG. 13 shows the resource processing flow of the 08 process. FIG. 14 shows the resource release processing flow of the OS process Ω-1. FIG. 15 shows the overall process of communication between computers using the present invention. Clay drawing, jl 1
FIG. 6 shows a mayme chart for communication between computers. Agent Patent Attorney Toshiyuki Usuda 312- 313- 314- 315-

Claims (1)

[Claims] 1. In a multiprocessor system equipped with an 111IkO processor and a shared memory that can be referenced and updated in common by the processor, one management table is allocated to each of the O8 program modules that can be independently and concurrently processed. The execution method of O8 enables scheduling of the program module by having a queue pointer area in the management table and means for registering the management table in the queue. 2. In the O8 execution method described in claim 1, the management table includes a flag indicating that the O8 program module corresponding to the management table is being executed in a certain processor and identification of the cough processor. means for setting the flag and processor identification information in the management table before starting execution on the processor of the program module t, and resetting the flag when processing of the program module ends. means t-, and while the flag is set, processors other than the processor identified by 19 in the processor identification information of the management table are set to a rest state in which the program module is not executed. Execution method of O8 characterized by program module t--no travesty t-. 3. Range of %*fi request In the fcOS execution method described in item 1, each processor has a register that can be referenced and updated in common, and a means for issuing an interrupt between each processor, and each processor has a register that can be referenced and updated in common. Before executing the program module, each processor sets a bit in the register assigned to the processor to confirm that there is no program module to be executed by the processor. By detecting the bit and resetting the bit at the 9th point, the program module O start request generated in a certain processor is transmitted to the processor whose bit in the register has been reset through an interrupt, and the program is executed in each processor. An O8 execution method characterized by equalizing the load due to module execution.