JPH063903B2 - Clock reproduction circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for reproducing a clock from a burst-like modulated signal such as satellite communication time-division multiplexed, and more particularly to a phase detection for clock reproduction of two or more systems. The present invention relates to a clock reproduction circuit suitable for stably reproducing a clock from a modulated signal in which two or more possible signals are time-division multiplexed.

[Background of the Invention]

As described in Japanese Patent Laid-Open No. 55-49056, a conventional clock recovery circuit for recovering a clock from a burst-like modulated signal is a PLL with excellent noise resistance and characteristics, and a wide band with a fast rise at the beginning of the burst. By switching between the resonance circuit and the resonant circuit, the transient response is fast at the beginning of the burst, and after the transient time, a clock signal with less noise can be reproduced. However, no consideration was given to reducing the noise of the clock signal reproduced during the transition near the beginning of the burst.

The MUSE system is a band compression transmission system of television signals developed for the purpose of implementing high-definition broadcasting. In connection with this MUSE system, audio signals are digitally encoded and FM-modulated video signals. RF-TDM that directly QPSK-modulates the same carrier frequency and time-division-multiplexes the voice signal for transmission during the vertical blanking period of
(Radio Frequency-Time Div
The Ion Multiplex method has been proposed.

That is, in this case, each of the audio signal and the video signal is a burst modulation signal when viewed alone.

When demodulating such a burst-shaped modulated signal, when the demodulation target is changed to the audio signal (burst) with the clock used for demodulating the video signal (burst) (especially at the beginning of the change), the audio signal demodulation It is normal for the clock for use to have a phase shift rather than an appropriate phase (this phase shift is called the noise of the clock signal here). ,
In the past, no consideration was given to correcting this phase shift.

[Object of the Invention]

An object of the present invention is to obtain a modulated signal that is time-division-multiplexed in a burst form when receiving a transmission method in which the first burst signal and the second burst signal have different modulation schemes and have the same clock speed or an integral multiple. An object of the present invention is to provide a clock reproduction circuit which reproduces a clock with less noise even near the beginning of a burst when reproducing the clock.

[Outline of Invention]

The point of the present invention is that, when the first burst signal and the second burst signal have different modulation systems and the same clock speed is received or a transmission system with an integral multiple is received, time-division multiplexed modulation signals of two or more systems are received. Each of them is demodulated, the clock of the stable clock recovery circuit output is passed through the variable delay circuit, and the difference between the output and the clock phase of the demodulation signal obtained from the demodulation circuit of the other system is used in order to use it as the clock of the other system. Is detected and its output is used to control the delay time of the variable delay circuit to obtain a stable clock with less noise.

Example of Invention

An embodiment of the present invention will be described below with reference to FIG. 1 is an input terminal, 2 and 3 are demodulation circuits, 4 is a clock recovery circuit,
Reference numeral 5 is a phase detector which constitutes the clock regeneration circuit 4, 6 is a loop filter which constitutes the clock regeneration circuit 4, 7 is a voltage controlled oscillator which constitutes the clock regeneration circuit 4, 8 is a voltage controlled variable delay circuit, and 9 is Phase detector, 10 timing generation circuit, 11 sample hold circuit, 12 switching circuit,
Reference numeral 13 is a loop filter, 14 is a phase synchronization detection circuit for determining whether the clock recovery circuit 4 normally generates a clock, and 15 is a voltage generation circuit.

The time-division-multiplexed modulated signal input to the input terminal 1 is demodulated by the demodulation circuit 2 and the demodulation circuit 3. Now, the time-division-multiplexed signal is, for example, a signal in which the output of the demodulation circuit 2 is longer than the output of the demodulation circuit 3, and it is better to regenerate the clock from the output of the demodulation circuit 2. ,
It is assumed that a clock having a higher stability than that of the clock output from the demodulation circuit 3 can be reproduced, and the clock frequencies of the output of the demodulation circuit 2 and the output of the demodulation circuit 3 are the same. A clock is regenerated from the output of the demodulation circuit 2 by a clock regenerator circuit 4 configured by a PLL with a phase detector 5, a loop filter 6 and a voltage controlled oscillator 7. Since the clock reproduced by the clock reproducing circuit 4 has high stability and the same frequency as the clock reproduced from the output of the demodulating circuit 3,
The phase detector 9 compares the phase of the clock signal via the voltage controlled variable delay circuit 8 with the output of the demodulator circuit 3, and the output is voltage controlled via the sample hold circuit 11, the switching circuit 12 and the loop filter 13. By negatively feeding back the signal to the variable delay circuit 8, the clock whose phase is matched with the output of the demodulation circuit 3 is reproduced. In this way, the stable clocks are phase-compared via the variable delay circuit, and the negative delay is fed back to the variable delay circuit to adjust the phase suitable for the output of the demodulation circuit 3. Therefore, the stable clock is stable even at the beginning of the burst and the demodulation circuit 2 or Even if the delay time difference 3 changes, a clock having a phase suitable for the output of the demodulation circuit 3 can be obtained.

Sample and hold circuit 11 and timing generator circuit 10
Is for conducting the time-division-multiplexed signals efficiently by demodulating the time-division-multiplexed modulation signal only during the period when the demodulation circuit 3 normally obtains the demodulation output and holding the other period. . Further, the phase synchronization detection circuit 14, the switching circuit 12 and the voltage generation circuit 15 keep the control voltage of the voltage controlled variable delay circuit 8 constant and open the negative feedback loop while the clock recovery circuit 4 is not performing normal clock recovery. This is to prevent malfunction by closing the negative feedback loop only after the clock recovery circuit 4 has normally recovered the clock.

Next, an embodiment in which the present invention is applied to a satellite broadcasting system will be described. A satellite broadcasting system is NHK in July 1984.
It is "New transmission system for high-definition television ~ MUSE ~" described on pages 19 to 30 of Vol. 27, Giken monthly report. 27th
As described in the audio multiplex method on the page, one embodiment of the present invention for demodulating a transmitted audio signal by modulating a video resample clock with an audio clock whose frequency and phase match Shown in Figure 2. That is, in the MUSE system, since the video signal is sent in an analog format, it is A / D converted and digitally processed. The sampling clock used in this A / D conversion is a resample clock. On the other hand, in the MUSE system, the sample clock of the audio signal modulated and transmitted by QPSK has the same frequency as the resample clock of the video signal,
Although they are originally sent in the same phase, there may be a delay time difference or temperature drift in the middle of transmission,
It is not appropriate to use the resample clock for the video signal as it is as the sample clock for the audio signal, and this must be corrected. An embodiment applied in such a case is shown in FIG. 16 is a signal input terminal, 17 is a video system demodulation circuit, 18 is an FM demodulation circuit, 19 is a clock reproduction circuit, 20 is a video system signal processing circuit, 21 is a video output, 22 is an analog / digital conversion circuit, and 23 is a digital phase. Comparator, 24 is a digital loop filter, 25 is a digital / analog conversion circuit, 26 is a voltage controlled oscillator, 27 is a phase synchronization detection circuit, 28 is a timing generation circuit, 29 is a mixer, 30 is a local oscillator, 31 is 4 Phase and phase detector, 32 and 33 are data strobe circuits, 34 and 35 are multipliers, 36 and 37 are analog phase detectors,
38 is an adder, 39 is a sample and hold circuit, 40 is a voltage generation circuit, 41 is a switching circuit, 42 is a loop filter, 43 is a voltage-controlled variable delay circuit, 44 is a digital signal processing circuit, 45
Is a digital-analog conversion circuit, 46 is a cutoff circuit, 47
Is an audio output.

The modulated signal is input to the signal input terminal 16, and the video system demodulation circuit 17 demodulates the video system to obtain the video output at the video output 21. The input signal is FM-demodulated by the FM demodulation circuit 18, analog-digital converted by the analog-digital conversion circuit 22, digitally signal-processed by the video signal processing circuit 20, and by the built-in digital-analog conversion circuit. It is converted and obtained as the video output at the video output 21. The clocks used in the video system signal processing circuits 20 and the audio system demodulation circuits shown in 29 to 47 are analog-to-digital converted, and the output digital signals are phase-compared by the digital phase comparator 23. The conversion circuit 25 converts it into an analog signal and controls the voltage-controlled oscillator 26. The voltage-controlled oscillator is fed back as the conversion timing clock of the analog-digital conversion circuit to regenerate the clock synchronized with the modulated signal.

On the other hand, the modulated signal is frequency-converted by the mixer 29 and the local oscillator 30, and four-phase phase detection is performed by the four-phase phase detector 31 to obtain baseband transmission waveforms, so-called I and Q eye patterns. Each waveform is squared by the multipliers 34 and 35 to extract the transmission clock frequency component, and the extracted clock frequency component and the clock and analog obtained by the video system demodulation circuit 17 and delayed by the voltage controlled variable delay circuit 43 Phase detector 36
And 37 for phase comparison, the error signal is added by adder 38, and the result is fed back as the control voltage of voltage controlled variable delay circuit 43 via sample and hold circuit 39, switching circuit 41 and loop filter 42, and transmitted. It is possible to obtain a clock whose phase matches the transmission waveform with the clock frequency component. This clock is used as a strobe clock for the data strobe circuits 32 and 33, and its output is converted into an analog signal from the digital signal of the voice transmitted by the digital signal processing circuit 44 and the digital / analog conversion circuit 45, and is passed through the cutoff circuit 46. A voice signal is obtained at the voice output 47. The sample-hold circuit 39 and the timing generation circuit 28 conduct (sample) the time-division-multiplexed modulated signal while receiving the audio signal, and hold the previous value while receiving the video signal. This is for preventing disturbance due to video signals, promptly converging to a desired value during the conduction period, and performing efficient demodulation. Phase synchronization detection circuit 27, switching circuit 41, voltage generation circuit 40 and cutoff circuit
Reference numeral 46 is for opening a feedback loop to prevent malfunctions when the clock generation circuit 19 is not performing normal clock reproduction, and for cutting off audio output to prevent abnormal sounds.

The frequency conversion in the mixer 29 and the local oscillator 30 is used because the FM demodulation circuit 18 and the 4-phase detector 31 have different proper frequencies of operation, but they are not provided when they can be demodulated and detected at the same frequency. May be. Further, the multipliers 34 and 35, the analog phase detectors 36 and 37, and the adder 38 detect the clock phase from both the I and Q waveforms of the four-phase phase and the detection output, and the adder 38 averages the feedback loop. Although configured, if only one of I or Q operates, the multiplier 34, the analog phase detector 36 and the adder 38 are deleted, and the output of the analog phase detector 37 is input to the sample hold circuit 39. Alternatively, the multiplier 35, the analog phase detector 37 and the adder 38 may be deleted and the output of the analog phase detector 36 may be connected to the input of the sample hold circuit 39.

In the embodiment of the present invention shown in FIGS. 1 and 2,
The clocks of the same frequency that can reproduce the clocks of two systems and have a fixed phase relationship have been described. It may be used after the phase is locked by the PLL having the frequency divider of each integer.

Next, a concrete circuit of the voltage controlled variable delay circuit is shown in FIG.
It is shown in FIG. 48 is an input terminal, 49 is an output terminal, 50 is a voltage control input terminal, 51, 52, 53 are coils, 54, 55, 56 are varicaps, 57 are resistors, 58 is a capacity, 59 to 64 are inverters, 65, 6
6,67 are resistors and 68,69,70 are varicaps. Both use the fact that the capacitance of the varicap changes as the voltage of the voltage control input terminal 50 changes.

Next, FIG. 5 shows an example in which the variable delay amount of the voltage-controlled variable delay circuit is large. Reference numeral 71 is an input terminal, 72 to 75 are delay circuits having a fixed delay amount, 76 is a switching circuit, 77 is a voltage control type variable delay circuit as shown in FIG. 3 or 4, 78, 7
Reference numeral 9 is a comparator, 80 and 81 are voltage sources for comparison voltage of the comparators 78 and 79, and 82 is a control circuit for controlling the switching circuit 76. Four fixed delay circuits 72 to 75 are provided in series, and the output from the middle of them is switched by the switching circuit 76. The delay amount of the fixed delay circuit is minutely changed by the voltage control type variable delay circuit to change the variable amount. Enlarge. First of all, the switching circuit 76 is arranged at the center (73
And the voltage control input terminal 50 controls the voltage control type variable delay circuit 77, but the delay time is short and the voltage of the voltage control input terminal 50 is raised, for example. When the value reaches a value, the comparator 78 inverts and the switching circuit is switched via the control circuit 82. When switching to the connection point of 74 and 75, the delay time increases, and the optimum delay time can be achieved while controlling the voltage-controlled variable delay circuit 77. . On the contrary, the switching circuit 76 is connected at the connection point of 74 and 75, and if the delay time is too long, the comparator 79 is inverted when the voltage of the voltage control input terminal 50 reaches a certain value. Switch circuit 76
Switch to the connection point of 73 and 74. In this way, when the control voltage tries to deviate from the control range of the voltage-controlled variable delay circuit 77, it is detected by the comparators 78 and 79 and the fixed delay amount is switched to increase the variable delay amount.

Next, FIG. 6 shows an embodiment of the present invention when a variable delay circuit as shown in FIG. 5 is used. 83 is a control circuit,
The same reference numerals as those in FIG. 2 indicate the same functions. Switching circuit 76
When there is a possibility that an abnormal sound will be generated in the audio output when switching between the two, the output of the phase synchronization detection circuit 27 is phase-synchronized by ORing the output of the phase synchronization detection circuit 27 and the output of the control circuit 82. Even if not performed, the audio output is cut off even when the switching circuit 76 is switched by the output of the control circuit 82.

A concrete example of the control circuit 83 is shown in FIG. 85 is an input terminal connected to the output of the phase synchronization detection circuit 27, 86 is an input terminal connected to the output of the digital-analog conversion circuit 45, 87 and 88 are OR circuits, 89 and 90 are comparators, and 91 and 92 are It is a voltage source for the comparison voltage of the comparators 89 and 90. When switching the switching circuit 76, since the control voltage changes, either the comparator 89 or 90 inverts. If either of them inverts, a signal appears at the output of the OR circuit 87, so that the cutoff circuit 46 passes through the OR circuit 88. The voice output is turned off by turning off. On the other hand, when the phase synchronization detection circuit 27 detects that the phase is not synchronized, the interruption circuit 46 is interrupted via the input terminal 85 and the OR circuit 88.

〔The invention's effect〕

According to the present invention, the modulation method of the first burst signal and the second burst signal is different, and the transmission method having the same clock speed or an integral multiple is received, and the clock of the first burst signal is originally used. Upon receiving the transmission method that can be used for the clock of the second burst signal, in order to absorb the variation due to the delay time difference of the demodulation system and the temperature change, the stable clock reproduction of the first burst signal and the second burst signal is performed. Since the clock of either system is delayed by the variable delay circuit and the phase is compared by the other playback system to control the delay amount, it is not necessary to speed up the response unlike the case where the frequency is different, and the loop filter can be operated sufficiently. Can and second
Even if there is no preamble period for clock-in at the beginning of the burst signal, there is an effect that a clock with less noise can be reproduced even near the beginning of the burst.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of another embodiment of the present invention, FIG. 3 is a circuit diagram of a specific example of a voltage-controlled variable delay circuit, and FIG. Another specific example circuit diagram of the voltage control type variable delay circuit, FIG. 5 is a further specific example circuit diagram of the voltage control type variable delay circuit, and FIG. 6 is a circuit diagram of still another embodiment of the present invention. FIG. 7 is a circuit diagram of a specific example of the control circuit of the audio output cutoff circuit. 2, 3 ... Demodulation circuit, 4, 19 ... Clock recovery circuit, 8, 43, 77 ... Voltage controlled variable delay circuit, 9, 36, 37 ... Phase detector, 11, 39 ... Sample / hold circuit, 12, 41 … Switching circuit, 14,27… Phase synchronization detection circuit, 46… Cutoff circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 7/00 A 9070-5C

Claims (6)

[Claims] 1. The first burst signal and the second burst signal transmitted in time series have different modulation systems, and the clock speeds of the first burst signal and the second burst signal are the same or integer multiples. In a clock recovery circuit for receiving a transmission signal composed of such a first burst signal and a second burst signal and extracting a clock, one of the received first burst signal and second burst signal Clock recovery means for extracting and reproducing a clock from one burst signal, voltage controlled variable delay means for inputting and delaying the clock extracted by the clock recovery means, and outputting the first burst signal and the second burst signal. Out of the burst signal of
The other burst signal is taken in, the phase thereof is compared with the phase of the clock delayed by the voltage control type variable delay means, the phase difference is detected and output, and the phase comparison means from the phase comparison means Filter means for inputting the phase difference output and band-limited, and outputting the output of the filter means to the voltage controlled variable delay means so that the phase difference detected by the phase comparing means becomes zero. A clock control circuit for controlling the voltage controlled variable delay means, wherein the clock output from the voltage controlled variable delay means is used as the clock for the other burst signal. 2. A clock regeneration circuit according to claim 1, further comprising a interruption means for interrupting an input or an output of the phase comparison means. 3. The clock regenerating circuit according to claim 1, further comprising sampling holding means for conducting and pre-holding the output of the phase comparison means. 4. A clock regenerating circuit according to any one of claims 1 to 3, wherein a phase synchronization detecting means for detecting whether or not the output of the clock regenerating means is stable. And a switching means for controlling the output of the phase comparison means to switch between the output of the phase comparison means and a constant voltage value controlled by the phase synchronization detection means to conduct to the voltage controlled variable delay means. Clock recovery circuit. 5. The clock recovery circuit according to any one of claims 1 to 4, wherein the first burst signal is a frequency-modulated video signal, and the second burst signal is a frequency-modulated video signal. The burst signal is a phase-modulated digital information signal, and the clock reproducing means outputs a clock phase-synchronized with the horizontal synchronizing signal of the video signal. 6. The clock reproducing circuit according to claim 5, wherein the digital information signal is a voice signal which is analog-digital converted by pulse code modulation.