JPH0638640B2 - Image processing method - Google Patents

Description

TECHNICAL FIELD The present invention relates to an image processing method, and more particularly to an apparatus for processing an image using a memory.

2. Description of the Related Art Image processing such as image reduction, enlargement and movement can be performed by digitizing a video signal and writing it in a memory, and reading the digitized video signal from this memory by designating an address different from that at the writing. In addition, it is possible to obtain an afterimage effect by writing only a moving part of the video signal in the memory and synthesizing and outputting the part and the other part that has already been written. .

In order to obtain this afterimage effect, a method of detecting a portion of the video signal corresponding to a moving object and writing only that portion can be considered. In addition, a memory for storing data for one field is additionally required, which causes a problem that the configuration becomes complicated.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an image processing method capable of obtaining an afterimage effect with a device having a simple structure.

According to an image processing method of the present invention, a screen on which an image is formed by a video signal is divided into a plurality of areas, and image data at each point in at least one of the plurality of areas corresponds to each storage position in the memory. To write to n
It is characterized in that it is performed only in one field period selected from (n is a natural number of 2 or more) field periods.

Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In FIG. 1, the video signal is A / A via the input terminal IN.
D (analog / digital) converter 1, area discrimination circuit 2
And the field cycle processing circuit 3. A /
In the D converter 1, the video signal is sampled at a predetermined sampling frequency, and image data corresponding to the obtained sample value is generated. The image data output from the A / D converter 1 is supplied to the memory 4. The memory 4 has, for example, a storage capacity capable of storing all image data generated in one field period, and has a plurality of storage positions corresponding to respective points on the screen where an image is formed by a video signal. There is.

The area discrimination circuit 2 is, for example, a counter that is reset by a horizontal synchronizing signal in the video signal and counts up with a clock having the same frequency as the sampling frequency in the A / D converter 1, and a counter that is reset by the vertical synchronizing signal in the video signal and is horizontal. A counter that counts up according to a synchronizing signal, and the image data supplied to the memory 4 by the output data of these two counters is divided into areas A and B on the screen as shown in FIG. High-level area A by judging whether it is point data
It is configured to generate one of a signal and a region B signal. Area A output from this area discrimination circuit 2
The signal is one input of the OR (logical sum) gate 5. The area B signal output from the area determination circuit 2 is supplied to one input terminal of a 2-input AND (logical product) gate 7. The output of the field cycle processing circuit 3 is supplied to the other input terminal of the AND gate 7. The field cycle processing circuit 3 is configured to generate a positive polarity pulse as shown in FIG. 3 which has a pulse width corresponding to one field period and which is generated in four field cycles by the vertical synchronizing signal in the video signal. There is.

The output of the AND gate 7 is the other input of the OR gate 5. The output of the OR gate 5 is supplied to the memory controller 6. The memory controller 6 controls the memory 4 so that the image data sequentially supplied to the memory 4 is sequentially written to the corresponding storage positions, and the storage data of each storage position is sequentially read in a predetermined order. In this memory controller 4, the high level signal output from the OR gate 5 acts as a write command, and only when the high level signal is output from the OR gate 5, each storage position of the memory 4 is stored. Image data is written to the.

The image data read from the memory 4 is supplied to the D / A converter 8 and converted into an analog signal, and then supplied to the output terminal OUT and sent to a video reproducing device such as a color monitor.

In the above configuration, when the image data of each point in the area A is supplied to the memory 4, the area discrimination circuit 2 outputs the area A signal. Then, a high level signal is output from the OR gate 5. When the high level signal is output from the OR gate 5, the image data is written to each storage position of the memory 4, so that the image data of each point of the area A is not written to each corresponding storage position. , For each field. Further, when the image data of each point in the area B is supplied to the memory 4, the area discrimination circuit 2 outputs the area B signal. Then, the AND gate 7 outputs a high level signal for one field period in four field cycles. Since the output of the AND gate 7 is supplied to the OR gate 5, the high level signal is output from the OR gate 5 in the period of 4 fields for 1 field period.
Therefore, the writing of the image data of each point of the area B to each corresponding storage position is performed only in one field period of the continuous four field periods.

Therefore, the video signal corresponding to the image as shown in FIG. 4A is supplied over the 5 field period, and the image data of each point of the areas A and B is supplied in the first 1 field period of the 5 field period. Assuming that writing is performed at each storage position of the corresponding memory 4, a video signal forming a moving image having an afterimage is supplied to the output terminal OUT as shown in FIG. 4 (B).

The area discrimination circuit 2 in the apparatus shown in FIG.
It is assumed that the area signal indicating each area is output when the storage location of the memory 4 corresponding to each point of each area in the case of division is designated. However, the area discriminating circuit 2 operates as shown in FIG. You may make it output the signal which shows each area | region when a screen is subdivided. By doing so, a video signal forming a moving image as shown in FIG. 6 is supplied to the output terminal OUT.

FIG. 7 is a block diagram showing another embodiment of the present invention. In the figure, an A / D converter 1, an area discrimination circuit 2,
Field processing circuit 3, memory 4, OR gate 5, memory controller 6, AND gate 7, D / A converter 8
Are connected in the same way as the device of FIG. However, in this example, the first
The area signal is supplied to one input terminal of a 2-input AND gate 9. The output of the field cycle processing circuit 3 is supplied to the other input terminal of the AND gate 9. The field cycle processing circuit 3 generates a pulse generated in a 4-field cycle as shown in FIG. 8 (A) and supplies it to the other input terminal of the AND gate 9 at the same time as in the device of FIG. As shown in FIG. 3B, a pulse generated in a 16-field cycle is generated and supplied to the other input terminal of the AND gate 7. AND
The output of the gate 9 is one input of the OR gate 5.

Although the afterimage effect can be obtained in the above-described configuration as in the apparatus of FIG. 1, the apparatus of FIG. 7 has an advantage that the current and past movements can be simultaneously viewed as a still image.

In the apparatus of FIG. 7, the field cycle processing circuit 3 may output two pulses having different generation timings in the same cycle as shown in FIGS. 9 (A) and 9 (B). .

Further, in both the apparatus of FIGS. 1 and 7, the write timing of the storage position of the memory 4 corresponding to each point of the areas A and B is fixed, but the write timing is set to a predetermined value. For example, the writing of each storage position of the memory 4 corresponding to each point of the area A in a certain period is performed in a 4-field cycle, and each storage position of the memory 4 corresponding to each point of the area B is changed at intervals. Is written in each field period, and in the next period, each memory location of the memory 4 corresponding to each point of the area A is written in each field period, and the memory corresponding to each point of the area B is written. Writing to each of the four storage locations may be performed only during one field period of four fields. By doing this, the "moving" part where the writing cycle is relatively fast and the "static" part where the writing cycle is relatively slow are not fixed on the screen, and a motion with a change on the entire screen is generated. be able to.

FIG. 10 is a block diagram showing still another embodiment of the present invention. In the figure, an A / D converter 1, an area discrimination circuit 2, a memory 4, an OR gate 5, a memory controller 6,
The AND gate 7 and the D / A converter 8 are connected in the same manner as in the device shown in FIG. However, in this example A
The output of the comparator 10 is supplied to the other input terminal of the ND gate 7. An audio signal in which a component in a predetermined band is emphasized by the equalizer amplifier 11 is supplied to the positive input terminal of the comparator 10. The reference level Vr is supplied to the negative input terminal of the comparator 11.

In the above configuration, the image when the music rises becomes an afterimage, and the image changes. For example, in the case of software such as so-called promotion video in which music and related images are recorded, It is possible to enhance the effect of music by adding a two-dimensional change of an image and a temporal change to the rhythm of music, rather than reproducing and viewing.

In the above embodiment, the screen is divided into a grid, but the screen may be divided as shown in FIG. Further, although the writing timing of each storage position of the memory 4 corresponding to each point of each area on the screen was two, the screen was divided as shown in FIG. 12, and the areas A, B and C were divided. It is also conceivable to set the write timings of the respective storage positions of the memory 4 corresponding to the respective points of D and D to the timings shown in FIGS. 13 (A) to 13 (D).

As described in detail above, the image processing method according to the present invention divides a screen on which an image is formed by a video signal into a plurality of areas, and stores image data of each point in at least one of the plurality of areas. Since writing to each storage location of the corresponding memory is performed only in one field period selected from consecutive n (n is a natural number of 2 or more) field periods, one field for detecting a moving object or the like The afterimage effect can be obtained by a circuit having a simple structure without separately providing a memory for storing minute image data. In addition, by changing the method of dividing the screen and the timing of writing the image data, it is possible to generate two-dimensional changes and temporal changes in the image at the same time. Will be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a screen division method, and FIG. 3 is a waveform showing an output of a field cycle processing circuit 3 in the apparatus of FIG. FIGS. 4 and 5 are views showing the operation of the apparatus of FIG. 1, FIG. 5 is a view showing another example of the screen dividing method, and FIG.
FIG. 7 is a diagram showing the operation of the apparatus of FIG. 1 when the screen is divided as shown in FIG. 7, FIG. 7 is a block diagram showing another embodiment of the present invention, and FIG. 8 is a field in the apparatus of FIG. FIG. 9 is a waveform diagram showing the output of the cycle processing circuit 3, FIG. 9 is a waveform diagram showing the output of the field cycle processing circuit 3 in the apparatus of FIG. 7, and FIG. 10 is a block diagram showing still another embodiment of the present invention. FIG. 11 is a diagram showing another example of the screen division method,
FIG. 12 is a diagram showing still another example of the screen dividing method, and FIG. 13 is a timing chart showing the write timing of each area when the screen is divided as shown in FIG. Explanation of symbols of main parts 2 ... Area discrimination circuit 3 ... Field cycle processing circuit 4 ... Memory 6 ... Memory controller

Claims (3)

[Claims] 1. A video signal of each point on the screen obtained by sampling the video signal in a memory having a plurality of storage locations corresponding to each point on the screen where an image is formed by the video signal. In the image processing method, a plurality of image data corresponding to the levels are sequentially supplied and written in the corresponding plurality of storage positions, and then the storage data of the plurality of storage positions are sequentially read in a predetermined order to process an image. Then, the screen is divided into a plurality of areas, and the writing of the image data of each point in at least one of the plurality of areas to each corresponding storage position of the memory is continued (n is 2). An image processing method, which is performed only during one field period selected from the above natural number) field period. 2. A field period (a) at each storage position of the memory corresponding to each point of a predetermined area of the plurality of areas.
Is a natural number) and is written in each storage position of the memory corresponding to each point of the area other than the predetermined area at a ma field period (m is a natural number of 2 or more and ma ≦ n). The image processing method according to claim 1, wherein the image processing method is performed. 3. A writing cycle to each storage position of the memory corresponding to each point of the predetermined area and the other area is alternately changed to a field cycle and ma field cycle at predetermined intervals. Claim 2 which is characterized by the above.
The image processing method described in the item.