JPH0638182A - Scanning line converter - Google Patents

Abstract

PURPOSE:To decrease a bit width of a line memory by converting an interlace signal through parallel processing so as to connect a coefficient multiplier before the line memory. CONSTITUTION:A 4n-th scanning line signal of an inputted non-interlace signal is written in a 1st memory 15, (4n+1)th and (4n+3)th scanning signals of the inputted noninterlace signal are written in a 2nd memory 16, and a (4n+2)-th scanning line signal of the inputted non-interlace signal is written in a 3rd memory 17. Then the scanning line signals written in the 1st-3rd memories 15-17 are read simultaneously by time axis expansion with a memory controller 18. Furthermore, since the signals after subject to multiplication processing by coefficient multipliers 11-13 are given to the line memories 15-17, a maximum value of the data from to the line memories 15-17 is smaller than those before inputted to coefficient multipliers 11-13 and the bit width of the line memories 15-17 is reduced in matching therewith.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scanning line conversion apparatus capable of converting a non-interlaced scanning type television signal into an interlaced scanning type television signal.

[0002]

2. Description of the Related Art Conventionally, in order to improve the image quality of a television signal, the frequency of a horizontal scanning line (hereinafter referred to as a line) is set to be twice the line frequency fH of a standard television signal (for example, NTSC system), and non-interlaced. There has been proposed a method of scanning a converted television signal.

In order to receive such a non-interlaced television signal on a standard television receiver,
It is necessary to convert the line frequency to fH, and the simplest method is to perform thinning processing for each non-interlaced scanning line having a line frequency of 2fH. However, if the line thinning processing is simply performed, the spatial sampling frequency in the vertical direction of the screen is reduced to 1/2, and aliasing distortion is generated, so that so-called flicker noise appears on the television monitor.

In order to avoid this, it is necessary to remove the aliasing distortion component in the vertical direction of the screen. Figure 1
It is a block diagram which shows an example of the conventional scanning line converter which converts a line frequency into fH, removing the aliasing distortion component of the screen vertical direction. Input line frequency 2fH
Line memory 1 and line memory 2 that delay the non-interlaced signal of 1 line by 1 line are connected in cascade,
And this non-interlaced signal is supplied to the coefficient multiplier 3. The output signal from the line memory 1 is the coefficient multiplier 4
And the output signals from the line memory 2 are supplied to the coefficient multipliers 5, respectively. With the above configuration, a digital filter that removes the aliasing distortion component in the vertical direction of the screen is configured. Further, the outputs of the coefficient multipliers 3, 4 and 5 are added by the adder 6, and the output of the adder 6 is supplied to the line memory 7. The line memory 7 performs time-axis expansion of the supplied signal and outputs it. The signal output from the line memory 7 is converted into an interlaced signal having a line frequency fH.

FIG. 2 is a timing chart for explaining the operation of the apparatus of FIG. 1, and is shown corresponding to the reference numerals in FIG. The line memory 1 delays the input non-interlaced signal of the line frequency 2fH line by line and outputs a signal as shown in FIG. Line memory 2
Outputs the signal shown in (b) by further delaying the signal shown in (a) supplied from the line memory 1 by one line. The coefficient multiplier 3 outputs the input non-interlaced signal multiplied by the coefficient α as shown in (c). The coefficient multiplier 4 multiplies the signal of (a) by the coefficient β (d).
It outputs like. The coefficient multiplier 5 outputs the signal of (b) multiplied by the coefficient γ as shown in (e). Adder 6
Respectively adds the signals of (c), (d) and (e) and outputs as in (f). The line memory 7 takes in (f) at the timing of the frequency fH which is 1/2 of the line frequency 2fH and outputs it.

As can be seen from the figure, the line memories 1, 2
Of the data of (f) written in the data and processed by the adder 6, the data generated every other line is not used at all and is in a thinned state. In the conventional scanning line conversion device as described above, each coefficient multiplier 3, 4 and 5
Since the timing processing is performed by the line memories 1 and 2 before performing the processing by, the bit widths of these line memories 1 and 2 are required to be the same as the bit width of the non-interlaced signal. For example, if the input non-interlaced signal is 8 bits, the bit widths of the line memories 1 and 2 are each 8 bits, and the bit width of the line memory 7 needs the same bit width. However, there is a problem that it increases in proportion to the bit width of the non-interlaced signal.

[0007]

SUMMARY OF THE INVENTION The present invention has been made to overcome such a problem, and it is a scan capable of reducing the total bit width of a line memory required to form a vertical filter. An object is to provide a line conversion device.

[0008]

An apparatus for converting a non-interlaced signal having a line frequency of 2fH into an interlaced signal having a line frequency of fH, wherein the non-interlaced signals are adjacent to each other 4n, 4n + 1, 4n +.
Of the 2 and 4n + 3 horizontal scanning lines, a first memory for writing a signal obtained by digitizing the 4nth scanning signal and a second memory for writing a signal obtained by digitizing the 4n + 1 and 4n + 3th scanning signals. A third memory for writing a signal obtained by digitizing the 4n + 2nd scanning signal, and a memory controller for controlling to simultaneously read the data respectively written in the first to third memories.

[0009]

The scanning line conversion apparatus of the present invention writes the input 4n-th scanning signal of the non-interlaced signal into the first memory and outputs the input 4n + of the non-interlaced signal.
The 1st and 4n + 3rd scanning signals are written in the second memory, the 4n + 2nd scanning signals of the input non-interlaced signals are written in the third memory, and the scanning written in these first to third memories The signals are read out at the same time and with the time axis expanded.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 is a block diagram showing the configuration of an embodiment of the scanning line conversion apparatus of the present invention. The digitized non-interlaced signal is supplied from the input terminals to the three coefficient multipliers 11, 12 and 13 respectively connected in parallel, and the sync separation circuit 14. The coefficient multipliers 11, 12 and 13 supply the values obtained by multiplying the input signals by the coefficients α, β and γ to the line memories 15, 16 and 17, respectively.
The memory control circuit 18 includes line memories 15 and 1
A write enable signal for individually writing 6 and 17 is supplied to each of the line memories 15, 16 and 17. Furthermore, the memory control circuit 1
Reference numeral 8 denotes a read enable signal for causing the line memories 15, 16 and 17 to perform reading.
And 17 respectively. Memory control circuit 1
Reference numeral 8 generates the above-described write enable signal and read enable signal in accordance with the generation timing of the horizontal sync signal separated by the sync separation circuit 14. Line memory 15, 1
Each of 6 and 17 includes a memory control circuit 18
When a write enable signal is supplied from the coefficient multiplier 1
The signals supplied from 1, 12, and 13 are written. Further, when the read enable signal is supplied from the memory control circuit 18, the line memories 15, 16 and 17 read the written data and supply it to the adder 19. The adder 19 includes line memories 15, 16 and 17
The data read from is added and output.

FIG. 4 is a timing chart for explaining the operation of the scanning line conversion apparatus of the present invention shown in FIG.
It is described in correspondence with the reference numerals given in FIG. The coefficient multiplier 11 multiplies the input non-interlaced signal (Xn to Xn + 6) of the line frequency 2fH by the coefficient α and outputs the product as shown in (a). The coefficient multiplier 12 multiplies the input non-interlaced signal of the line frequency 2fH by the coefficient β and outputs the product as shown in (b). The coefficient multiplier 13 multiplies the input non-interlaced signal of the line frequency 2fH by the coefficient γ and outputs the product as shown in (c).

The memory controller 18 includes a coefficient multiplier 1
Of the data such as (a) supplied from 1, only the 4nth data (n starts from 0, that is, the 0th data of (a) becomes αXn) is written. The write enable signal is supplied to the line memory 15. Further, the memory controller 18 uses the coefficient multiplier 1
A write enable signal for writing only the 4n + 1 and 4n + 3th supplied data out of the data (b) supplied from 2 is supplied to the line memory 16. Further, the memory controller 18 supplies to the line memory 17 a write enable signal for writing only the 4n + 2nd supplied data of the data (c) supplied from the coefficient multiplier 13.

The line memory 15 sequentially overwrites and stores only the 4nth supplied data among the data as shown in (a) according to the write enable signal supplied from the memory controller 18, as shown in the drawing. The line memory 16 stores 4n of the data shown in (b) according to the write enable signal supplied from the memory controller 18.
Only the data supplied at +1 and 4n + 3 are sequentially overwritten and stored as shown. The line memory 17 sequentially stores only the 4n + 2nd supplied data among the data as shown in (c) according to the write enable signal supplied from the memory controller 18, as shown in FIG.

That is, for the line memory 15,
The write enable signal is supplied once to the four data at the timing as shown in the figure, and the data written in the line memory 15 becomes αXn, αXn + 4 .... Further, the write enable signal is supplied to the line memory 16 once for every two data at the timings shown in the figure, and the data written to the line memory 16 are βXn + 1 and βXn +.
3, βXn + 5 ... Further, the write enable signal is supplied to the line memory 17 at a rate of once for each of the four data at the timing shown in FIG.
The data written in is γXn + 2, γXn + 6 ....

The memory controller 18 outputs a read enable signal for reading the data stored in the line memories 15, 16 and 17 to a line frequency of 2 fH.
Output as shown at the timing of the frequency fH of / 2. The line memories 15, 16 and 17 respectively store the data stored and held before the read enable signal is supplied (d) at the timing of the read enable signal,
Output as shown in (e) and (f). For example, in FIG. 4, the first read enable signal supplied from the memory controller 18 causes αXn stored and held in the line memory 15 to be read as shown in (d) and stored and held in the line memory 16. .Beta.Xn + 1 is read as shown in (e), and .gamma.Xn + 2 stored and held in the line memory 17 is read as shown in (f). Then, by the second read enable signal, αXn + 4 stored and held in the line memory 15 is read out as shown in (d), and βXn + 3 stored and held in the line memory 16 is stored in (e). .Gamma.Xn + 2, which has been read and stored in the line memory 17, is read as shown in (f). The values (d), (e) and (f) read out as described above are added by the adder 19 and output.

At this time, the timing output from the adder 19 is the same as the timing of the read enable signal supplied from the memory controller 18. Since the read enable signal is supplied at the timing of fH which is half the line frequency 2fH of the input non-interlaced signal, the adder 19 outputs the data whose time axis is expanded to the frequency fH. Will be. Therefore, the signal output from the adder 19 is converted into the interlaced signal having the line frequency fH.

In the scanning line conversion apparatus of the present invention as described above, the coefficient multipliers 11, 12 and 13 perform multiplication processing (multiplier is less than 1), and then the line memories 15 and 1 respectively.
Since 6 and 17 are used, the maximum value of the data supplied to each line memory is smaller than that before being input to the coefficient multiplier, and the bit width of each line memory is also reduced accordingly. You can

For example, as an example of the actual count value, α = 1 /
Assuming that 8, β = 3/4, γ = 1/8, and the bit width of input data is 8 bits, the maximum number in 8 bits is 255 (decimal number). When this is input to the device of FIG. 3, the output of the coefficient multiplier 11 is 255 × α = 255.
× 1/8 = 31.875. That is, the line memory 15 is never supplied with data larger than 31.875. Therefore, it is understood that 6 bits is sufficient for the line memory 15. Similarly, the output of the coefficient multiplier 12 is 255 × β = 255 × 3/4 = 191.25, so that the line memory 16 requires 8 bits.
The output of the coefficient multiplier 13 is 255 × γ = 255 × 1/8
= 31.875. That is, the data larger than 31.875 is never supplied to the line memory 17,
It turns out that 6 bits is sufficient.

Therefore, in the scanning line conversion apparatus of the present invention, when the multiplication coefficients of the coefficient multipliers 11, 12 and 13 are α = 1/8, β = 3/4 and γ = 1/8, respectively,
The bit widths of the line memories 15, 16 and 17 are 6 bits, 8 bits and 6 bits, respectively. Therefore, the total bit width of the line memory is 20 bits, and the total bit width of the line memory of the conventional device is 24 bits (8 bits × 3).
It has been reduced compared to.

[0020]

As described above, according to the scanning line conversion apparatus of the present invention, the 4n-th scanning signal of the input non-interlaced signal is written in the first line memory and the input non-interlaced signal of 4n + 1, And the 4n + 3rd scanning signal is written in the second line memory, the 4n + 2nd scanning signal of the input non-interlaced signal is written in the third line memory, and the scanning written in these first to third memories Since the signals are read out at the same time and with the time axis expanded and the interlaced signals are converted by parallel processing, a coefficient multiplier, which is a component of a filter that removes aliasing distortion components in the vertical direction of the screen, is used as a line memory. You will be able to connect before.

Therefore, the multiplication process of the coefficient multiplier (the multiplier is 1
Since the maximum value of the data after completion is smaller than that before the data is input to the coefficient multiplier, the bit width of the line memory can be reduced accordingly. Further, since the reading from the line memory is performed while expanding the time axis, the operation speed required for the adder for adding the time is 1/2 as compared with the conventional one.

[Brief description of drawings]

FIG. 1 is a block diagram of a conventional scanning line conversion device.

FIG. 2 is an operation time chart of a conventional scanning line conversion device.

FIG. 3 is a block diagram of a scanning line conversion apparatus according to the present invention.

FIG. 4 is an operation time chart of the scanning line conversion device of the present invention.

[Explanation of symbols for main parts]

 11, 12, 13 Coefficient multiplier 15, 16, 17 Line memory 18 Memory control

Claims (1)

[Claims] 1. A device for converting a non-interlaced signal having a line frequency of 2fH into a non-interlaced signal having a line frequency of fH, wherein the non-interlaced signals are adjacent to each other 4n, 4n.
Of the horizontal scanning lines n + 1, 4n + 2, and 4n + 3, a first memory for writing a signal obtained by digitizing the 4nth scanning signal and a second memory for writing a signal obtained by digitizing the 4n + 1 and 4n + 3th scanning signals. And 4n
A memory controller having a third memory for writing a signal obtained by digitizing the + 2nd scanning signal, and controlling so that the data respectively written in the first to third memories are read out at the same time and with the time axis expanded. A scanning line conversion device comprising: