JP2001008098A - Image processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a video signal at an optional reduction rate without deteriorating the image quality such as loopback distortion by applying sub sampling to an input video signal while applying prescribed filtering processing and recording only prescribed data. SOLUTION: In reduction in a horizontal direction, multipliers 6, 7 multiply signals 5a, 5b from a counter 5 with an input video signal 1, a 1 clock delay element 8 delays an output of the multiplier 7 by one clock time, an output of a switch 9 is summed to an output signal of the multiplier 6 by an adder 10, a 1 clock delay element 11 delays an output of the adder 10 by one clock and a line memory 12 stores the delayed signal. Let a reduction rate be n/M and number of bits of the counter 5 be p, then a relation of M=2(p-1) holds, and let k be a value excluding the most significant bit from the count value and let h be exclusive ORing between the most significant bit before the delay and the count value, then a signal 5b results from ORing the k and h and a signal 5a is a value resulting from substrating the signal 5b from the (n). The reduction in a vertical direction is conducted by the similar configuration to above.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly, to an image processing apparatus that can reduce an image without distortion.

[0002]

2. Description of the Related Art As an image processing apparatus for reducing a video signal, there is known an image processing apparatus disclosed in Japanese Patent Application Laid-Open No. 1-261976.

[0003] In the above publication, when performing vertical reduction of the screen, it is possible to remove aliasing distortion in the vertical direction by performing a filtering process.

[0004]

However, the above publication has a problem that the reduction ratio is fixed and the video signal cannot be reduced at an arbitrary reduction ratio.

The present invention has been made in consideration of the above problems, and has as its object to provide an image processing apparatus that solves the above problem.

[0006]

Means for Solving the Problems The present invention has the following arrangement to solve the above-mentioned problems.

That is, in an image processing apparatus which samples a video signal and converts it into a digital data sequence, the coefficient generating means for generating a predetermined coefficient is multiplied by a multiplication for sequentially multiplying the digital data sequence by the predetermined coefficient. And an adder for cumulatively adding the digital data sequence multiplied by the coefficient to adjacent digital data or digital data delayed by one scanning line, and a predetermined one of the cumulatively added digital data. And a memory for recording only the digital data.

Here, the image processing apparatuses may be connected in series.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to reduce a video signal without aliasing distortion, it is necessary to perform a filtering process on the input video signal and to perform sub-sampling for thinning out data.

Here, as one method of the filtering processing, the sampled and input time-series video signal data are weighted by n times, and then the average of the video signal data of a predetermined data sequence is obtained. It is known.

Therefore, in the present invention, sub-sampling is performed while performing the following filtering processing.

That is, the data sequence of the input video signal is x
(0), x (1), x (2), x (3)..., And the sub-sampled data sequence is y (0), y (1),
y (2), y (3)..., y (0) = (nx (0) + nx (1) + nx (2)... + (Mq · n) ) · X (q)) / My (1) = ((n− (M−q · n)) · x (q) + nx · (q + 1) + nx · (q + 2) + nx · (q + 3) + (2 · M− (1 + q + r) · n) · x (q + r + 1)) / My (2) =...

Here, n / M is a reduction ratio (n,
M is a positive integer), q is the reciprocal of the reduction ratio, M / n
Is an integer value obtained by truncating the decimal portion of r, and r is 2 · M /
This is an integer value obtained by truncating the decimal part of n−q−1.

A specific example will be described below.

N = 88, M = 256, that is, reduction ratio n /
If M = 0.34, q = 2, r = 2, and y (0) = (88 × x (0) + 88 × x (1) + 80 × x (2)) / 256 y (1) = ( 8.x (2) + 88.x (3) + 88.x (4) + 72.x (5)) / 256 y (2) = (16.x (5) + 88.x (6) + 88.x (7) ) + 64 · x (8)) / 256 y (3) =...

If n = 230 and M = 256, that is, if the reduction ratio n / M = 0.90, q = 1 and r = 0, and y (0) = (230 × x (0) + 26 ×). x (1)) / 256 y (1) = (204 · x (1) + 52 · x (2)) / 256 y (2) = (178 · x (2) + 78 · x (3)) / 256 y (3) = ... Equation (3) is obtained.

That is, when n = 88 and M = 256, y
(0) is a data sequence (x (t),
The sum of the data sequence of the input video signal multiplied by n (88 · x (0)) in a range where the sum of n multiplied by t = 0, 1, 2, 3,... + 88 · x (1)),
The difference between the sum of n (88 + 88 = 176) and M (256
−176 = 80) and the data sequence (80 · x (2)) of the input video signal.

Further, y (1) is the sum of the above n (88 + 8
8 = 176) and the difference between M (256-176 = 80) and n
The sum of the data sequence (8 × x (2)) of the input video signal multiplied by the difference (88−80 = 8) and n multiplied by the data sequence of the input video signal exceeds M Not in the range,
n (88 · x)
(3) + 88 · x (4)) and the sum of n (8 + 88 +
88 = 184) and the data sequence (72 · x (5)) of the input video signal multiplied by the difference between M and M (256−184 = 72).
Is the sum of

Hereinafter, y (3), y (4)... Are a repetition of the same operation as y (2).

FIG. 1 shows the configuration of the image processing apparatus according to the present invention which performs the above-described operations.

In FIG. 1, first, in order to reduce in the horizontal direction, a video signal input from an input terminal 1 is controlled by control signals 5a and 5b from a counter 5 for controlling a coefficient by which the video signal is multiplied, and a multiplier 6 , 7 are multiplied.

The output of the multiplier 7 is delayed by a delay unit 8 for delaying data by one clock, and then added via a switch 9 to the output signal of the multiplier 6 by an adder 10. Here, the switch 9 controls the control signal 5 from the counter 5.
Under the control of c, switching is performed so as to form a feedback loop in which a signal obtained by delaying the output of the adder 10 is input to the adder 10.

The output of the adder 10 is delayed by a delay unit 11 for delaying data by one clock, and then output to a line memory 12.
Will be recorded.

Next, reduction in the vertical direction is performed in the same configuration as the above-described reduction in the horizontal direction. At this time, instead of the delay units 8 and 11 for delaying the data for one clock, the line memories 16 and 19 for delaying one scanning line are used.
A field memory 20 is used instead of the line memory 12.

The video signals reduced in the horizontal and vertical directions are recorded in the field memory 20.

The operation of the image processing apparatus having the above configuration will be described below with reference to the timing charts shown in FIGS.

In FIG. 2, n = 88 and M = 256, and the operation of the counter 5 will be described first.

The "count" in the figure is the count value of the counter 5, where the number of bits of the counter 5 is p,
Let p be 9 bits. The counter 5 is reset by a horizontal synchronizing signal, and counts up in units of n (= 88) by a clock. Note that the number of bits p and M of the counter have a relationship of M = 2 ^(p-1) .

Here, “k” is a value obtained by removing the most significant bit from the “count” value, and the “most significant bit” is
This shows the most significant bit of “count”.

"H" indicates that the "most significant bit" is 1
It is delayed by the number of clocks and exclusive ORed with the "most significant bit" before the delay.

"5c" is obtained by delaying "h" by one clock, "5b" is the logical product of "k" and "h", and "5a" is n (= 88). ) To "5b"
Is subtracted.

The control signals "5a", "5b" and "5c" are output from the counter 5 by the above operation.

Next, the calculation with the input video signal will be described.

"1" is an input video signal.

"6a" is converted by the multiplier 6 into "1" and "5a".
Is multiplied, and “8a” is obtained by the multiplier 7 as “1”.
And “5b” are delayed by one clock. Incidentally, the lower p-1 (=
8) By truncating the bits, the same calculation result as that obtained by dividing by M (= 256) is obtained.

"9a" is the output of the switch 9. When the control signal of “5c” is “1”, the switch 9 sets “8”.
"a" is selected, and when it is "0", "11a" described later is selected.

"11a" is obtained by delaying the value obtained by adding "6a" and "9a" by the adder 10 by one clock. This value is fed back to the switch 9 and is temporarily stored in the line memory 12. The storage in the line memory 12 is performed only when "5c" is "1".

With the above operation, the operation result of the above equation (2) is stored in the line memory 12.

Further, the same operation as described above is performed in the vertical direction.

As for the reduction operation in the vertical direction, the counter 13 is reset by the vertical synchronization signal and is counted up by the horizontal synchronization signal. “5a” and “13” in FIG.
"a" is "5b" and "13b" is "5c" and "13
"c" correspond to each.

When n = 230 and M = 256,
The timing chart is as shown in FIG.

In FIG. 1, the field memory 20 is
By controlling for each clock, the line memory 12 can be omitted.

[0043]

According to the present invention, it is possible to reduce an image at an arbitrary reduction ratio while suppressing image quality deterioration such as aliasing distortion.

Further, since the filtering processing at the time of image reduction is of a cyclic type, it is possible to reduce the circuit scale, and it is also suitable for integration into an integrated circuit, thereby contributing to cost reduction. Becomes

Further, since the reduced image signal is stored in the field memory, a multi-screen or picture-in-picture can be easily realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an image processing apparatus according to the present invention.

FIG. 2 is a first diagram illustrating the operation of the image processing apparatus according to the present invention.
6 is a timing chart of FIG.

FIG. 3 is a second diagram illustrating the operation of the image processing apparatus according to the present invention.
6 is a timing chart of FIG.

[Explanation of symbols]

1 input terminal, 2 clock input terminal, 3 horizontal sync signal input terminal, 4 coefficient input terminal, 5 counter, 6 multiplier, 7 multiplier, 8 1 Clock delay element, 9 switch, 10 adder, 11 1
Clock delay element, 12 line memory, 13 counter, 14 multiplier, 15 multiplier, 16 line memory, 17 switch, 18 adder, 19
..Line memory, 20.Field memory, 21.
Horizontal input signal input terminal, 22 vertical input signal input terminal, 23 input coefficient input terminal

Claims (2)

[Claims] 1. An image processing apparatus for processing a video signal after sampling a video signal into a digital data sequence and processing the digital signal, a coefficient generating means for generating a predetermined coefficient, and a multiplication for sequentially multiplying the digital data sequence by the predetermined coefficient An adder for cumulatively adding the digital data sequence multiplied by the coefficient to adjacent digital data or digital data delayed by one scanning line; and a predetermined one of the cumulatively added digital data. An image processing apparatus, comprising: a memory for recording only digital data. 2. An image processing apparatus, wherein the image processing apparatuses according to claim 1 are connected in series.