JPH0638040A - Image data processor - Google Patents

Abstract

PURPOSE:To effectively utilize the storage area of a line memory for two lines by performing processing to use the data of three lines while using the memory. CONSTITUTION:Processing is performed to data Xn-1 of an attention picture element by using data SOUT after shading correction. The processing is executed by performing arithmetic to data Bn and Bn-1 of a present line, data An and An-1 of a line preceding to the last line and data Xn-1 of the attention picture element in the preceding line. Namely, the arithmetic is performed to the data of picture elements at prescribed positions in the matrix of 3X3 picture elements. When the data An of the line preceding to the last line are read from the memory, the data Bn of the present line are stored at the storage position of these data An. Therefore, the line memory for two lines is prepared in the memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data processing apparatus which is used in, for example, a facsimile machine or an image scanner, and which is preferably applied for filter processing utilizing the correlation of data between read lines. is there.

[0002]

2. Description of the Related Art For example, in a facsimile machine or the like, so-called filter processing for emphasizing a binary image is performed on data read by an image sensor. Such filter processing is performed by paying attention to a certain pixel and referring to data of pixels around the target pixel.

For the filtering process, a line memory is used which can store data for the number of pixels which is three times as large as the number of pixels forming the reading line by the image sensor. That is, this line memory can store data for three lines. Three lines of data including the line including the pixel of interest and each line before and after the line of interest are written in this line memory. Then, the data of the pixel of interest is processed based on each data of the pixels in the matrix of 3 × 3 centered on the pixel of interest.
That is, a certain calculation is performed on the data of the pixel of interest and the data of the pixel having a predetermined positional relationship with the pixel of interest, and the data of the pixel of interest is subjected to processing such as emphasis processing based on the calculation result. To be done.

The emphasis process is a process of increasing or decreasing the data so that white and black appear clearly in the binary image. Therefore, in the above filter processing, for example, the emphasis processing is not performed on the image portion determined to be the halftone image.

[0005]

In the above filter processing, a line memory for three lines is used to generate a matrix of 3 × 3 pixels centering on the pixel of interest. Further, in addition to the above-described filter processing, when processing is performed based on the correlation between adjacent lines, a line memory of a plurality of lines is required. In this case, if it is necessary to create a matrix of N × N pixels, for example, a memory for N lines is generally used.

However, from the viewpoint of effective use of the storage area of the memory element provided in the facsimile apparatus or the like, it is desirable to reduce the capacity of the line memory required for the filtering process. Furthermore, if the capacity of the line memory can be reduced and a memory element with a small storage capacity can be used, the cost can be reduced. Therefore, it is an essential subject to reduce the capacity of the line memory required for the filtering process.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above technical problems and to provide an image data processing apparatus which can realize a process using image data of a plurality of lines by using a line memory having a small capacity.

[0008]

In order to achieve the above object, the image data processing apparatus according to the first aspect of the present invention is an image data processing apparatus in which each scanning line when scanning an image with a plurality of lines along a predetermined direction is formed. Pixel data is sequentially supplied, and processing is performed based on N line data of the current line data to which the pixel corresponding to the supplied data belongs and the (N-1) line data immediately before this current line. In the image data processing device for performing, the storage means capable of storing data of (N-1) lines and the data of each constituent pixel of the (N-1) line immediately before the current line are stored from the storage means. Means for sequentially reading and the read (N-1)
The processing means to which the data of each constituent pixel of the line and the data of the constituent pixel of the current line are given, and the data of the constituent pixel of the line which is (N-1) lines before the current line in the storage means. A means for writing the data of the constituent pixels of the current line is included in the storage position where the reading is completed.

According to another aspect of the image data processing device of the present invention, data of individual pixels constituting each scanning line when scanning an image with a plurality of lines along a predetermined direction are sequentially supplied, and the supplied data is supplied. Based on the data of the current line to which the corresponding pixel belongs, the data of the previous line immediately before this current line, and the data of the previous two lines immediately before this previous line, 3 × with the pixel of interest in the previous line as the center In the image data processing device for processing the data of the pixel of interest based on the data of 9 pixels forming the matrix of 3 pixels, the storage means capable of storing the data of 2 lines and the storage means A means for sequentially reading the data of the respective constituent pixels of the line and the previous-preceding line; And data of the constituent pixels of the pixel of interest, and processing means for performing a predetermined process on the data of the pixel of interest based on predetermined data of the data of nine pixels forming the matrix of 3 × 3 pixels, And a means for writing the data of the constituent pixels of the current line at a storage position in the storage means at which the reading of the data of the constituent pixels of the previous line is completed.

[0010]

According to the above structure, when the data of each of the constituent pixels of (N-1) lines immediately before the current line is read from the storage means, (N-1) lines of the current line are read. The data of the constituent pixels of the current line is written at the read end position of the data of the constituent pixels of the previous line. That is,
When processing data using N line data consisting of the current line and the (N-1) line immediately preceding it, the data of the constituent pixels of the line preceding the current line by (N-1) lines is the data. Once read from the storage means for processing, it is no longer necessary. The new data of the current line is written in the storage position of the unnecessary data.

Thus, it is sufficient to prepare a storage means capable of storing (N-1) lines of data when performing data processing based on N lines of data. Therefore, for example, when processing is performed on a target pixel by performing an operation based on the data of a predetermined pixel among the 9 pixels forming a matrix of 3 × 3 pixels centering on the target pixel, the data for two lines is stored. It suffices to have a storage means that can do it.

[0012]

[Embodiment] In the following, taking a facsimile machine as an example,
An embodiment of the present invention will be described in detail. Figure 1
FIG. 1 is a block diagram showing an electrical configuration of a facsimile machine incorporating an embodiment of the present invention.

In this facsimile machine, an input image processing circuit (FIP (Fax Image sensor Processor) unit) 11 is provided.
An image output processing circuit (PRT section) 12, a CPU 14 that controls the entire apparatus, and an input image processing circuit 1.
1 and an image output processing circuit 12 and a CPU interface 13 necessary for connecting the CPU 14 to each other.
The input image processing circuit 11 and the image output processing circuit 12 operate asynchronously. In addition, the CPU interface 13
Is a DMA (Direct Memory Access) in this embodiment.
It has a built-in function.

When the original is set on the facsimile and is read, the input image processing circuit 11 supplies the driving clock CCLK and the horizontal synchronizing signal SI to the image sensor 15. The image sensor 15 optically reads the original image based on the supplied drive clock CCLK and the horizontal synchronizing signal SI, and the read analog image data is given to the analog section 16.

The analog section 16 includes an input image processing circuit 1
1, the automatic gain adjustment signal AGC, the sample hold signal SHOLD, and the gain setting signal DSCH are given, and the analog image data given from the image sensor 15 is converted into a sample hold signal subjected to a predetermined amplification process, and the A / D It is given to converter 17. The A / D converter 17 is operated by the conversion clock ADCCLK supplied from the input image processing circuit 11, converts the supplied sample hold signal into digital image data, and supplies the digital image data to the input image processing circuit 11.

The input image processing circuit 11 performs various input image processing on the digital image data (read image data) supplied from the A / D converter 17. The input image process is a shading correction process for the read image data, a binarization correction process, an error diffusion process necessary for expressing a halftone, and the like. In input image processing,
Since it is necessary to perform two-dimensional image processing based on a plurality of line data, a memory is required to store at least two lines of image data and other various parameters required for image processing. Therefore, the input image processing circuit 11 is connected to a memory 18, which is a storage unit composed of, for example, a 32 KB SRAM (static random access memory). A certain area of the memory 18 is used as a line memory, and predetermined data for shading correction calculation and error diffusion data are stored in a certain area of the memory 18.

The input image processing circuit 11 supplies a read strobe signal / ROE0 or a write strobe signal / RWE0 to the memory 18, and designates an address to write the line data in the designated address area and also to write the line data. Read out. Further, the input image processing of the read image data is performed using the line data read from the memory 18.

The access speed at which the input image processing circuit 11 writes data into or reads data from the memory 18 is, for example, a memory access clock S of 20 MHz.
It is done in synchronization with YSCLK, and 16 clocks
Data of one pixel is processed as a cycle. The reading speed of the image sensor 15, that is, the drive clock CCL applied to the image sensor 15
K is, for example, a frequency of about 400 KHz (the reason why such a frequency is set is that the operation speed of the image sensor 15 is limited), and the memory access synchronization clock SYSCLK is sufficiently faster than that. It is said that.

The read image data after the input image processing is temporarily stored in the DRAM (dynamic random access memory) 19 as it is. Data transfer from the input image processing circuit 11 to the DRAM 19 is performed by the CPU.
Since the interface 13 has a built-in DMA function, DMA transfer is performed. The DMA transfer is performed when the read image data is given from the input image processing circuit 11 to the CPU interface 13 and the data reaches a predetermined amount. That is, when the data reaches a predetermined amount, C
The PU interface 13 makes a DMA request to the CPU 14, and upon receiving the DMA approval from the CPU 14, transfers the read image data to the DRAM 19.

The read image data once stored in the DRAM 19 is read out by the CPU 14, compressed, and stored again in the DRAM 19. There are various methods for this compression processing depending on the standard of the facsimile apparatus, and for example, the methods such as MRR, MR, MH are known. The read image data compressed and stored in the DRAM 19 is read by the CPU 14 and given to the modem 20, converted from digital data to analog data by the modem 20, and transferred to a telephone line via an NCU (Network Control Unit) 21. It is output and transmitted to the facsimile machine on the other end of the transmission.

On the other hand, when data is transmitted through the telephone line, it is received by the NCU 21, the received data (analog data) is converted into digital data by the modem 20, and stored in the DRAM 19. This data is compressed data. The compressed data stored in the DRAM 19 is read out by the CPU 14 and subjected to decompression processing.
It is restored to AM19.

After that, the CPU 14 gives the image data restored in the DRAM 19 to the image output processing circuit 12. When the image output processing circuit 12 receives image data from the CPU 14 via the CPU interface 13,
Output processing is performed on the image data, the LSU (laser scanning unit) 22 is driven, and the image data subjected to the output processing is recorded on a sheet or the like.

The output processing performed by the image output processing circuit 12 is, for example, smoothing processing for smoothing the unevenness of the contour of image data, conversion of pixel density or line density when enlarging or reducing an image. Processing, pixel density conversion processing and the like due to the difference between the density of given image data and the resolution of the LSU 22. In these output processes, for example, the smoothing pattern for the pixel of interest is changed according to the state of surrounding pixels for the pixel of interest in the image data, or the pixel density is converted by taking the logical sum of the data of a plurality of lines. A memory is needed to hold the data. Also, the image output processing circuit 12
When outputting a video signal as image data from the LSU 22 to the LSU 22, since there is a difference between the output processing speed and the LSU 22 processing speed, the video signal is temporarily stored in the line memory as a buffer, and then the buffer line memory is used. It is necessary to read the video signal and output it to the LSU 22. Therefore, a line memory is required. Therefore, the memory 18 is also utilized in the output process.

The memory 18 is accessed by the image output processing circuit 12 in synchronization with the memory access clock SYSCLK, like the input image processing circuit 11, and is accessed via the input image processing circuit 11. Therefore, the image output processing circuit 12 supplies the input image processing circuit 11 with the memory request signal MREQ and the write strobe signal / P.
RTWE or a read strobe signal / PRTOE is given, an address is designated, and data is written to or read from the address designated area.

Although the input image processing circuit 11 and the image output processing circuit 12 operate asynchronously as described above, a common memory access synchronization clock SYS is used for both circuits.
CLK is given. Therefore, while the input image processing circuit 11 and the image output processing circuit 12 operate asynchronously, the memory 18 is accessed in synchronization with the memory access synchronization clock SYSCLK.

When the memory access request signal MREQ is not output from the image output processing circuit 12, the input image processing circuit 11 has the access right to the memory 18.
Further, in one cycle of the operation of the input image processing circuit 11, the memory access synchronization clock SYSCLK is set to 16 clocks, and 8 of the 16 clocks are used.
The clock completes the memory access within one cycle. Therefore, in the internal state of the input image processing circuit 11, the memory access operation is performed based on 8 clocks of the 16 clocks of the memory access synchronization clock SYSCLK for each cycle, and the remaining 8
The operation is stopped (waiting state) during the clock period.

One cycle of the operation of the input image processing circuit 11 is performed by the memory access synchronization clock SYSC as described above.
As described above, the LK16 clock can be used as a unit because the read image data from the image sensor 15 supplied to the input image processing circuit 11 has a relatively low frequency, for example, a drive clock CCLK of about 400 kHz.
This is because the memory access synchronization clock SYSCLK is relatively high, for example, a clock of 20 MHz, while it is input in pixel units in synchronization with. That is,
If one cycle of the operation of the input image processing circuit 11 is defined in units of the period in which the read image data of one pixel is given to the input image processing circuit 11, the memory access synchronization clock SYSCLK is 16 clocks.

As a result, even when the input image processing circuit 11 has the access right to the memory 18, the memory access synchronization clock SYSCLK is obtained in each cycle.
It is in a stopped state for 8 clocks. On the other hand, the image output processing circuit 12 that operates asynchronously with the input image processing circuit 11 gives a memory access request signal MREQ to the input image processing circuit 11 and the memory access signal switching circuit 110 at an arbitrary timing. When the request signal MREQ is given, the memory access right is transferred to the image output processing circuit 12 side as described above.

Further, the input image processing circuit 11 stops the circuit operation in response to the memory access request signal MREQ, and grants the access right of the memory 18 to the image output processing circuit 12.
Hand over to. Therefore, the image output processing circuit 12 uses the memory 1
8 accesses can be made. Image output processing circuit 1
One memory access period of 2 is predetermined. For example, a memory access synchronization clock SYSC
The period is LK8 clocks.

When the image output processing circuit 12 completes one access to the memory 18, the memory access request signal MREQ is not output from the image output processing circuit 12. Therefore, the memory access signal switching circuit 110 switches to the input image processing circuit 11 side, and the input image processing circuit 1
1 again gains access to the memory 18. In this case, the memory access of the input image processing circuit 11 is performed every memory cycle by the memory access synchronization clock SYSC.
Since the LK8 clock period is sufficient, if the memory access synchronization clock SYSCLK8 clock period is compensated as the memory access period for each cycle, the memory access by the input image processing circuit 11 can be performed without any trouble.

That is, even if the memory access request signal MREQ from the image output processing circuit 12 interrupts at an arbitrary timing, the circuit operation may be stopped while the request signal MREQ is interrupted.
Even if the request signal MREQ is not interrupted, an operation stop period is inevitably present in each operation cycle.
Since the stop period may be any timing, the input image processing circuit 11 can access the memory without any trouble.

Further, the memory access by the image output processing circuit 12 can also be performed for each operation cycle at an arbitrary timing. FIG. 2 is a block diagram showing the internal configuration of the input image processing circuit 11. Input image processing circuit 11
Is an image sensor 15, an analog section 16 and an A / D
An image sensor interface 25 for outputting a signal for driving the converter 17 and the like is provided.
Further, a RAM interface 26 is provided for exchanging data with the memory 18. A 15-bit address bus RA and an 8-bit data bus RD are connected to the RAM interface 26. R
From the AM interface 26 to the memory 18,
Read strobe signal / ROE0 and write strobe signal / RWE0 are applied. On the other hand, the image output processing circuit 12 outputs the address signal PRTADR and the data PR.
TDOUT, a write strobe signal PRTWE, a read strobe signal PRTOE, and the like are given, and a memory request signal MREQ is further input. Further, the above-mentioned memory access clock signal SYSCLK is also given.

The 7-bit image data ID from the A / D converter 17 is given to the shading correction section 31, and the variation of the density between pixels due to the variation of the luminance of the reading light source is corrected. The shading correction is performed based on the black reference data BST corresponding to a pure black image and the white reference data WST corresponding to a pure white image. These black reference data BST and white reference data WST are generated by the white / black reference value generation unit 32, and R
It is written in the memory 18 via the AM interface 26. The black reference data BST is created by acquiring the output of the image sensor 15 with the lamp for illuminating the original being turned off. Further, the white reference data WST is created by turning on the lamp for illuminating the original and causing the image sensor 15 to read the white reference plate on which the white reference image is formed.

The white / black reference value generator 32 offsets the difference between the maximum output data of the A / D converter 17 and the white reference data WST when the white reference data WST is generated.
Calculated as FSET. This offset OFFSET
Is written in the memory 18 and used for shading correction (details will be described later). That is, white /
The black reference value generation unit 32 functions as an offset calculation means, and automatically generates the offset OFFSET at the same time when the white reference data WST is generated. The generation of such an offset OFFSET does not necessarily have to be automatically performed, and the white reference data WST and the maximum output data of the A / D converter 17 are generated in response to a predetermined operation from the operation unit of the facsimile apparatus. Offset OFF based on
SET may be calculated.

Data SOUT after shading correction
Is input to the filter processing unit 33. In the filter processing unit 33, the image areas of the halftone image area and the binary image area are separately detected, and the edge portion of the image is emphasized with respect to the image of the binary image area. . The data FOUT after the filter processing is given to the density adjustment processing unit 34. The density adjustment processing unit 34 performs processing for enhancing the density reproducibility of a halftone image. Specifically, 4x4
An image portion including 16 pixels forming a matrix of pixels is sequentially extracted, and a predetermined density correction value corresponding to the pixel position in the matrix is added to the pixel data at each pixel position.

Output signal WOUT of the density adjustment processing section 34
Is given to the γ correction unit 35 and the simple binarization processing unit 26. That is, the data of the halftone image is obtained by the γ correction unit
And the image data of the binary image is given to the simple binarization unit 36.
Given to. In the γ correction unit 35, the image sensor 15
The γ characteristic of the image data and the development characteristic when the electrostatic latent image formed on the photoconductor by the scanning of the laser beam is developed into a toner image, and the correction for accurately reproducing the density of the original image is corrected by the image data. Is applied to.

The γ-corrected data GOUT is given to the error diffusion processing section 37. The error diffusion processing is a pseudo intermediate processing method, and the error between the read density and the binarized density of the reference pixel in the vicinity of the target pixel is weighted and distributed according to the positional relationship with the target pixel, Is a technique for performing the binarization process for (1) based on the result of adding the density of the pixel of interest and the binarization error distributed from the reference pixels in the vicinity. The binarization process is performed based on a certain threshold.

The data WOUT given from the density adjustment processing unit 34 to the simple binarization processing unit 36 is binarized into "0" or "1" by a predetermined threshold value. A threshold for binarization is input to the simple binarization processing unit 36 from the automatic density adjustment processing unit 38. Automatic density adjustment processing unit 38
Is to take the average value of the peak densities of a plurality of lines and change the threshold value for binarization based on this average value. Therefore, for example, different thresholds are set for each part of one document.

The binary data from the simple binarization processing unit 36 is input to the isolated point removal processing unit 39. The isolated point removal processing prevents deterioration of image quality due to, for example, uneven rotation of a motor for conveying a document, and white pixels or black pixels are independently formed due to noise such as dirt on the document surface. This is a process for removing the so-called isolated pixel when it exists. This isolated point removal processing forces the binary data of the target pixel to be forced to the binary data when a pixel at a predetermined position around the target pixel has binary data of either a white pixel or a black pixel. It can be done by converting to data.

By such processing, it is possible to prevent the black pixel or the white pixel from being isolated, so that the image quality can be improved.
Not only that, the compression efficiency at the time of performing the compression encoding of the binary data for the facsimile transmission is increased, so that the transmission code amount is reduced. Therefore, high-speed communication becomes possible. The binary data from the error diffusion processing unit 37 and the isolated point removal processing unit 39 is given to the binarization output circuit 40, and the binary data serially given for each pixel is 8-bit parallel data BI.
It is converted into N0 to BIN7 and output. This binary data is given to the CPU interface 13 of FIG.

In the input image processing circuit 11, in addition to the above-mentioned components, an address counter 41 for generating a write or read address for the memory 18, a timing control circuit 42 for controlling the operation timing of each unit, and the like. It is equipped. FIG. 3 is a block diagram showing the internal configuration of the shading correction unit 31. Shading correction unit 31
Are given white reference data WST, black reference data BST, and image data ID. Then, the white reference data W
The difference (ST-BST) between ST and the black reference data BST is calculated by the first subtractor 45, and the difference (ID-BST) between the image data ID and the black reference data BST is calculated by the second subtractor 4.
6 is calculated. Further, the outputs of the subtracters 45 and 46 (W
ST-BST) and (ID-BST) are given to the first and second adders 47 and 48, respectively, and the offset OFFSET is added to each.

Output of adder 47 (WST-BST + OF
FSET) and the output of the adder 48 (ID-BST + OF
FSET) is given to the division circuit 49. In the division circuit 49, the division shown by the following equation (1) is performed and the shading correction data SOUT is output.

[0043]

[Equation 1]

In the calculation of the equation (1), the white reference data WST and the offset OFFSET are added and the image data ID and the offset OFFSET are added first, and the black reference data BST is obtained from each addition result. It can also be realized by subtracting each and performing a division operation on each subtraction result. The white reference data WST and the black reference data BST are generated by the white / black reference value generation unit 32 (see FIG. 2) and stored in the memory 18. This memory 1
The reference data WST and BST in 8 are read out and given to the subtracters 45 and 46.

On the other hand, the offset OFFSET is calculated at the same time when the white / black reference value generator 32 generates the white reference data WST, as described above, and the offset OFFSET is stored in the memory 1.
8 is stored in the adder 47,
48. This offset OFFSET is calculated by the following equation (2). OFFSET = (maximum output of A / D converter) −WST (2) That is, the difference between the maximum output data of the A / D converter 17 and the white reference value WST is the offset OFFSET.
By adding such offset OFFSET to the divisor data (WST-BST) and the dividend data (ID-BST) of the division operation for shading correction, a wide dynamic range of the shading correction data SOUT is secured.

That is, for example, the A / D converter 17
When the output data of 7 has a depth of 7 bits and the white reference value WST is data of "1111" or less, (ID-BST) / (WST-BST) is substantially 4 The data is expressed in bits or less. Therefore, the dynamic range of the shading correction data SOUT may be narrowed.

On the other hand, in this embodiment, the offset OFFSET is added to the divisor data and the dividend data of the calculation for shading correction.
The number of effective bits increases, and a wide dynamic range is secured. As a result, the corrected data SOU
T is data representing the density in multiple gradations. It should be noted that the offset OFFSET may use a predetermined constant value instead of the value calculated by the above equation (2).

An example of the configuration of the division circuit 49 is shown in FIG. That is, when the operation of A ÷ B is performed, the divisor data B is given to one input terminal of the subtractor 50, and the dividend data A is given to the input terminal Ia of the selector 51.
The output of the selector 51 is given to the other input terminal of the subtractor 50. The subtractor 50 subtracts the divisor data B from the output data of the selector 51, and if subtraction is possible (the subtraction result is a negative value). If the subtraction is impossible, a signal of logic "0" is derived on line 52. This signal is input to the 7-bit shift register 53.

The output of the data selector 51 is the line 54
Is shifted by one bit to the upper side and fed back to the input terminal Ic of the selector 51. Further, the data of the subtraction result in the subtractor 50 is shifted from the line 55 to the upper side by 1 bit and fed back to the input terminal Ic of the data selector 51. A selection control signal for selecting the dividend data A given to the input terminal Ia is given to the data selector 51 from the line 56. Furthermore, the subtractor 5
The signals derived from 0 to the line 52 are input terminals Ib, I
It is given from the line 57 as a selection control signal for selecting any one of the input signals of c. The data selector 51 selects the input data from the input terminal Ib when the signal of logic "1" is given from the line 57, and the input data from the input terminal Ic if the signal from the line 57 is logic "0". Select.

With this configuration, the dividend data A from the input terminal Ia is initially supplied to the subtractor 50. At this time, if A−B <0, a signal of logic “0” is derived on the line 52. Then, the data obtained by shifting the dividend data A from the input terminal Ic to the upper side by 1 bit is selected and input to the subtractor 50. At this time, if the divisor data B can be subtracted from the data shifted by 1 bit, a signal of logic "1" is derived on the line 52, and the data from the input terminal Ib obtained by shifting the subtraction result to the upper side by 1 bit is obtained. It is selected by the data selector 51.

Such an operation is repeated 7 times if the dividend data A and the divisor data B are 7 bits, for example. As a result, the shift register 53 stores 7-bit data obtained by dividing the dividend data A by the divisor data B. This 7-bit data is output as division data. FIG. 5 is a diagram for explaining the processing in the filter processing unit 33. In this embodiment, a so-called Laplacian filter is used. The filtering process is performed based on the data after the shading correction of the pixels arranged in a matrix of 3 × 3 centered on the target pixel.

Data for three lines is required to form a matrix of 3 × 3 pixels. That is, the data B of the current line that is shading-corrected and sequentially output
_{n, B n-1, B} n-2, ····, data X _n of the previous line including the target _{pixel, X n-1, X n} -2, the data A _n of ... and before the previous line , A _n-1 , A _n-2 , ... Are required. In the filtering process, the difference value S shown in the following expression (3) is calculated.

[0053]

[Equation 2]

Then, according to the calculated difference value S, the data FOU after the filter processing shown in Table 1 below is performed.
T is obtained. However, it is assumed that the data of each pixel is 8-bit data and can have a value in the range of 0 to 255.

[0055]

[Table 1]

In Table 1, X corresponds to the image data X _n-1 in FIG. 5, SLB is a threshold value for black pixel emphasis processing, and SWB is a threshold value for white pixel emphasis processing. . By the above-described processing, the halftone area and the binary image area are separately detected, and the processing for emphasizing white and black is performed on the binary image area. This improves the reproducibility of the binary image.

In this embodiment, a line memory for two lines is provided in the storage area of the memory 18 for the filtering process. This is done by the memory 18 shown in FIG.
The memory map will be described. Addresses "0000" to "1AFF" of the memory 18 are used to store the data SOUT after shading correction for two lines, the black reference data BST, and the white reference data WST. One line is composed of, for example, 1728 pixels. In addition, addresses "1B00" to "1FFF"
Is used as a work area and has the address "2000"
"26BF" is used for error diffusion processing and simple binarization processing. Furthermore, addresses "26C0" to "26FF"
Is used for storing a correction table for γ correction, and addresses “2700” to “7FFF” are stored in the CPU 14
Used as a work area.

In the filter processing, the address "0000"
~ "1AFF" is used as a line memory for two lines. That is, the data after shading correction corresponding to the first pixel in the main scanning direction in the image reading of the image sensor has the addresses “0000” and “0”.
001 ”is written. The data of one of two adjacent lines is stored in the address “0000”, and the data of the other line is stored in the address “0001”. Similarly, the data of the second pixel is stored in the addresses “0004” and “0005”, and the data of the third pixel is stored in the addresses “0008” and “0009”. In this way, the data of each pixel for two lines can be stored.

For example, the addresses "0000", "00"
04 ”,“ 0008 ”,“ 000C ”, ... The data of the line before last is written to the address“ 000 ”.
1 ”,“ 0005 ”,“ 0009 ”,“ 000D ”, ...
-It is assumed that the data of the previous line is written in.
For example, when the data of the previous line written at the address "0008" is read out as the data A _n-2 of FIG. 5 and used for the filtering process, the data of the current line B _{n-at the} address "0008". ₂ is written. Similarly, when the use of the data of the line before the end is completed in the filtering process, the data of the present line is written to the storage address of the pixel data instead of the data of the pixel for which the use is completed.

In this way, the filter processing that needs to handle the image data for three lines can be achieved by preparing the line memory for two lines. From this, memory 1
It is possible to effectively utilize the eight storage areas. On the contrary, since an element having a small storage capacity can be used as the memory 18, the cost can be reduced. In addition,
Image data for two lines may be used for the filtering process, or image data for four lines or more may be used. If the filtering process is performed based on the data for N (N ≧ 2) lines, the memory 18 stores (N−
1) A line memory for lines is prepared, and data of each constituent pixel for (N-1) lines immediately before the current line is sequentially read from the memory, and data before (N-1) lines before the current line. It is sufficient to write the data of the current line to the read address. As a result, the filter processing that requires data for N lines can be achieved by preparing a memory for (N-1) lines.

FIG. 7 is a diagram for explaining the processing in the density adjustment processing section 34. The density adjustment processing unit 34 is 4 ×
A partial image composed of 16 pixels arranged in a matrix of 4 pixels is taken out in order, and a predetermined density is obtained for the pixels W0, W1, W2, ..., W7 at predetermined pixel positions in this matrix. The correction value is adjusted. For example, the density correction values added to the pixels W0, W1, ..., W7 are WD0, WD1, ..., WD7, respectively, and WD0 = WD1 = WD2 = ... WD7 = 3.・ ・ (4) At this time, if the image data FOUT after the filter processing for the pixels arranged in a matrix of 4 × 4 pixels is as shown in FIG. 8A, this data is
It will be changed to the data WOUT of (b).

The density correction value WDi (0≤i
The addition of ≦ 7) may be performed under predetermined conditions. For example, assuming that FOUT> 0 ... (5) is a condition for addition, the image data FOUT after the filter processing as shown in FIG. 9A is converted into the data WOUT as shown in FIG. 9B. To be done. That is, the density correction value WDi is not added to the pixel of FOUT = 0.

Further, different conditions are set for each pixel position in the matrix, and when the data FOUT satisfies the condition at each pixel position, the density correction value WDi associated with the pixel position is added. Good. For example, as shown in FIG. 10, pixels W0 and W in the matrix are
The following condition C1 is set for 3, W4 and W7, and the following condition C2 is set for the pixels W1, W2, W5 and W6.

Condition C1 ... FOUT> WMIN = 0 ... (6) Condition C2 ... FOUT> WMAX = 8 ... (7) Conditions C1 and C2 set for each pixel position Assuming that the density correction value WDi corresponding to the pixel position is added to the pixel satisfying the above condition, the image data FOUT after the filtering process as shown in FIG. 11 (a) is as shown in FIG. 11 (b). Converted to data WOUT. That is, in this case, only the condition C1 is satisfied.

The density correction values WDi need not be all equal, and different density correction values may be set for each pixel at each position. FIG. 12 is a block diagram showing a configuration example for performing the above-mentioned density adjustment processing. Density correction value WD0
The WD 7 is stored in the memory 18 in advance. The density correction values WD0 to WD7 are stored in the data bus 59 by the CPU 14.
Be derived to. Then, the density correction values WD0, WD1, ..., WD7 are written in the registers 60, 61 ,.

On the other hand, threshold data WMI for conditioning
N and WMAX are written to the registers 68 and 69 via the data bus 59, respectively. With this configuration, the pixels W0, W1, W in the 4 × 4 pixel matrix are
2, ..., W7 (see FIG. 7) image data,
Density correction values WD0, WD1, WD2, ..., W
D7 is added.

When the addition is performed conditionally, the data of the pixels W0, W1, W2, ..., W7 to be added are compared with the output data of the registers 68 and 69, and the comparison result is determined. It may be determined whether or not the addition is performed. FIG.
FIG. 9 is a block diagram showing another configuration example for the density adjustment processing. With this configuration, the density correction values WD0, WD1, ...
., WD7 is input to the multiplexer 70,
Any one of the density correction values WDi is derived from the output terminals Q0 to Q6 as density correction data WDATA.

A selection control signal for selecting which of the density correction values WDi to be output is given to the multiplexer 70 from the line decoder 71. The line decoder 71 has eight output terminals Y0 to Y7, and any one of them corresponds to the density correction value WDi to be selected.
Derives low-level signals to two output terminals. When no addition is performed, all output terminals Y0 to Y7 are at high level.

In this configuration example, a predetermined 4-bit address is given to each pixel position of the 4 × 4 pixel matrix, and the signal of the lower 3 bits of this address is input to the input terminals A, B, and C. It has been entered. The most significant bit of the address is given to the input terminal G1 via the AND gate 72. The AND gate 72 also has a signal OUTFI for selecting whether to perform density adjustment.
L has been entered.

When a low level signal is applied to the input terminal G1, the line decoder 71 derives a high level signal to all the output terminals Y0 to Y7. Therefore, the most significant bit of the address is "0" or the signal OU
When TFIL is at low level, the output data of the multiplexer 70 is "0". That is, at this time, the density correction value WDi is not added.

FIG. 14 is a diagram showing a 4-bit address given to each pixel of a 4 × 4 pixel matrix. That is, the pixel W of FIG. 7 to which the density correction value WDi should be added
0, W1, ..., For W7, the most significant bit is "1"
For the remaining pixels, the most significant bit is “0”. Therefore, the density correction value WDi is added only to the pixels W0, W1, ..., W7. Then, by the lower 3 bits of the address, each pixel W
The density correction values WD0 to WD7 corresponding to 0 to W7 are selected and output as the density correction data WDATA.

FIG. 15 is a diagram for explaining the processing in the γ correction section 35. The contents of the γ correction table (see FIG. 6) stored in the memory 18 are as shown in Table 2 below.
FIG. 15 shows a γ curve which is a graph of this γ correction table. In addition, "H" represents that the number before it is a hexadecimal number.

[0073]

[Table 2]

When the γ correction is performed, the data WOUT from the density adjustment processing section 34 is assigned to the lower two digits of the address of the γ correction table. Then, the value stored at that address is read from the memory 18 as the γ-corrected data GOUT, whereby the γ-correction is achieved. For example, by performing γ correction on the data WOUT after the density adjustment processing of the 4 × 4 pixel matrix of FIG. 8B, the γ-corrected data GOUT of FIG. 8C is obtained. Similarly, when γ correction is performed on the data WOUT after the density adjustment processing of FIGS. 9B and 11B, the image data GOUT of FIGS. 8C and 11C, respectively.
Is obtained.

FIG. 8 (c), FIG. 9 (c) and FIG.
8 (d) and 8 (d) for each data GOUT in (c)
And halftone processing using the dither matrix shown in FIG. 11 (d) respectively, results in FIG. 8 (e) and FIG. 9 (e), respectively.
And the binary image shown in FIG. 11 (e) is obtained. The shaded areas are black pixels. These Figure 8 (e),
In the binary images of FIG. 9 (e) and FIG. 11 (e), since white pixels and black pixels are mixed in an appropriate ratio, there is a problem that, for example, white pixels are crushed by surrounding black pixels. I can overcome it. This is particularly effective when black pixels are spread due to the spread of toner particles when an image is printed by a laser beam printer, for example.

As described above, it is the result of the density adjustment processing in the density adjustment processing unit 34 that an appropriate ratio of white pixels and black pixels is obtained in the image after the halftone processing. If the adjustment in the section 34 is omitted, the density reproduction of the halftone image may be poor. More specifically, the density data of each pixel forming the partial image of FIG. 8A is an intermediate value "6". Therefore, even if γ correction is directly applied to each density data of this partial image, all pixels are only converted to the same value. Therefore, there is substantially no difference from the case where only the halftone processing by the dither matrix is performed, and there is a possibility that the intermediate density is not reproduced well.

On the other hand, if the density adjustment processing in this embodiment is performed, it is possible to cause variations in the density data as shown in FIG. 8 (b). Therefore, so to speak, 4 × 4
Since the γ correction for expressing the intermediate density is performed for each partial image forming the matrix of pixels, the intermediate density can be reproduced well. In this case, if the density correction value WDi is added under the condition of the above expression (5) as in the processing shown in FIG. 9, the density data of the pixel which is a black pixel is obviously intermediate. It can be prevented from being corrected to the typical density data. As a result, the density reproducibility is further improved.

Further, as in the processing shown in FIG.
If the density adjustment processing is performed by setting different conditions for each pixel position, the density reproduction adjustment range is widened, and the density can be reproduced more favorably. FIG. 16 shows the density adjustment process and γ
It is a figure for explaining other processing techniques for amendment processing. In this example, each pixel position WP0, WP1, WP2, ..., WP of a 4 × 4 pixel matrix for density adjustment
Γ correction tables GT0, GT for each of 15
, GT3, ..., GT15 (in FIG. 16, only GT0 to GT8 are shown to avoid complexity). Then, for the 4 × 4 pixel filtered image data FOUT that is the target of the density adjustment processing, a different γ correction table is referred to depending on the position of each pixel in the matrix.

In the example of FIG. 16, the addresses of the γ correction table are in the upper two digits in the pixel positions WP0, WP1, WP2, ...
.., "00H" to "0FH" corresponding to WP15 are assigned, and the data after filtering is assigned to the following two digits. Therefore, for example, the pixel position W
The image data FOUT after the filter process of P8 is “06
If "H", data "05H" at address "0806H"
Is obtained as the data GOUT after γ correction.

The relationship between the γ correction tables GT0 to GT15 is, for example, the density correction values WD1 to WD7 for the pixels W0 to W7 in the matrix of 4 × 4 pixels in FIG.
Are added, the density adjustment is performed so that the addition processing is not performed on the remaining pixels in the matrix, and the result of the γ correction on the data after the density adjustment is obtained.

With such a configuration, the above-described density adjustment processing and γ correction processing can be performed at once. FIG. 17 is a diagram for explaining the processing in the error diffusion processing unit 37. In the error diffusion processing, when a certain pixel P0 is binarized, an error HG between the multivalued density data of this pixel P0 and the binarized density data (density data corresponding to white or black) is obtained, This is a process of distributing this error to pixels around the pixel P0 at a predetermined distribution ratio. For example, the multi-value density data to be binarized for the pixel P0 is “30H” and the binarization threshold is “20H”.
Then, the pixel P0 becomes a white pixel. At this time, assuming that the density of a pure white pixel is “3F”, the binarization error HG is HG = 3FH−30H = FH (8)

In the present embodiment, the binarization error HG generated in the pixel P0 is adjacent to the pixel P0 on the downstream side in each of the main scanning direction RM and the sub scanning direction RS when the image is read by the image sensor 15. The pixels P1 and P5 are distributed by being multiplied by a coefficient ¼. In addition, a pixel P2 adjacent to the pixel P1 on the downstream side in the main scanning direction RM, and a pixel P
5, two pixels P3 on the upstream side in the main scanning direction RM
P4 and a pixel P6 adjacent to the pixel P5 on the downstream side in the main scanning direction are multiplied by a factor of 1/8 and distributed.

In the error diffusion processing for the target pixel, the error distributed from the peripheral pixels is added to the density data of the target pixel, and the binarization processing is performed on the addition result. This process will be described with reference to FIG. Considering the pixel of interest A as a center, the pixel of interest A has binarization errors HG (G), HG in the pixels G, E, D of the previous line L1.
(E) and HG (D) are distributed by being multiplied by the coefficient 1/8. In addition, the binarization error HG (F) at the pixel F has a coefficient of 1 /
It is distributed by multiplying by 4. Current line L2 including pixel of interest A
With respect to, the binarization error HG (B) in the pixel B adjacent to the upstream side in the main scanning direction RS is distributed by being multiplied by a coefficient ¼, and further, to the pixel B, the upstream side in the main scanning direction RS. The binarization error HG (C) at the pixel C located at
It is distributed by multiplying by 8.

Therefore, assuming that the data given from the γ correction unit 35 to the target pixel A is GOUT (A), the binarization process for the target pixel A is performed by the value T shown by the following equation (9). It is performed by comparing (A) with a predetermined threshold value.

[0085]

[Equation 3]

The specific processing procedure of such an error diffusion processing is as follows. The error diffusion process performed in this embodiment is composed of the following [Process 1] to [Process 6]. [Processing 1] The binarization error HG (B) generated in the process one pixel before the pixel of interest A and the binarization error HG (C) two pixels before are associated with the positional relationship with the pixel of interest A. A coefficient is multiplied and added, and the cumulative error value RG (h) shown by the following formula (10) is calculated.

[0087]

[Equation 4]

[Processing 2] The cumulative error value RG (m) in the previous line L1 shown in the following equation (11) and the cumulative error value RG (h) obtained in [Processing 1] are added to each other. The cumulative error value RG (i) to be added to the data of the pixel of interest A is calculated by the equation (12) below. The accumulated error value RG (m) is stored in the memory 18 by [Process 6] described later, which has already been completed for the pixel of the previous line L1. This accumulated error value RG (m) is stored in the memory 18 (FIG. 6).
reference. ).

[0089]

[Equation 5]

[Processing 3] Data GOUT (A) after γ correction of the target pixel A and accumulated error value R obtained in [Processing 2]
(I) is added to the value T (A) to be a binarization determination target
Ask for. This value T (A) becomes the value of the following expression (13). T (A) = GOUT (A) + RG (i) (13) [Process 4] The binarization determination target value T (A) is compared with the binarization threshold value to perform binarization. Binarization error HG (A) at judgment
Ask for. Since the data corresponding to the pure white density and the data corresponding to the pure black density are known in advance, if the judgment target value T (A) is compared with the binarization threshold, the binarization error HG for the target pixel A is obtained. (A) can be obtained.

[Processing 5] The value obtained by multiplying the obtained binarization error HG (A) of the target pixel A by the error diffusion coefficient ⅛ is set to 1
The cumulative error value RG (j) obtained in the above [Process 1] in the error diffusion process in which the pixel B before the pixel is the target pixel is added, and the added value is set as the cumulative error value RG (k). The cumulative error value RG (j) is expressed by the following equation (14) using the binarization error HG (X) generated in the error diffusion processing for the pixel X immediately before the pixel C.

[0092]

[Equation 6]

Therefore, the cumulative error value RG (k) is expressed by the following expression (15).

[0094]

[Equation 7]

[Process 6] Cumulative error value RG (j)
, The binarization error HG in the pixel B immediately before the target pixel A
A value obtained by multiplying (B) by the error diffusion coefficient ⅛ is added to obtain a cumulative error value RG (n) represented by the following expression (16).

[0096]

[Equation 8]

This accumulated error value RG (n) is written to the address corresponding to the target pixel A in the memory 18 in order to use it for the processing for the pixel Y of the next line. The written value is used in the above [Processing 2] when the pixel Y becomes the target pixel. By performing such [Processing 1] to [Processing 6] every time the target pixel is switched, the error diffusion process is achieved, and thereby the pseudo halftone process is performed.

As described above, in the error diffusion processing of this embodiment, the cumulative error value RG (n) is stored in the memory 18 in association with the target pixel A, and the cumulative error value RG is stored.
(N) is used in the error diffusion process for the pixel Y having a predetermined positional relationship with the pixel A in the next line. Therefore, in order to perform the error diffusion process on the pixel Y, if the binarization errors for the pixels G, F, E, and D are not individually read from the memory, but the cumulative error value RG (n) is read, Line L2, which is the previous line for Y
The reading of the data relating to the pixel is completed. Therefore,
Since the number of accesses to the memory 18 is small, the error diffusion process can be performed at high speed.

FIG. 19 is a block diagram showing a concrete hardware configuration for commonly implementing the above shading correction, filter processing, density adjustment processing, γ correction processing and error diffusion processing. Since the γ correction and the error diffusion process are performed only on the halftone image, the configuration of FIG. 19 can be said to be a configuration for data processing on the halftone image. A /
The 7-bit image data ID from the D converter 17 (see FIG. 1) is given from the line 80 to each input terminal A of the first adder 81 and the second adder 82. The data from the memory 18 is also input from the line 83 to the input terminal A of the adders 81 and 82,
Further, the data from the memory 18 which is once held in the register 91 is also given. The data read from the memory 18 is also held in the read register 84, and the contents of the read register 84 can be given to the input terminal A of the adders 81 and 82.

The output of the first adder 81 is the register 9
It is fed back to the input terminal A through 0, 92, 93 and is fed back to the input terminal B as it is. Further, the output of the first adder 81 is also given to the division circuit 86 from the line 85. The output of the division circuit 86 is given to the input terminal B of the first adder 81.
The output of the first addition adder 81 is also given to the address generation unit 87 for generating an address in the memory 18.

On the other hand, the output of the second adder 82 is input to the binarization determination circuit 88 for binarization determination in the error diffusion processing via the register 94. The binary data output from the binarization determination circuit 88 is input to the binarization output circuit 40 (see FIG. 2) via the register 99. Further, the binarization determination circuit 88 derives a binarization error that occurs during binarization on the line 89, and this error is given to the input terminal A of the adder 82 via the registers 97 and 98. The binarization error also occurs in the register 97 and the line 100.
Can also be input to the input terminal A of the adder 82.

The output of the second adder 82 is also fed back to the input terminal B as it is. Further, this output is fed back to the input terminal B via the registers 95 and 96. Furthermore, the output of the second adder 82 is the binarization determination circuit 88.
Is also given to. 20 and 21 are timing charts for explaining the operation. First, the shading correction process, the filter process, and the density adjustment process will be described with reference to FIG. In FIG. 20, (a)
Indicates a clock signal CLK that defines the processing operation, (b)
Indicates an image ID input from the A / D converter 17 for each pixel, (c) indicates processing contents, (d) indicates read data from the memory 18, and (e) indicates writing to the memory 18. 7F shows the embedded data, (f) shows the generated value of the address counter 41 (see FIG. 2) inside the address generation circuit 87, and (g) shows the contents held in the read register 84. Furthermore, (h) represents dividend data in the division circuit 86, (i) represents divisor data, and (j) represents division data. Further, (k) represents data taken in from the input terminal A of the first adder 81, (l) represents data taken in from the input terminal B, and (m) represents its output data. Furthermore, (n), (o), (p) and (q) represent the contents held in the registers 90, 91, 92 and 93, respectively.

First, the operation relating to the memory 18 will be described with reference to Table 3 below.

[0104]

[Table 3]

The processing for each pixel is completed in 8 cycles from the first cycle to the eighth cycle. In the first cycle (WST), the white reference data WST is read from the memory 18.
Is read and the value of the address counter 41 is decremented by -2 from the current value. Second cycle (A)
Then, the data after the shading correction is read from the memory 18, and the value of the address counter 41 is not changed. The data after the shading correction that is read in the second cycle (A) is the data of the pre-previous line indicated by adding the initial letter A in FIG.

In the third cycle (B), data after shading correction is written, and the address counter 41
The value of is decremented by -1. The data written at this time is the data of the current line indicated by the initial letter B in FIG. In the fourth cycle (X), the data after the shading correction is read as in the second cycle (A), and the value of the address counter 41 does not change. The data read in the fourth cycle (X) is the data of the previous line indicated by adding the initial letter X in FIG.

In the fifth cycle (RGn), the accumulated error value RGn of the above equation (16) generated in the error diffusion processing is generated.
Are written in the memory 18. At this time, the value of the address counter 41 is incremented by +3. In the sixth cycle (RGm), the accumulated error value RGm of the above equation (11) obtained in the error diffusion processing of the previous line is read from the memory 18, and the value of the address counter 41 is not changed.

In the seventh cycle (BST), the black reference data BST is read. At this time, the value of the address counter 41 remains unchanged. In the eighth cycle (GOUT), the γ-corrected data GOUT generated from the γ-correction table (see FIG. 6) is read, and the value of the address counter 41 is incremented by +1.

The image data ID is given in order from the image data ID1 of the first pixel to ID1, ID2, ... FIG. 20 shows the image data I of the eighth pixel.
From D8 is represented. Image ID 8 of the 8th pixel
In the first cycle (WST), the black reference data WS stored in the memory 18 corresponding to the ninth pixel designated by the address counter 41
T9 is read. The read data is held in the register 91 at the rising edge of the clock signal CLK.

The instruction value of the address counter 41 is decremented by -2 to "7", and the second cycle (A)
Then, the data A7 after the shading correction of the seventh pixel in the line before the previous line is read. This data A7 is held in the read register 84, and further the first adder 81
Is applied to one input terminal A. To the other input terminal B of the adder 81, the data SOUT7 after shading correction corresponding to the eighth pixel of the current line output from the division circuit 86 is given as the data B7. As a result, the sum (A7 + B7) of the data A7 on the previous line and the data B7 on the current line for the seventh pixel is the adder 8
1 to the output terminal.

In the second cycle (A), the instruction value of the address counter 41 is kept at "7", and in the third cycle (B), the shading-corrected data SOUT7 and the data A7 corresponding to the seventh pixel are stored. It is stored in the position where it was. That is, the data after the shading correction of the current line is written to the storage address from which the data after the shading correction of the previous line is read.

The above (A7 +) in the first adder 81
The calculation of B7) is performed in the third cycle (B). This calculation corresponds to the addition of the pixel data A _n and B _n in the above filter processing. The bit calculation formula of the addition operation in the third cycle (B) is shown in FIG. That is, 7-bit data A and 7-bit data B are added to obtain 8-bit data (A + B). In the figure, A (0), A (1), ..., B (0), B
(1), ..., A + B (0), A + B (1), ... Represents “0” or “1” data for each bit.

Now, the third for the image data ID8
The added value (A7 + B7) obtained in the cycle (B) is stored in the data register 90 and given to the input terminal B of the adder 81 in the fourth cycle (X). In the fourth cycle (X), the data register 93
The data (A5 + B5) held in the above is taken into the input terminal A of the first adder 81. That is, in the fourth cycle (X), the data (A7 +) corresponding to the seventh pixel
B7) is held in the data register 90, data (A6 + B6) corresponding to the sixth pixel is held in the data register 92, and data (A5 + B5) corresponding to the fifth pixel is held in the data register 93. Has been done. Therefore, if the data A7 and B7 correspond to the data A _n and B _n in FIG. 5, the data A5 and B5 correspond to the data A _n-2 and B _n-2 , respectively.

4AV of the following expression (17), which is the addition result of the first adder 81, is led to the output terminal. 4AV = (A7 + B7) + (A5 + B5) (17) The bit calculation formula of this addition operation is shown in FIG. 23, and 8-bit data (A + B) corresponding to data (A7 + B7) and data The data (A + B) 'corresponding to (A5 + B6) is added, and the 9-bit addition result 4AV
Is obtained. The 9-bit data 4AV corresponds to four times the average value AV of the data A7, B7, A5, B5 of the four pixels that are the addition targets.

Since the value of the address counter 41 is decremented by -1 in the third cycle (B), the data X6 after the shading correction of the sixth pixel is read from the eye 18 in the fourth cycle (X). This data X6 is
When the data A7 and B7 correspond to the data A _n and B _n in FIG. 5, they correspond to the data X _n-1 . The data X6 read from the memory 18 is read from the read register 84 to the input terminal A of the first adder 81 in the fifth cycle (RGn).
Given to. At this time, by the bit operation described later,
The data 2X6 which is twice the data X6 is supplied to the input terminal A. Further, a value 2AV obtained by dividing 4AV which is the output of the adder 81 in the fourth cycle (X) by 2 by a bit operation described later is input to the input terminal B.
The 2AV input at this time is inverted and input, and therefore the adder 81 performs the operation of the following expression (18).

[0116]

[Equation 9]

By comparing this equation (18) with the above equation (3), the value of the above equation (18) is nothing but the difference S corresponding to the sixth pixel of the previous line. Be understood. The bit calculation formula in the fifth cycle (RGn) is
As shown in FIG. 23. That is, the data 4AV calculated in the fourth cycle (X) is inverted (shown with an overline in FIG. 23),
Further, it is shifted to the lower side by one bit, and data-2AV is created. Then, the least significant bit AV (0) of the data 4AV is added to the lower order of the data X corresponding to the data X6, and thereby the data 2X which is twice the data X is created. And data 2X and data-2
The addition with AV is performed, and the difference S of 9 bits is obtained by the calculation shown in the equation (18).

The above-mentioned data 4AV and data X
Bit manipulation on the random number (R1
+ R2-1) occurs. The difference S thus calculated is added by the adder 8 in the next sixth cycle (RGm).
1 is applied to the input terminal B, and (X6 + S) is calculated. Then, according to the difference value S and the value of the addition result (X6 + S), the data is selected so as to conform to the data processing method shown in Table 1 above, and the selected data is the eighth cycle (in the BST, the filter is used). Data FO after processing
It is written in the data register 90 as UT6.

The bit calculation in the sixth cycle (RGm) is performed by adding the lower 7 bits of the data S created in the fifth cycle and the 7-bit data X, as shown in FIG. Is done. As a result, 8-bit data XS is obtained. Data FO after filtering
The UT6 also adds the adder 8 in the eighth cycle (BST).
1 is also applied to the input terminal B. At this time, the adder 81
The filtered data FOUT
The density correction data WD corresponding to the 6 pixel positions is given.

Therefore, the output of the adder 81 becomes the data WOUT6 of the following formula (19) which has been subjected to the density adjustment processing shown in FIG. WOUT6 = FOUT6 + WD (19) Based on this data WOUT6, γ correction described later is performed, and γ-corrected data GOUT is obtained.

The addition operation of the equation (19) for density adjustment is performed in the seventh cycle (BST), and the γ correction is performed in the eighth cycle (GOUT). The bit calculation formulas in the seventh and eighth cycles are as shown in FIG.
In the eighth cycle (BST), since the value of the address counter 41 is “9”, the black reference data BST9 stored in combination with the ninth pixel is read from the memory 18. The offset OFFSET is inverted and given to the input terminal B of the adder 81 from a register not shown in FIG. Then, BST'9 = BST9-OFFSET (20) is calculated.

Adder 8 in the eighth cycle (BST)
The bit calculation formula for 1 is shown in FIG. That is, 7-bit offset OFFSET is subtracted from 7-bit data BST corresponding to black reference data BST9 to obtain 8-bit data BS corresponding to data BST'9.
T'is obtained. This calculated value BST'9 is shown in FIG.
As shown in 0, the image data ID of the 9th pixel
9 is applied to the input terminal B of the adder 81 in the first cycle (WST) and the data register 90
Held in. In the first cycle (WST), the white reference data WST9 held in the data register 91.
Is applied to the input terminal A of the adder 81. Then, in the adder 81, the calculation shown in the following Expression (21) is performed.

WST9-BST'9 (21) The bit calculation in this first cycle (WST) is as shown in FIG. That is, the data W
Data B from 7-bit data WST corresponding to ST9
The 7-bit data BST 'corresponding to ST'9 is subtracted to obtain 8-bit data (WB'). This data (W-B ') is the value (WST9-B) of the equation (21).
This corresponds to ST'9).

In the subsequent second cycle (A), as shown in FIG. 20, the value of the equation (21) is taken into the division circuit 86 as divisor data. Further, the value BST ′ 9 from the data register 90 is given to the input terminal B of the adder 81. On the other hand, the input terminal A receives the image data ID9. Then, the calculation of the following formula (22) is performed.

ID9-BST′9 (22) The bit calculation formula of this operation is as shown in FIG. That is, the 7-bit data ID corresponding to the image data ID9 is subtracted from the 7-bit data BST 'corresponding to the data BST'9 to obtain 8-bit data (IB'). This data (IB ') is
This corresponds to the data (ID9-BST'9) in the equation (22).

In the following third cycle (B), the above-mentioned
As shown in FIG. 20, the value of the equation (22) is taken in by the division circuit 86 as dividend data.
Then, during the period in which seven clocks CLK are input, the division shown by the following equation (23) is performed, and the division result is the data SOUT after the shading correction for the ninth pixel.
9

[0127]

[Equation 10]

It will be apparent from the comparison with the above equation (1) that the value of the equation (23) is the value after shading correction. Now, the data SOUT9 after the shading correction is the image data ID1 of the tenth pixel.
In the third cycle (B) for 0, it is written in the memory 18. The data writing position at this time is the reading position of the data A9 after the shading correction of the previous-before line which was read out immediately before that for the filter processing.

The bit calculation formula of the division operation of the above formula (23) is as shown in FIG. That is, the lower 7 bits of the data (IB ') obtained in the second cycle are taken, and 1 bit is added to the lower side to create a total of 8 bits of data. Then, the lower 7 bits of the data (WB ') calculated in the first cycle are subtracted from the 8-bit data (IB'). As a result of this subtraction, 8-bit data DIV is included in the first to eighth bits.
Is obtained, and the data SOUT (k) of "1" or "0" is obtained in the 9th bit depending on whether or not the subtraction was possible.
(However, 0 ≦ k ≦ 7) is obtained.

Then, when the subtraction is possible, the divisor data (WB ') is subtracted from the data obtained by shifting the subtraction result by 1 bit to the upper side, and when the subtraction is not possible, it becomes the target of the subtraction. The data (IB ') is shifted to the upper side by 1 bit and used again as a target of subtraction. By repeating such an operation seven times and accumulating the data SOUT (k) obtained in each subtraction operation, the 7-bit data SOUT can be obtained. This data SOUT corresponds to the data SOUT9 of the equation (23),
The data will be after shading correction.

Next, the γ correction process and the error diffusion process will be described with reference to the timing chart of FIG. In FIG. 21, the contents of (a) to (g) are shown in FIG.
Same as (g). The second adder 82 is added to (r).
The data given to the input terminal A of is shown, (s)
Shows the data given to its input terminal B, and (t) shows the data of the operation result derived at its output terminal. Furthermore, (u), (v), (w), (x), (y), (z)
Data stored in the registers 94, 95, 96, 97, 98, 99 are shown in FIG.

When the density-adjusted data WOUT7 (see FIG. 20) is output from the adder 81 in the seventh cycle (BST) for the image data ID9 corresponding to the ninth pixel, the address generation unit 87 outputs γ. Generate the address of the correction table. The data WOUT7 after the density adjustment constitutes a part of the address of the γ correction table as described above.

As a result, in the eighth cycle (GOUT), the data GOUT7 after γ correction is read from the memory 18, and γ correction is achieved (see FIG. 23). The data GOUT7 after the γ correction is the data GOUT of the pixel of interest in the error diffusion processing in the first cycle (WST) corresponding to the image data ID10 of the tenth pixel.
(X7) is input from the read register 84 to the input terminal A of the second adder 82. At this time, the adder 82
The accumulated error RG is applied to the input terminal B of the output terminal from the output terminal.

This accumulated error RG corresponds to the accumulated error RG (m) shown in the above equation (11). That is, when the pixel corresponding to the data GOUT (X7) is the target pixel A in FIG. 18, the peripheral pixel data G, F, E,
This is a value obtained by adding a value obtained by multiplying each of the D, C, and B generated errors HG by the error diffusion coefficient. The data GOUT (X7) is the image data ID of the current line when the input image data ID is
It corresponds to the 7th pixel in the previous line.

More specifically, the sixth line of the line before the previous line
The data A6 of the pixel, the data A7 of the seventh pixel, the data A8 of the eighth pixel and the data A9 of the ninth pixel, and the data X5 of the fifth pixel and the data X6 of the sixth pixel in the previous line Binarization error H
The value obtained by multiplying G by the error diffusion coefficient and adding is the cumulative error RG input in the first cycle (WST). RAND
Is a random number. The random number RAND will be described later.

As a result, in the first cycle (WST) and the second cycle (A), the data T (X7) shown in the following expression (24) is derived from the output terminal of the adder 82. T (X7) = GOUT (X7) + RG (24) In this way, the above [Process 3] in the error diffusion process is performed. That is, the above data T (X7)
Corresponds to T (A) in the equation (13) that is the target of the binarization determination.

The bit calculation formula of this addition operation is shown in FIG. That is, in the first cycle (WST) and the second cycle (A), 6-bit data GO
The UT and 7-bit data RG are added to obtain 8-bit data T. In the third cycle (B), the above-mentioned data T (X7) is given to the binarization determination circuit 88 and binarization determination processing is performed, and the binarized data BIN (X
7) is held in the register 99. On the other hand, in the binarization determination circuit 88, as shown in FIG. 25, based on the comparison between the binarization threshold and the data T (X7), the data T (X
Binarization error data HG (X7) for 7) is generated.

The generated binarization error data HG (X
7) is applied to the input terminal A of the adder 82, as shown in FIG. At this time, the input terminal B is supplied with the data RG (X4 + X5) held in the register 96. This data RG (X4 + X5) corresponds to a value obtained by multiplying the binarization error generated in the pixels X and C in FIG. 18 by the error diffusion coefficient and adding the pixel when the pixel corresponding to the data X7 is the pixel A in FIG. To do.

That is, if the binarization errors in the pixels corresponding to the data X4 and X5 are H (X4) and H (X5), respectively,

[0140]

[Equation 11]

It is represented by Then, the binarization error HG (X
7) is multiplied by the error diffusion coefficient ⅛ to obtain the above cumulative error R
Value obtained by adding G (X4 + X5) RG (X4 + X5 + X
7) is led to the output terminal. The bit calculation formula in the third cycle (B) is shown in FIG. That is, the 8-bit binarization error HG (X7) generated in the second cycle (A) is shifted to the lower side by 3 bits to be ⅛ times, and then the 8-bit accumulated error is generated. It is multiplied by a certain RG (X4 + X5). As a result,
The accumulated error RG (X4 + X5 + X7) shown in the equation (26) is obtained. In this way, the above [Process 5] is performed.

[0142]

[Equation 12]

Calculated cumulative error RG (X4 + X5 + X
7) next, in the fourth cycle (X), the adder 82
Is applied to the input terminal B of. At this time, the input terminal A is
The binarization error HG (X6) at the sixth pixel on the previous line is given from the register 98. In the fourth cycle (X) and the fifth cycle (RGn), as shown in the bit calculation formula in FIG. 26, the binarization error HG (X6) is shifted to the lower side by 3 bits and is multiplied by 1/8. And the cumulative error RG (X4 + X5 + X7) is added. As a result, the accumulated error R shown in the following equation (27)
G (X4 to X7) is obtained. As a result, the above [Process 6] in the error diffusion process is performed.

[0144]

[Equation 13]

This calculated cumulative error RG (X4 to X
7) is written in the register 94 and the memory 18, and is used when the error diffusion processing is performed on the pixels of the current line. 6th cycle (RG
In m), the binarization error HG (X7) corresponding to the data X7 held in the register 97 is given to the input terminal A of the adder 82. Then, the binarization error HG (X6) corresponding to the data X6 held in the register 98 is given to the input terminal B. Then, by the bit calculation shown in FIG. 25, the accumulated error RG (X6
+ X7) is calculated. Thereby, the above [Process 1]
Will be done.

[0146]

[Equation 14]

The obtained cumulative error RG (X6 + X7) is
As shown in FIG. 21, the next 7th cycle (BS
In T), it is given to the input terminal B of the adder 82. At this time, at the input terminal A, the line corresponding to the image data ID currently input is taken as the current line, and the accumulated error RG (A7 ~ A10) is given. This accumulated error RG (A7 to A10) is equal to the sixth cycle (RG
m), the data is read from the memory 18 as the data RGm, and given from the read register 84 to the input terminal A of the adder 82 in the seventh cycle (BST).

The accumulated error RG (A7 to A10) is data corresponding to the data X8 to be subjected to the error diffusion processing next. That is, the data X8 of the eighth pixel on the previous line is
If it corresponds to the pixel A in FIG. 18, the pixels G, F, E,
The cumulative value of the binarization error in the data A7 to A10 of the 7th pixel to the 10th pixel of the previous-before line corresponding to D is the cumulative error RG (A7 to A10). Specifically, data A
The binarization errors corresponding to 7 to A10 are HG (A
7), HG (A8), HG (A9), HG (A10), the cumulative error (A7 to A10) becomes the value of the following formula (29).

[0149]

[Equation 15]

Therefore, in the seventh cycle (BST), the cumulative error RG (A7 to A10 + X6 + X7) of the following Expression (30) is calculated at the output terminal of the adder 82, and the above-mentioned [Process 2] is performed. It will be. RG (A7 to A10 + X6 + X7) = RG (A7 to A10) + RG (X6 + X7) ... (30) The bit calculation formula of this operation is as shown in FIG. The accumulated error RG (X6 + X7) of 8 bits, which is the calculation result in (RGm), and the memory 18
7-bit accumulated error RGm (= RG
(A7 to A10)) are added as they are.

The addition result in the seventh cycle (BST) is
In the eighth cycle (GOUT), it is supplied to the input terminal B of the adder 82 again. At this time, the random number RAND is input to the input terminal A, and as a result, the cumulative error RG (A7 to A10 + X6 + X7 + RAND) is derived at the output terminal. The addition of the random number RAND has the following significance. That is, if the density data in an image portion having a relatively large area is constant at a certain specific value corresponding to an intermediate density, the error diffusion process may significantly deteriorate the processed image. Known to be. Such image deterioration can be eliminated by adding random numbers as described above.

The cumulative error RG (A
7-A10 + X6 + X7 + RAND) is a register 94
And to the input terminal B of the adder 82 in the first cycle (WST) corresponding to the image data ID11 of the 11th pixel that follows. After this,
The error diffusion processing similar to that performed on the data X7 in the input period of the image data ID9 corresponding to the ninth pixel is performed on the data X8 of the eighth pixel on the previous line.

As described above, with the configuration of FIG.
Mainly adder 81, division circuit 86 and register 9
The shading correction, the filter processing, and the density adjustment processing are achieved by the 0, 92, 93, the address generation circuit 87, and the like, and the gamma correction and the error diffusion processing are mainly performed by the adder 82, the binarization determination circuit 88, the registers 95 to 98, and the like. Is achieved.

Next, the isolated point removal processing performed by the isolated point removal processing unit 39 (see FIG. 2) on the binary image will be described. 27, 28, and 29 are diagrams for explaining the isolated point removal processing. The isolated point removal process is performed by adding “*” to the binary image processed by the simple binarization processing unit 36.
When the value of the pixel of interest indicated by is different from any of the values of pixels at predetermined surrounding positions surrounding the pixel of interest, the value of the pixel of interest is converted into the value of the surrounding pixels.

Specifically, as shown in FIG. 27A, if the pixel of interest is a white pixel and the eight pixels around it are black pixels, the pixel of interest is an isolated white pixel. For this reason,
The isolated white pixel is converted into a black pixel. Figure 27 (b)
Conversely, the target pixel is an isolated black pixel, and the target pixel is converted to a white pixel at this time. Also, FIG.
8 and 29 show the case where a pixel having a value different from that of the target pixel surrounds the target pixel in a U-shape, and the value of the target pixel is also converted in this case. Specifically, as shown in FIG.
In the case of (b) and FIGS. 29 (a) and (b), the value of the pixel of interest is converted into a black pixel, and in the cases of FIGS. 28 (c) and (d) and FIGS. , The value of the pixel of interest is converted to a white pixel.

By such isolated point removal processing, a good binary image can be reproduced by removing the noise component remaining in the binary image and the influence of the jitter caused by the uneven transportation of the document. Not only that, the data compression efficiency can be improved by removing the isolated points. This reduces the transmission code generated by the encoding processing such as MH, MR, and MRR, so that the time required for facsimile communication can be reduced.

FIG. 30 is a block diagram showing a configuration related to the isolated point removal processing unit 39. The line memory 110 configured by a partial storage area (see FIG. 6) of the memory 18.
Has a storage capacity capable of storing each binary data of pixels for two lines. This line memory 110
Is connected to a control circuit 111, and m-bit (8-bit in this embodiment) address signals AD1 to ADm are applied from the control circuit 111. Control circuit 11
In addition, the write enable signal WE and the output enable signal OE are
It is given to the line memory 110. In the drawings, an overline attached to a symbol indicating a signal indicates that the signal is a signal of negative logic, and the description of the overline is omitted in the specification.

The control circuit 111 is connected to an image processing unit 112 including components that are in charge of each process from shading correction before isolated point removal processing to simple binarization processing. The image processing unit 112 serially outputs the binarized binary data BID for each pixel bit by bit. This binary data BID is given to the serial input terminal SI of the n-bit (2-bit in this embodiment) shift register SRz. The shift register SRz takes in the binary data BID bit by bit based on the clock signal CK3 supplied from the control circuit 111. Parallel output terminal PO1 of shift register SRz
~ P On is the line memory 110 via the line 113.
Of the input terminals DI1 to DIn.

On the other hand, the output terminal DO of the line memory 110
1 to DOn are connected to the parallel input terminals PI1 to PIn of the n-bit shift registers SRx and SRy. Each of the shift registers SRx and SRy is provided with a control signal input terminal S / P to which a trigger signal for latching n-bit data from the line memory 110 in parallel is input. Signals LO1 and LO2 are provided. At the falling edges of the control signals LO1 and LO2, the input terminal P
The data from I1 to PIn is latched.

A clock signal CK for data shift is supplied from the control circuit 111 to the shift registers SRx and SRy.
1 and CK2 are input respectively. Clock signal C
When K1 is given, the data is shifted bit by bit in the shift register SRx and the serial output terminal SO
To output data bit by bit. The same applies to the shift register SRy.

The serial output signals of the shift registers SRx, SRy and SRz are the 3-bit shift register 12 respectively.
1, 122 and 123 are applied to the respective serial input terminals SI and are taken in based on the clock signals CK1, CK2 and CK3, respectively. Shift registers 121, 1
The 3-bit data respectively taken in by 22 and 123 are converted into parallel output terminals PO _{n + 1} , PO _{n + 2} ,
From PO _{n + 3} to the input terminal A of the binarization redetermination circuit 115,
B, C, ..., I. The binarization re-determination circuit 15 sets the pixel corresponding to the data given to the input terminal E as the pixel of interest, and the above-described FIG. 27, FIG. 28, and FIG.
The isolated point removal processing shown in is performed, and the processed data E ′
Is output.

A mode register 116 is connected to the binarization redetermination circuit 115. This mode register 11
Reference numeral 6 denotes k-bit (2 bits in this embodiment) data MO1 to MOk for selecting a mode of isolated point removal processing.
Is given from the CPU 14 (see FIG. 1). In this embodiment, three types of modes can be selected, the value of the pixel of interest is converted when the condition of FIG. 27 is satisfied in the first mode, and the condition of FIG. 27 or 28 is satisfied in the second mode. Sometimes the value of the pixel of interest is converted, and in the third mode, as shown in FIG.
7, the value of the pixel of interest is converted when the condition of FIG. 28 or 29 is satisfied.

FIG. 31 is a diagram for explaining the relationship of the data input to the binarization redetermination circuit 115. From the shift register 123, data ID1z, for three pixels of the current line, which has just been processed by the image processing unit 112,
ID2z and ID3z are output. Further, the shift register 122 stores the data of the previous line in the shift register SRy.
Data ID1y, ID2 for the three pixels
y, ID3y is output. Furthermore, the shift register 1
The data of the line before two is given to 21 from the shift register SRx, and the data ID1x and ID2 for the three pixels are given.
x, ID3x is output.

As a result, the binarization redetermination circuit 115
As shown in FIG. 31, binary data of each pixel forming a 3 × 3 pixel matrix is input in parallel. At this time, the data ID2x given to the input terminal E is treated as the data of the pixel of interest, and the processing is performed. Since the processing is performed in the order of reading by the image sensor 15 (see FIG. 1), the pixels corresponding to the data previously input to the shift registers 121, 123, and 124 are closer to the head position of each line.

FIG. 32 is a timing chart for explaining the operation. (a) shows the cycle number, and (b) shows the binary data B of the current line input to the shift register SRz.
ID, (c) shows address signals AD1 to ADm, (d) shows a low-active write enable signal WE,
(e) shows a low active output enable signal, (f) shows data derived from the output terminals DO1 to DOn of the line memory 110, and (g) shows the line memories from the input terminals DI1 to DIn of the line memory 110. The data written in 110 is shown. Further, (h) and (j) are control signals LO supplied to the shift registers SRx and SRy, respectively.
1 and LO2, and parallel writing of data to the shift registers SRx and SRy is performed at the falling edge of this signal. Also, (i), (k), (l) are clock signals CK1, CK
2 and CK3, and (m) to (v) represent data input to the binarization redetermination circuit 115, respectively.

In the period from the second cycle to the (n-1) th cycle, the shift register SRz stores binary data ID1z, ID2z, ID3 of each pixel forming the current line.
z, ..., ID (n-1) z are sequentially input. When the data IDnz is input to the shift register SRz in the nth cycle, the output enable signal O is output at time t1.
E becomes low level. At this time, addresses AD1 to A
The value of Dm is the n-bit data ID1y to I of the previous line.
It has a value (IDny) corresponding to Dny, and therefore n-bit data of data ID1y to IDny is derived to the output terminals DO1 to DOn. This data is stored in the shift register SR in synchronization with the fall of the control signal LO2.
Latched in parallel with y.

When the output permission signal OE rises at time t2, the addresses AD1 to ADm are switched to the values (IDnx) corresponding to the n-bit data ID1x to IDnx of the line before the previous line. At time t3 after the address is switched, the output enable signal OE becomes low level again. As a result, the n-bit data ID1x to IDnx of the previous line are derived from the output terminals DO1 to DOn. This data is written in the shift register SRy in synchronization with the fall of the control signal LO1.

When the output permission signal rises at time t4,
This time, the write enable signal E falls at time t5 while keeping the address unchanged. As a result, the shift register S
N-bit data ID of the current line held in Rz
1z to IDnz are the data IDs 1x to ID of the line before the last
The nx is stored at the stored address (IDnx). That is, when the data of the previous line is read for the isolated point removal processing, the data of the current line is written at the read position. As a result, the isolated point removal process, which is a process for pixels on three lines, can be realized by the line memory 110 having a capacity of two lines.

On the other hand, the head data ID1y of the data written in the shift register SRy is shifted by the clock signal CK2 applied at time t6.
No. 2 is written in the first stage. Similarly, the leading data ID1x, ID1z of the data written in the shift registers SRx, SRz are written in the first stage of the shift registers 121, 123 by the clock signals CK1, CK3 given at time t7. .

After that, clock signals CK1, CK2,
CK3 allows shift registers 121, 122, 123
The data is shifted within the range, and as a result, during the period from time t8, the input terminals A to
The data of 9 pixels forming the matrix of FIG. 31 is input to I in parallel. Then, the data ID'2y as the determination result of the binarization re-determination circuit 115 is output from the output terminal E '.

FIG. 33 is a timing chart for explaining the final stage operation of the isolated point removal processing for one line of pixels. Signals (a) to (v) in the figure are shown in Fig. 32.
Is the same as. In this example, it is assumed that one line is composed of 99 pixels, and n = 2 and m = 8 are set to simplify the description. Image processing unit 1
12 is the binary data ID99z of the last pixel of the current line
Immediately after outputting, the data of the next line is not output and dummy data dummy is output. This dummy data
The dummy is data corresponding to, for example, white pixels.

The dummy data dummy is output when the number of pixels constituting one line is different from an integral multiple of the number of pixels read / written in one access to the line memory 110. That is, the binary data ID of the last pixel in one line
After 99x is written in the shift register SRx, the data not written in the line memory 110 in the shift register SRx is n pixels (2 pixels in the example of FIG. 33).
The image processing unit 112 outputs dummy data dummy until it is stored (for pixels).

By the way, when a continuous address is alternately assigned to each line in the line memory 110 capable of storing data for two lines, a problem occurs. That is, for example, if the data of the previous line is an odd address ...
It is stored in "95", "97", "99", ...
The data of the line before the last is an even address ... "96",
It is assumed that the information is stored as "98", ....
At this time, by generating consecutive addresses, the data of the previous line and the data of the previous-two lines can be read alternately.

On the other hand, the writing of the data of the current line to the line memory 110 is performed for the read end address of the line before the previous line as described above. That is, in the above case,
.., "96", "98", ... Are written in the current line data. As a result, when the data of the next line is given from the image processing unit 112, the data of the line before the next line is stored in the even addresses, ..., “96”, “98” ,. The data on the line before the previous one is an odd address ... "95", "9"
7 ”,“ 99 ”, ... That is, the correspondence between the even and odd addresses and the data differs for each processing of one line.

Therefore, in this embodiment, the generated address is made different for each line. That is, continuous addresses are generated as shown in FIG. 33 (c) for a certain line, and FIG. 34 (c) for the next line.
An address as shown in is generated. That is, the even-numbered address and the odd-numbered address are exchanged so that the write address is always the address in which the data of the previous line is stored.

The structure provided in the control circuit 111 for generating such an address is shown in FIG. That is, the address counter 12 that generates a continuous 8-bit address based on the clock signal CKIN
The output of the output terminal Q1 corresponding to the least significant bit of 5 passes through the exclusive OR gate 126 and addresses AD1 to AD8.
Is the least significant bit AD1. Exclusive OR gate 12
6, a signal ROW which toggles between “0” and “1” for each line is given from the image processing unit 112. If the signal ROW is "0", the signal at the output terminal Q1 becomes the least significant bit AD1 of the address as it is, and the signal RO
If W is "1", the signal at the output terminal Q1 is inverted and becomes the least significant bit AD1. As a result, for each line, as shown in FIG.
The continuous addresses shown in (c) and the discontinuous addresses shown in FIG. 34 (c) are generated alternately.

FIG. 36 is a diagram showing the internal structure of the binarization redetermination circuit 115. The binarization re-determination circuit 115 includes a logical operation unit 140 configured by a logical circuit mainly composed of AND gates. Binary data of 3 × 3 matrix-arranged pixels are input from the input terminals A, B, C, ... In addition, 2-bit mode selection data M from the mode register 116
O1 and MO2 are OR gate 141 and AND gate 1
42 and line 146.

The logic operation section 140 is divided into ten logic circuit sections 130, 132, ...
have. Each of the logic circuit units 130 to 139 has input terminals A to I and OR gates 141 and AN, respectively.
When the output signal of the D gate 142 is in the state shown in FIG. 36, a signal of logic “1” is output to the line 143. That is, for example, in the logic circuit unit 130, the input signals from the input terminal E and the OR gate 141 are logic “1”.
When the remaining input signal is a logic "0" at line 1
A signal of logic "1" is derived at 43a.

The signal derived on line 143 is applied to one input terminal of exclusive OR gate 145 via OR gate 144. This exclusive OR gate 145
The signal from the input terminal E is applied to the other input terminal of the output of the exclusive OR gate 145, and the output of the exclusive OR gate 145 is output to the output terminal E ′ as the data of the pixel of interest that has undergone the binarization re-determination process. It That is, if the output of the OR gate 144 is logic "1", the input data of the input terminal E, which is the binary data of the pixel of interest, is inverted, and if the output of the OR gate 144 is logic "0", the input data of the input terminal E is unchanged. It is the data after the binarization re-determination process.

Assuming that the white pixel has a logic "1" and the black pixel has a logic "0", the logic circuit section can be clearly understood by comparing FIGS. 27, 28 and 29 with FIG. There is the following correspondence between 130 to 139 and the respective drawings of FIGS. 27, 28 and 29. 27. (a) Logic circuit section 131 .. FIG. 27 (b) Logic circuit section 132 ..... FIG. 28 (a) Logic circuit section 133 .. b) Logic circuit section 134 ... FIG. 28 (c) Logic circuit section 135 ..... FIG. 28 (d) Logic circuit section 136 .... FIG. 29 (a) Logic circuit section 137. 29 (b) Logic circuit portion 138 ... 29 (c) Logic circuit portion 139 .. FIG. 29 (d) On the other hand, the above-mentioned first mode, second mode and third mode and mode selection data MO1 , MO2 is as follows.

First Mode ・ ・ ・ MO1 = 1, MO2 = 0 Second Mode ・ ・ ・ MO1 = 0, MO2 = 1 Second Mode ・ ・ ・ MO1 = 1, MO2 = 1 Therefore, the first mode Then, since only the output signal of the OR gate 141 has the logic "1", only the logic circuit units 130 and 131 are valid. Therefore, as shown in FIG.
Regarding the image of (b), the binary data given to the input terminal E is inverted.

In the second mode, the OR gate 141
Since the output signal of 1 and the signal from the line 146 are logic "1", the logic circuit units 130 to 135 are enabled. Therefore, FIGS. 27 (a), (b) and FIGS. 28 (a), (b), (c), (d)
The binary data given to the input terminal E is inverted for the image. Further, in the third mode, the OR gate 14
The output signal of 1, the output signal of the AND gate 142, and the signal from the line 146 are all logic "1". Therefore, all the logic circuit units 130 to 139 become effective,
The data from the input terminal E is inverted for all the images shown in FIGS. 27, 28 and 29.

In this way, the binarization redetermination process in each mode is achieved. Since all the patterns in which isolated pixels are generated are covered by the patterns shown in FIGS. 27, 28, and 29, the isolated pixel existing in the binary image is caused by any of the causes. However, it will be surely removed. As a result, the compression efficiency at the time of compression-encoding the binary image is improved, so that the transmission code amount can be reduced. As a result, the communication can be speeded up and the occupation time of the communication line can be shortened.

Which of the first, second and third modes is selected may be determined in consideration of the balance between the quality of the image quality and the high or low of the transmission speed. On the other hand, as described above, a part of the storage area of the memory 18 is used as the line memory 110 for the isolated point removal processing. Therefore, the processing can be performed without preparing an expensive and complicated structure such as a shift register or a FIFO memory capable of storing binary data for one line, which contributes to cost reduction.

The access to the line memory 110 is performed in units of a plurality of pixels using an n-bit shift register. For this reason, the number of accesses to the line memory 110 is small, and high-speed processing is possible. Moreover, since the binary data is read / written in units of a plurality of pixels, it is possible to share a common storage area with a filter process or an error diffusion process for processing multi-value density data composed of a plurality of bits. (See FIG. 6).

FIG. 37 is a block diagram showing another configuration example of the isolated point removal processing unit 39. In FIG. 37, parts corresponding to the respective parts shown in FIG. 30 are designated by the same reference numerals. In this configuration example, the shift register SR
A line memory 110 that can store 2n-bit data, which is twice the capacity of x, SRy, and SRz, as one word, and can store binary data for two lines as a whole.
A is formed in a part of the storage area of the memory 18 (see FIG. 1).

Out of the 2n-bit input terminals DI1 to DI2n of the line memory 110A, the lower-order n-bit terminals DI1 to DIn are supplied with the n-bit data of the current line held in the shift register SRz. Also,
The n-bit data of the previous line held in the shift register SRz is given to the terminals DIn + 1 to DI2n for the upper n bits.

On the other hand, of the 2n-bit output terminals DO1 to DO2n of the line memory 110A, the data derived to the lower n-bit terminals DO01 to DOn are applied to the shift register SRx corresponding to the line before the previous line. Further, the data led to the terminals DIn + 1 to DI2n for the upper n bits are given to the shift register SRy corresponding to the previous line.

A control signal LO1 and a clock signal CK1 from the control circuit 111A are commonly applied to the shift registers SRx and SRy. With this configuration, the n-bit data of the current line is written in the lower n bits of each word in the line memory 110A. Then, during the period when the data of the next line is given from the image processing unit 112, it is given to the shift register SRy as the data of the previous line for the next line.

The data of the previous line written in the shift register SRy is written as the upper n-bit data of each word of the line memory 110A. And
When the process for the next line is performed, it is given to the shift register SRx as the data of the line before the previous line. FIG. 38 is a timing chart for explaining the operation. The image processing unit 112 sequentially outputs the data of the current line from the first pixel from the second cycle. At this time, the control circuit 111A controls the data IDn of the nth pixel.
During the period until −1 is output and the data IDnz of the nth pixel is further output, the addresses AD1 to ADM are set to the value “0” corresponding to the first pixel.

The output enable signal OE falls at the time t11 when the data for n pixels is accumulated in the shift register SRz, whereby the n-bit data is output to the output terminals DO1 to DOn and the shift register SRy is output. Given. The n-bit data corresponds to the data ID1y to IDny from the first pixel to the n-th pixel on the previous line. Further, n-bit data is also derived from the output terminals DOn + 1 to DO2n and given to the shift register SRx. This n-bit data corresponds to the data ID1x to IDnx from the first pixel to the n-th pixel in the previous line.

When the output permission signal rises at time t12, the write permission signal WE falls instead at time t13, and the data ID1z to IDnz for n pixels of the current line held in the shift register SRz are input terminals. DI
It is written in the line memory 110A from 1 to DIn.
At the same time, data ID1y to IDny for n pixels of the previous line held in the shift register SRy are written in the line memory 110A from the input terminals DIn + 1 to DI2n. At this time, the write address is the data ID1y to IDny, ID1x to
This is the address where IDnx was written. That is, new data is written to the address where the data reading is completed.

After the completion of this writing, the control circuit 111A
Is the address AD during the period from the (n + 1) th cycle.
1 to ADM are switched to the next address "1". Time t
When the clock signal CK1 is supplied to 14, shift operations are performed in the shift registers SRx and SRy, and as a result, the input terminals C, C of the binarization redetermination circuit 115 corresponding to the first stages of the shift registers 121 and 122 are generated. The data ID1x and ID1y of the first pixel on the previous-preceding line and on the preceding line are input to E, respectively.

Further, at time t15, the clock signal CK3
Is given to the shift register SRz, the data ID1z of the first pixel of the current line is held in the first stage of the shift register 123 along with the shift operation, and this data is input to the binarization redetermination circuit 115. Given to terminal I.
After that, the shift operations in the shift registers SRx, SRy, SRz and the shift registers 121, 122, 123 are performed in accordance with the input of the clocks CK1, CK3, and the binarization redetermination process of the data ID2y is performed at time t16. Data of 9 pixels in parallel
Entered in. As a result, the re-determined data ID '
2y is led to the output terminal E '.

As described above, in the present configuration example, when performing isolated point removal processing using the line memory for two lines, the data of adjacent two lines is stored by bit division of each word of the line memory 110A. I have to. Then, the shift registers SRx, SRy, SR are arranged so that the data of the line before the line corresponding to the lower bit of each word data is stored in the upper bit of each word.
z and the line memory 110A are connected.

With this configuration, if continuous addresses are generated for the processing of any line, the data of the previous line and the data of the line before the shift lines SRx and SRy are transferred.
Therefore, unlike the first configuration example shown in FIG. 30, the address given to the line memory does not need to be devised. Therefore, it is not necessary for the image processing unit 112 to provide the control circuit 111A with the signal ROW that toggles each time one line is processed.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. For example, in the above-described embodiment, a facsimile machine is taken as an example, but the present invention has a configuration for processing image data obtained by optically reading an image, such as an image scanner or a copying machine. It can be widely applied. In addition, various design changes can be made without changing the gist of the present invention.

[0198]

As described above, according to the image data processing apparatus of the present invention, the storage means capable of storing (N-1) lines of data in order to perform the processing based on the data of N lines. Is enough. As a result, for example, the storage area of the memory provided in the facsimile machine can be effectively used. On the contrary, since a memory element having a small capacity can be used, it is possible to contribute to cost reduction.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a facsimile apparatus to which an embodiment of the present invention is applied.

FIG. 2 is a block diagram showing an internal configuration of an input image processing circuit of the facsimile device.

FIG. 3 is a block diagram showing a configuration of a shading correction unit.

FIG. 4 is a block diagram showing a configuration example of a division circuit.

FIG. 5 is a diagram for explaining filter processing.

FIG. 6 is a diagram showing a storage area allocation state in a memory.

FIG. 7 is a diagram for explaining density adjustment processing.

FIG. 8 is a diagram for explaining density adjustment processing, γ correction processing, and the like.

FIG. 9 is a diagram for explaining density adjustment processing, γ correction processing, and the like.

FIG. 10 is a diagram for explaining density adjustment processing.

FIG. 11 is a diagram for explaining density adjustment processing, γ correction processing, and the like.

FIG. 12 is a block diagram illustrating a configuration example of a density adjustment processing unit.

FIG. 13 is a block diagram illustrating another configuration example of the density adjustment processing unit.

FIG. 14 is a diagram showing an address assigned to each pixel position of a density adjustment processing target matrix.

FIG. 15 is a diagram for explaining γ correction processing.

FIG. 16 is a diagram for explaining another technique for density adjustment processing and γ correction processing.

FIG. 17 is a diagram for explaining error diffusion processing.

FIG. 18 is a diagram for explaining error diffusion processing.

FIG. 19 is a block diagram showing a hardware configuration for performing processing on a halftone image.

FIG. 20 is a timing chart for explaining operations related to shading correction processing, filter processing, and density adjustment processing.

FIG. 21 is a timing chart for explaining operations related to γ correction processing and error diffusion processing.

FIG. 22 is a diagram for explaining bit calculation related to filter processing.

FIG. 23 is a diagram for explaining bit calculation related to density adjustment processing and γ correction processing.

FIG. 24 is a diagram for explaining bit calculation related to shading correction processing.

FIG. 25 is a diagram for explaining bit calculation related to error diffusion processing.

FIG. 26 is a diagram for explaining bit calculation related to error diffusion processing.

FIG. 27 is a diagram for explaining isolated point removal processing.

FIG. 28 is a diagram for explaining isolated point removal processing.

FIG. 29 is a diagram for explaining isolated point removal processing.

FIG. 30 is a block diagram showing a configuration related to isolated point removal processing.

FIG. 31 is a diagram for explaining a positional relationship of pixels corresponding to data used for isolated point removal processing.

FIG. 32 is a timing chart for explaining the operation.

FIG. 33 is a timing chart for explaining the operation in the final stage of the process for one line.

FIG. 34 is a timing chart for explaining an operation in the final stage of the process for one line.

FIG. 35 is a block diagram showing a configuration for generating an address given to a line memory.

FIG. 36 is a block diagram showing a configuration of a binarization redetermination circuit.

FIG. 37 is a block diagram illustrating another configuration example of the isolated point removal processing unit.

FIG. 38 is a timing chart for explaining the operation.

[Explanation of symbols]

 11 Input Image Processing Circuit 14 CPU 15 Image Sensor 17 A / D Converter 18 Memory 22 LSU 31 Shading Correction Section 32 White / Black Reference Value Generation Section 33 Filter Processing Section 34 Density Adjustment Section 35 γ Correction Section 36 Simple Binarization Processing Section 37 error diffusion processing unit 39 isolated point removal processing unit 45,46 subtractor 47,48 adder 49 division circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Satoshi Iwatsubo 9-2 28, Yada, Sumida, Higashisumiyoshi-ku, Osaka City, Osaka Prefecture Terrace FLORA E

Claims (2)

[Claims] 1. Data of individual pixels constituting each scan line when scanning an image with a plurality of lines along a predetermined direction are sequentially supplied, and data of a current line to which a pixel corresponding to the supplied data belongs. And (N before the current line
-1) In an image data processing device that performs processing based on line data and N line data, storage means capable of storing (N-1) line data and current storage means Means for sequentially reading the data of each of the constituent pixels of the (N-1) line immediately before the line, the data of each of the constituent pixels of the read (N-1) line, and the data of the constituent pixels of the current line And the processing means to which the data of the constituent pixels of the current line are written in the storage position where the reading of the data of the constituent pixels of the line preceding the current line by (N-1) lines is completed. An image data processing device comprising: 2. Data of individual pixels constituting each scan line when scanning an image with a plurality of lines along a predetermined direction are sequentially supplied, and data of a current line to which a pixel corresponding to the supplied data belongs. And 9 pixels forming a matrix of 3 × 3 pixels centered on the pixel of interest in the previous line, based on the data of the previous line immediately before this current line and the data of the previous line immediately before this previous line In the image data processing device for processing the data of the pixel of interest on the basis of the minute data, storage means capable of storing data for two lines, and from this storage means, each of the constituent pixels of the previous line and the line before the preceding line. Means for sequentially reading the data of, the data of each of the constituent pixels of the preceding line and the preceding two lines that have been read, and the data of the constituent pixels of the current line are given, The processing means for performing a predetermined process on the data of the pixel of interest based on predetermined data of the data for 9 pixels forming the matrix of 3 × 3 pixels, and the constituent pixels of the line before the line in the storage means. Means for writing the data of the constituent pixels of the current line at the storage position where the reading of the data has been completed.