JPS6292580A - Picture smoothing device - Google Patents

Abstract

PURPOSE:To simplify the constitution and to obtain a smoothing output by bit-converting and delaying an input (n) bit picture signal and applying two-dimensional smoothing processing. CONSTITUTION:The quadruple data from a ROM40 are delayed respectively for one line by line memories 41 and 42, delaying picture element data are delayed in the column direction by D-FF45-48 and two-bit data for five picture elements are obtained. By using a ROM49, the table conversion is executed to the 21-fold value for the addition and the adding value of the adder bit data. An adder 50 adds the 6-bit data for three picture elements composed of input picture element data and the output data of D-FF43 and 44 and the output after the table conversion, the higher order 6-bit only of the result is considered as the average value and the two-dimensionally smoothed processed picture signal is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to an image smoothing device, such as an image input device for a copying machine, a facsimile machine, or a personal computer, etc., which digitally processes an image and reproduces the image. The present invention relates to an image smoothing device suitable for use in, and particularly relates to an image smoothing device whose purpose is to remove noise.

[Prior art 1] Conventionally, in this type of apparatus, moiré a, which occurs during halftone image processing, or various types of ! Apply image smoothing processing to suppress density unevenness that exists in the background part of the q draft.
However, if an image has density information of, for example, 6 bits, the pixel data is divided into 3×3 pixels or 4×
In order to perform two-dimensional smoothing processing on 4 pixels, 6 bi
A memory is required to store multiple lines of t data.

(8 bits) and is input from terminal S. In FIG. 1, an image memory (also called line memory) 1 and an image memory 2 can each store pixel data (8 bits) for l life.
And the memory! The output and the output of the image memory 2 which is further delayed by one line become pixel signals on the same column that are shifted by one line from each other. Data from the terminal S and the line memory 1.2 are transferred to a 6-bit D-type flip-flop (hereinafter referred to as DF/F) 3, 4. O
By delaying one pixel in the column direction with F/F 5, 8 and DF/F 7.8, if the output of 11F/F 5 is the pixel of interest, the surrounding 3 x 3 pixel data can be detected at the same time. .

Then, if the adder lO adds the data of 9 pixels, and this is multiplied by 1/9 by the divider circuit 9, the pixel of interest (OF/
F5 output) A simple smoothed value over neighboring 3×3 pixels is obtained from the output of the divider circuit 9.

However, line memory 1. and 2, for example, if there are 3456 pixels in the column direction, word IbitS is added to 4.
Each (static) RAM requires six chips, and the SRAM used is also expensive for an item that requires high-speed processing, such as a copying machine. Therefore, as shown in FIG. 2, for example, if the delayed image data stored in the line memories 20 and 22 is set to 2 bits, the number of chips can be reduced to 1/3.

That is, in FIG. 2, the input pixel data to the line memory 20 input from the terminal S' is divided into two upper 8-bit widths.
bit, the input/output end of OF/F23 and the port F/F 2
The 6-bit pixel data is used as is for the 3-pixel signal at the output end of No. 4. On the other hand, the other 6 pixel signals are stored in the line memory 20.
．． 22.0F/F25.2B, 2b via 27.28
This 2-bit 6-pixel signal is multiplied by 21 in the multiplication circuit 31, and the adder 30 multiplies the 8-bit 3
If data for 9 pixels is obtained by adding the data to the pixel signal, smoothing over the 3×3 pixel area as described above can be performed.

[Problem that the invention seeks to solve] In FIG. 2, each pixel data is 2 bits.

"00" → 0 level (decimal system), -1otN → 2I level.

Used for smoothing processing as "10" → 42nd level and "11" → 83rd level. That is, in the circuit shown in FIG. 2, 9 pixel data is handled, 3 pixels of which are handled by 8 bits, and 6 pixels by 2 bits, and the smoothing process is reduced to 24 gradations.

However, for images where the density change within the 3x3 pixels to be smoothed is small and the overall change from white to black, the 24-step density change described above expresses the density change at equal intervals rather than minutely. For example, when the input image level changes from 3 level to 32 level for all 9 pixels, the 2-bit data changes from "O1" to "10".

In other words, during the smoothing calculation, the pixel data is processed as having changed from 2 levels to 42 levels, so the value becomes 32X3 + 42X8 '3232 levels □ = 38 levels. In other words, even though the actual image power is a small density change of 3 levels → 32 levels, the smoothing processing output is 2 levels.
The level changes discontinuously from 4th level to 38th level. In other words, in the reproduced image H, it appears as a pseudo ring.

This means that all 2-bit data used for smoothing is “01” →
This is because it changes to "10". Means for Solving Problem E 1 The present invention has been devised in view of the above problems, and an object of the present invention is to provide an image y-digesting device capable of obtaining a smoothed output with an in-tube configuration.

A further object of the present invention is to provide an inexpensive image smoothing device that can provide stable smoothed output.

To this end, the present invention provides means for converting an input n-bit image signal into m (m<n) bits using a series of periodically changing threshold values, and delaying the m-bit signal obtained by the means, It is characterized by having a delay means for outputting a signal, and a means for inputting an 8-bit m-bit signal and an n-bit image signal obtained by the delay means and performing two-dimensional smoothing processing.

[Example] The invention will now be described in detail with reference to one drawing.

FIG. 3 shows an embodiment of the image smoothing device of the present invention.

In FIG. 3, there are 6 bits in the lower address of ROM 40.
Input the human image data of RON40 and select the top 4 b
A line address and a column address of 2 bits each are input to the it address. ROI114
From 0, 2-bit image data is output according to the designated address. Using this -E position 4-bit address value, 4 pixels x 4 pixels are set to 1@ position, and the 4-value threshold is periodically changed to convert the 6-bit input image data into the optimal 2-bit data in a table. For example, -14 to 14 as shown in Figure 4.
If the value obtained by adding up to the input 6-bit data is used as the reference value for table conversion, then
The bit data is as shown in FIG.

For example, if the input data is 14, in the normal 4-value processing as described above, the 4-value data will be "OO", but in Figure 4, the input data will be "O" and the line address. is "1", the reference value for table conversion is the value obtained by adding two levels to the input data 14, that is, 1B. Therefore, the quaternary data output from the ROM 40 (
2 bit) becomes 01.

In Fig. 4, eight 4-value patterns are stored in a 4x4 matrix as an example, but the input 8 patterns shown in Fig. 5 are
As is clear from the eight ways of 4-value conversion for 3-level data, the 4-value conversion differs depending on the position in the image for uniform density data, so if you average over several adjacent pixels, Although each data has only 4 levels of values, it can be treated as a value that is close to the input 8-bit data and that does not cause any discontinuous part in the density change.

In FIG. 3, the quaternary data from the ROM 40 is stored in line memories 41 and 42 for l lives, respectively.
! : and further delay these delayed pixel data in the column direction by four OF/Fs 45, 48, 47 and 48 (each OF/F delays data by one pixel '!i), Obtain 2-bit data for 5 pixels. Then, 49 is used for RO to perform addition of the 2-bit data of the five pixels and table conversion to a value obtained by multiplying the added value by 21.

Since the adder 50 only needs to calculate the average value of 8 pixels, 6
8-bit data for 3 pixels consisting of input image data of bit t and data obtained through two OF/Fs 43 and 44 that delay the input image data by 1 pixel in the column direction, Addition is performed with the output after table conversion, and only the upper 8 bits of the result are treated as the modulus average value. Therefore, the adder 50 outputs an image signal that has been subjected to two-dimensional smoothing processing.

Note that in this embodiment, 8-bit image data is
An example of converting to IT data was shown, but 3bit, 4b
The processing according to the present invention can be performed in the same way when converting to it data. For example, when converting 6-bit image data to 3-bit data, the added value shown in FIG. 4 is 8 to -
In this embodiment, as shown in FIG. 5, an example in which the normal quaternary level is simply shifted is shown. In other words, the width corresponding to the input level of the quantized 01" or "lO" level is all 16 levels, but if you want to reproduce the middle 1lla degree level more precisely, the width will also be the input level. It may be changed depending on the range.

As explained above, for example, when converting 6-bit image data into 2-bit data, by periodically changing the quantization level, the 2-bit image data is used to smooth the image. , it is possible to improve the linearity of the smoothed value with respect to the original 6-bit pixel data.

[Effects of IJI] As explained above, according to the present invention, by using small-scale hardware, two-dimensional image smoothing processing can be easily realized, and stable smoothing output can be achieved. can be obtained.

[Brief explanation of drawings]

1 and 2 are diagrams showing a conventional image smoothing processing circuit, FIG. 3 is a diagram showing a circuit of an image smoothing device according to an embodiment of the present invention, and FIG. 4 is a diagram showing an example of a matrix in the ROM 40. FIG. 5 is a diagram showing an example of the relationship between storage data in the ROM 40 and addresses. 40, 49-ROM, 41.42... line memory, 43.44.45.4B, 4? , 48...OF/
F, 5θ...adder. Figure 1 Figure 2

Claims (1)

[Scope of Claims] Means for converting an input n-bit image signal into m (m<n) bits using a periodically changing threshold value sequence; and delaying the m-bit signal obtained by the means;
a delay means for outputting a bit signal; a delayed m-bit signal obtained by the delay means; and a delayed m-bit signal obtained by the delay means;
An image smoothing device comprising means for inputting a bit image signal and performing two-dimensional smoothing processing.