JPS61113364A - Picture processor - Google Patents

Abstract

PURPOSE:To suppress moire by modulating the repetitive period of a matrix element in a processor using the dither method. CONSTITUTION:A sole dither threshold value is decided for a dither ROM506 by using address inputs H0-H2, L0-L2. The dither threshold value 511 and a picture signal 510 are compared to obtain a binary-coded signal 512. A moire suppressing factor register 508 stores in a binary value the least significant bit of the picture signal 510 only once at the dither matrix. Thus, although the output of the counter 502 is constant in 8 picture elements in the main scanning direction, a random number of 0-7 is generated at each dither area. The random number is added to picture element counter outputs A0-A2, main scanning direction addresses H0-H2 whose periodicity is unbalanced are obtained, and when the moire suppression factor of the dither area is 1, the phase is shifted by one.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an image processing device that binarizes a gradation-expressed image signal using a dither method.

[Prior Art] Image reproduction is performed by dithering a gravure-printed document (so-called halftone document) using a conventional image processing device.

When this happens, low-frequency beats (moiré patterns) are superimposed on the reproduced image due to interference between the specific frequency components of the halftone dots of the scanned original image and the repeated frequency components of the dither matrix, resulting in an extremely unclear image. There were drawbacks.

As a countermeasure, a method has been proposed in which the interfering frequency components are removed by reading the image using a spatial filter and smoothing the image in an area approximately the size of a dither matrix, followed by dither processing.

However, since this conventional example has the feature of adding processing such as smoothing to the read image signal, high-speed processing requires a two-dimensional digital filter using hardware, resulting in an enormous circuit scale and cost. The general-purpose device had the disadvantage that it was not applicable to Xiaomi.

[Objective] An object of the present invention is to provide an inexpensive image processing device that can suppress moiré that occurs in a reproduced halftone image by modulating the repetition period of matrix elements of a dither matrix. be.

[Example] Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a general 4×4 dither matrix. It is well known that the threshold value of this dither matrix and the image signal are compared and binarized.

In order to make the following explanation easier to understand, elements with threshold values of 8 or less in this dither matrix are shown with diagonal lines, and the numbers assigned to each column of the matrix are ROM (read-only memory) that stores the dither threshold values. ) main scanning direction 7
It can be thought of as a counterpart to Luz.

FIGS. 2(A) to 2(D) are diagrams for explaining the present invention in detail. In general, dither processing uses a group of threshold values periodically, so the same threshold value is repeated for every four pixels in the main scanning direction (arrow in the figure) as shown in FIG. 2(A). As described above, this repetition frequency interferes with the pitch frequency of the halftone dots on the document, generating a low frequency beat and causing moiré.

A feature of the present invention is that, as shown in FIG. 2(B), for example, a moire suppression factor that is randomly set to O or 1 is set for each dither matrix, and this moire suppression factor is used as the main factor of the dither matrix. In addition to the scanning direction address, the added main scanning direction address is used to determine the threshold value of the dither matrix for the next area. In this way, phase modulation is applied to the dither pattern and its periodicity is disrupted.

FIG. 2(C) shows how the dither matrix of FIG. 2(A) is phase-modulated and its periodicity is disrupted.

In the figure, for example, if the dither matrix given by main scanning direction address 1°2.3.4 is selected for the image signal shown in area Bl (block 1), then area B2 (block, 2 ), the suppression factor is 1, so the main scanning direction address of B1 is 1, 2, 3.4.
When +1 is added to, l+1=2.2+1=3.3+1=4
．． Since 4+1=1, 2, 3, 4. The dither matrix whose main operating direction is addressed by L is selected.

If such a method of determining the dither matrix threshold value is adopted, the periodicity of the dither is disrupted, so that low frequency moiré can be significantly reduced.

Figure 2 (D) shows how the generation distance changes due to the phase modulation of the threshold values "lO°" and "6'" elements in the dither matrix.This figure also shows the periodicity. 1.On the other hand, dither joints that may occur in the reproduced image by disrupting the periodicity of the dither matrix have a suppression factor of O or 1.
Therefore, the address difference in the main scanning direction between adjacent blocks is not noticeable since it only causes a difference at most.

Furthermore, if we focus on the same threshold values in the dither matrix, even though they do not occur periodically, there are always 16 types of threshold values within the 4x4 area, so the gradation is hardly disturbed. .

Next, the suppression factor will be explained. Basically, it is desirable that this suppression factor is generated irregularly, and it can be realized by using a random number generator, a noise generator, etc., but the most easily available one is the LSB (least significant bit) of the read image signal. ) is 1 bit. Since the LSB has a change of 0.1 which is almost unrelated to the shading of the image, texture due to its generation mechanism does not appear in the reproduced image.

Alternatively, a change in the intermediate bits of the image signal may be used as the moire suppression factor; that is, the 3rd bit of the 6 bits of the image signal for any one pixel in the block changes from 0.1.1 to 0. For such blocks, 1 is assigned to the suppression factor.

In other words, by performing phase modulation of the dither matrix only on the high spatial frequency parts of the image, it is possible, for example, to perform dither processing that automatically suppresses moiré only on the halftone dots and halftone dots in a document containing text. becomes.

Next, regarding more specific embodiments of the present invention, FIGS.
This will be explained using figures. For convenience of explanation, it is assumed that the image signal is 6 bits and the dither matrix is 8×8.

FIG. 3 is a block diagram of an embodiment of the present invention, in which 1 is C
The image signal quantized to 6 bits by the 0 image reading unit 1, which is an image reading unit consisting of an OD (solid-state image sensor) and an A/D converter, is sent to an image area division circuit 2, a character area binarization circuit 3, and a photo area. The signals are input to a z-value conversion circuit 4 and a halftone area binarization circuit 5, respectively.

The image area dividing circuit 2 determines whether the area is a text area, a photo area, or a halftone area for each block surrounded by 8×8 pixels, and divides the image into a 2-bit area (for example, 00: text area, 01: halftone area). A selection signal consisting of points, 10: photographic area) is input to the multiplexer 7.

On the other hand, the image signals converted from gradation signals to binary signals by the three binary conversion circuits 3, 4.5 described above are input to 8-line delay circuits 6, 9.10, respectively. Each 8-line delay circuit is a circuit that holds binary data of 8 pixels.

In this way, the 8-line delay circuit 6 is connected to the character area binarization circuit 3.
The image signal that has been binarized with emphasis on resolution is sent to the 8-line delay circuit 9 and is then binarized (that is, conventional dithering) by the photographic area binarization circuit 4 with emphasis on continuous tone expression. The image signal is held in the 8-line delay circuit 10, and the image signal converted into a binary image by the above-mentioned phase-modulated dither matrix is held by the halftone area z-value conversion circuit 5.

The image signals binarized in three ways in this way are selected by the multiplexer 7 according to the determination result by the image area division circuit 2. The selected image signal is binarized most appropriately according to the image tone of the original image. This is a black and white image signal which is reproduced by the recording section 8 faithfully to the original image.
.

Next, the halftone area binarization circuit 5 which suppresses moiré in a halftone dot image and binarizes it by phase modulating the dither matrix, which is the subject of the present invention, will be described in detail.

FIG. 4 is a block diagram of the halftone area z value conversion circuit 5.

In FIG. 4, a pixel counter 501 counts a pixel clock synchronized with the image signal of a unit pixel in the main scanning direction.
The bit counter or line counter 505 is a 3-bit counter that counts H5YNC (horizontal synchronization signal) every time one line of image signal is input in the sub-scanning direction. Note that H5YNC is E (enable) of the pixel counter 501.
Pixel counter 5 only when input to the terminal and H3YNC is false.
01 is counted (that is, it is not counted when switching lines).

The moire suppression counter 502 is a 3-bit counter that counts by 1 according to the moire suppression factor '' for each dither matrix. It is something.

The dither ROM 506 stores dither threshold values in an 8×8 matrix, and its main scanning direction address input is Ho.
, H,, Hl, and the sub-scanning direction address inputs are Lo, L 1 , L of the output of the line counter 505 mentioned above.
It is 2.

Address human power Ho +H1, Hz, Lo +LL
A unique dither threshold value is determined in the dither ROM 506 by lL2, and this dither threshold value 511 and the image signal 510 are compared by the comparator 507 to obtain a binarized video signal 512.

Next, the main scanning direction address HO+ of the dither ROM 506
Pixel counter output Ao to obtain Hl + Hl
, A 1 , and Az modulation method will be explained.

Reference numeral 508 denotes a 1-bit moire suppression factor register that stores the z value of the least significant bit of the image signal 510 only once for each dither matrix. Therefore, 508 outputs a value of 1 or O between 8 pixels in the main scanning direction and 8 lines in the sub-scanning direction.

As described above, the output of the moiré suppression factor register 508 is chaotic regardless of the density of the image signal 510.

The NAND gate 503 becomes false when the moire suppression factor is 1 when Ao, AI, and A2 are all true (that is, every 8 pixels in the main scanning direction and every start address of the dither matrix), and the moire suppression counter 502 is counted up. .

In this way, the output of the moire suppression counter 502 is always constant within eight pixels in the main scanning direction, but a random number from 0 to 7 is generated for each dither area. This random number is added to the adder 504
Thus, the main scanning direction addresses Ho, H+, H2 which are added to Ao, A, , A2 and whose one periodicity is lost are obtained.

For example, if the output of the moire suppression counter 502 is 1, the output of the main scanning counter 501 is A0. A1, A2 are 0, 1 in decimal notation. m-., 7, the main scanning addresses Ho, Hl of the dither ROM.

H2 is converted into 1, 2, . φ..., progresses as 7°0.

Therefore, if the moire suppression factor of the next dither area is 1, the moire suppression counter 502 is counted up from 1 to 2, and as a result, the main scanning address of the next dither ROM 506 is 2.3°4.5. 6, 7, 0.1, and the phase is shifted by 1 with respect to the previous dither address.

The above operation is performed for each main scan, but as mentioned above, since the moire suppression factor is constant within the dither matrix, the dither output is 8 in the sub-scan direction.
It is not modulated within the x8 area.

Therefore, the dither matrix of this embodiment is an 8×8 dot concentrated halftone dot dither, and the COD resolution is 16 pe.
In the case of l/ms, the dot density in the main scanning direction is 2 dots/ms.
It is possible to obtain a reproduced image with a constant dot density of 2 dots/mm in the sub-scanning direction by modulating centering around mrn, as in normal dither processing.

In this example, as mentioned above, by applying phase modulation only in the main scanning direction, a considerable moiré suppression effect was obtained; Although the moire that occurs is suppressed in the main scanning direction, it is still noticeable in the sub-scanning direction.

Therefore, as a modification of this embodiment, it is proposed to carry out phase modulation also in the sub-scanning direction, as shown in FIG.

Similar to the embodiment shown in FIG. 4, the same processing as that for the main scanning direction addresses can be applied to the sub-scanning direction addresses, that is, by providing a NAND gate 514, the moiré suppression factor for the sub-scanning direction is 8. For each line, for example, the sub-scan moire suppression counter 509 performs counting using the LSB of the image signal at a specific address in the - main scanning direction.

That is, if the moire suppression factor is 1 for every 8 lines, the moire suppression counter is counted up one by one, and the output thereof is added to the line counter 505 by the adder 513.

As a result, the dither addresses for the 8nth line and the 8n+1st line in the sub-scanning direction are shifted by l life in accordance with the moire confinement, and the periodicity is destroyed as well as the effect in the main scanning direction. In this way, the occurrence of moiré in the sub-scanning direction is also suppressed.

In the embodiment described above, one part of the dither matrix that is read out periodically by adding the moire suppression factor to the main scanning direction address and the sub scanning direction address of the dither ROM.
This image processing apparatus employs a method of skipping one row or one column and shifting it by that amount to modulate the array of dither threshold values.

Therefore, the subtraction value between the count value of the moire suppression counter and the pixel counter and line counter may be used as the address input of the dither ROM. In other words, when using the subtracted value,
At the junction of the dither patterns, the first row or column of the dither pattern becomes equal to the last row or column of all patterns, and one row or column enters into the repetition of the normal pattern, so the periodicity is also disrupted.

Even in this manner, the occurrence of moire can be suppressed.

Next, a case where the dither matrix has a size of 8×8 or more will be described. In such a case, as mentioned above,
The periodicity is not destroyed by simply shifting by one row or column, so the moiré suppression factor is set to 2 bits, and this 2-bit
When at least one of the bits is true, the NAND gate 503 or (and) 514 is opened to increment the moire suppression counter 502 or (and) 509 by the value (1, 2, 3) of the moire suppression factor register.
Changing a part of the circuit 1. In this way, even for dither matrices larger than 8x8, the dither matrix can be shifted by 1 row (or 1 column), 2 rows (or 2 columns), or 3 rows ( or 3 rows) and become completely disordered, and the periodicity is completely destroyed.

In this way, moiré suppression is effective even for dither matrices of 8×8 or more.

[Effect] As explained above, when the image processing device of the present invention is used, the periodicity of the dither matrix generation pattern is destroyed by the moiré suppression factor even if the dither method is used for the halftone image, so the periodicity of the dither matrix is Moiré caused by interference with the periodicity of the halftone image is suppressed.

Furthermore, since the image processing apparatus of the present invention has a much simpler and smaller-scale configuration than conventional image processing apparatuses, the present invention can provide an inexpensive image processing apparatus.

[Brief explanation of the drawing]

FIG. 3 is a block diagram of an image processing device that is an embodiment of the present invention. FIG. 4 is a circuit diagram of a part of an embodiment of the present invention, and FIG. 5 is a circuit diagram of another embodiment in which a part of the embodiment of the present invention is modified. In the figure, 1... Image reading unit, 5... Halftone area z value conversion circuit, 6, 9.10... 8 line delay circuit, 7... Multiplexer, 501... Pixel counter, 502 ,50
9...Moiré suppression counter, 503, 514...N
AND gate, 504, 513... adder, 505.
...Line counter, 506...Dither ROM, 50
7... Comparator, 508... Moiré suppression factor register.

Claims (7)

[Claims] (1) An image processing device using a dither method, which includes means for specifying threshold values in a dither matrix and means for determining the order in which the threshold values are specified, and the image processing is characterized in that the order is determined by random numbers. Device. (2) The image processing apparatus according to claim 1, wherein the means for specifying the threshold values in the dither matrix specifies all the threshold values in the dither matrix once. (3) The image processing apparatus according to claim 2, wherein the order of specifying the threshold values is determined by randomly determining only the selection of rows of the dither matrix. (4) The image processing apparatus according to claim 2, wherein the order of specifying the threshold values is determined by randomly determining only the selection of columns of the dither matrix. (5) The means for determining the order of specifying the threshold values further includes means for holding a part of the image signal, and the order of specifying the threshold values is determined according to the value held in the holding means. An image processing device according to claim 2. (6) The image processing apparatus according to claim 5, wherein the means for holding a part of the image signal holds image information of the least significant bit of the image signal. (7) The image processing apparatus according to claim 5, wherein the data held in the means for holding a part of the image signal is not changed in pixel time corresponding to the matrix size of the dither matrix.