JPS61131683A - Picture processor - Google Patents

Abstract

PURPOSE:To obtain a reproducing picture generating hardly moire against mesh point picture input signal by providing plural means for converting an input picture into a binary code and selecting/outputting the input picture according to the density value of an input picture information. CONSTITUTION:An input signal (i) is quantized to 6 bits in a picture read part 1 and then they are inputted to an image area dividing part 2, and a character area binary part 3, a photographic area binary part 4 and a mesh point area binary 5, respectively. The image area dividing part 2 discriminates at every blocks enclosed by 4X4 picture element whether its area is a character area, or a photographic area or a mesh point area, and outputs the selection signal composed of 2 bits to a multiplexer 7. The multiplexer 7 selects one of the binary signal from each the character area binary part 3, the photographic area binary part 4 and the mesh point binary part 5 based on this selecting signal and output them. Thus, the reproducing picture which is faithful to the original is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to an image processing device that obtains a reproduced image by dividing an image signal expressed in gradations into two.

L Prior Art In conventional image processing devices that use the redaster method, when a Clavia-printed original (so-called halftone original) is dithered and reproduced, the specific frequency components of the halftone dots of the read original image and the dither matrix are Low-frequency beats (moiré pattern) appear in the reproduced image due to interference with the repetitive frequency components of
The disadvantage is that the images are superimposed, resulting in a very unclear image.

As a countermeasure to this problem, a method has been proposed in which a spatial filter is used to smooth the read image in a predetermined area to remove interference frequency components and then dither processing is performed.

FIG. 2 is a block diagram of the image processing apparatus according to the conventional example. 104 is an edge detection/image area determination section, 105 is a changeover switch, and 106 is a recording section.The operation of this configuration will be explained below.

First, the image reading unit 100 is a COD (fixed image sensor)
and an A/D converter, and quantizes the read image information into 6 bits. Quantized gradation image signal i
(X, Y) (X, Y are the coordinates of pixels in the main/sub-scanning direction, respectively) are the smoothing unit 101 and the constant threshold binarization unit 1
02 respectively. The fixed threshold value binarization unit 102 binarizes the image signal i (X, Y) at a fixed threshold value and sends it to the changeover switch 105. Smoothing part 1
01 has an internal line memory, and the image signal is stored in the 11th
The image signal is divided into blocks using the smoothing filter p(x, y) shown in the figure, and the smoothed pixel information of the pixel of interest in the block is converted to the smoothed pixel information value (ΣΣP (X, Y) X i ( X, Y) ) /
Calculated by (ΣΣP (X, Y)).

The pixel density information calculated in this manner is sequentially sent to the dither pattern z-value conversion section 103 and the edge detection section 104. The dither pattern binarization unit 103 uses the dither pattern shown in FIG. 8813 to binarize the input smoothed pixel information and sends it to the changeover switch 105. On the other hand, the edge detection/image area determination unit 104 uses the spatial filter shown in FIG.
The edge portion of the image is detected from the input smoothed pixel information, and the selector switch 105 is changed according to the detection result to select the output of the constant threshold value binarization unit 102 or the dither pattern.
Select one of the outputs of the digitization unit 103 and record it in the recording unit 105.
It is sent to.

However, in the conventional example with the above configuration, since processing such as smoothing is applied to the read image signal, a hardware two-dimensional digital filter is required to speed up image processing, and as a result, the circuit The disadvantage is that the scale is enormous and it cannot be applied to general-purpose equipment due to cost.

"Objective" The present invention has been made in view of the drawbacks of the above-mentioned prior art.
The purpose is to propose an image processing device with a simple configuration that can obtain reproduced images without moiré even when a halftone image signal is input.

"Example" An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.
is an image reading section having a CCO (solid-state image sensor) and an A/D converter section.The image signal i quantized to 6 bits by the image reading section 1 is sent to an image area dividing section 2 and a character area binarization section 3. , are input to the photo area binarization unit 4 and the halftone area binarization unit 5, respectively.

The image area dividing unit 2 determines whether the area is a text area, a photo area, or a halftone area for each block surrounded by 4×4 pixels, and divides the area into 2-bit areas (for example, OO: text area, 01: #1 point area,
lO: photographic area] is output to the multiplexer 7.

- 10,000, the image signals converted from gradation signals to binary signals by the three binary conversion units 3 and 4.5 described above are input to four-line delay circuits 6 and 9.10, respectively. The 4-line delay circuit is a circuit for synchronizing with the image area dividing section 2 and holding binary data of 4 pixels.

In this way, the 4-line delay circuit 6 receives the image signal binarized by the text area binarization unit 3 with emphasis on resolution, and the 4-line delay circuit 9 receives the image signal converted into continuous tone by the photo area 2-digitization unit 4. An image signal that has been binarized with emphasis (that is, conventional dithering) is stored in the four-line delay circuit 10, and a z-valued image signal with moiré suppressed by the halftone area binarization section 5 is held.

The image signals binarized in three ways in this manner are selected by the multiplexer 7 according to the shaving product obtained by the image area dividing circuit 2. The selected image signal is a black and white image signal that has been binarized most appropriately according to the tone of the original image, and is reproduced by the recording section 8 faithfully to the original image.

The image processing apparatus of this embodiment, which aims to suppress the occurrence of moire, has this feature in the halftone area z-value conversion section 5. This halftone area 2
The digitization unit 5 further includes a plurality of binarization circuits therein, and each binarization circuit performs binarization using a different threshold matrix.
It is characterized in that these outputs are selectively output according to the density value of the input image signal.

Therefore, the halftone area binarization section 5 will be described in further detail below.

FIG. 3 is a block diagram of an example of the halftone area z-value conversion section 5. As shown in FIG.

In FIG. 3, i is an image signal quantized to 6 bits by the image reading unit l shown in FIG.
, BL2 in Figure 14, BL3 in Figure 15, 16th
The signals are inputted to four binarization circuits 5-1.5-2.5-3.5-4 each having a different threshold matrix called BL4 in the figure. The comparison conditions in the binarization circuit are as shown in the figure. If the conditions are satisfied, 1 is output, and if the conditions are not satisfied, O is output.
This outputs the following.

The outputs of the four binarization circuits are connected to a gate 2 so that an appropriate binarization signal is output according to the density value of the input image signal i.
0 to 24 are combined. The output condition of each gate 20 to 23 is gate 20=(i)BLl)(i)BL
2) Gate 21+ (i≦BLIJ end (i) BL2) (i) BL3) Gate 22= (i) BLI)
Yo (i≦BL2) book (i) BL3 ngate 23* (
i≦BLI) * (i≦BL2) tremor) BL4), that is, when the image signal i is larger than either the threshold of BLI or BL2, 1 is output, and it is between BLI, BL, and 2. When the image signal i is smaller than BL3, it outputs 0 or l depending on the magnitude relationship between the image signal i and BL3, and when it is smaller than either 8L1 or BL2, it outputs 0 or l depending on the magnitude relationship with BL4. .

In Figure 4, which is a visual graph of the above explanation, BLI (Figure 13) has a small period, and BL2 (Figure 14) has a large period. When the concentration value of the signal i is included in the shaded area in FIG. 4, the output of the gate 24 becomes l, and when it is included in the horizontal line area, the output of the gate 24 becomes the output of the gate 21 or 22, and becomes the threshold value B.
It is determined by the magnitude of L3 and the image signal i. In the case of a white portion, the output of the gate 24 is determined by the magnitude of the threshold value BL4 and the image signal i.

As is clear from the above explanations and figures, by combining the outputs of the plurality of 2 parts according to the density value of the input image signal, it is possible to disturb the generation cycle of the dither pattern as a result. As a result, there is no resonance with the low frequencies of the halftone dots, so moiré does not occur.

In this way, the halftone area binarization unit 5 can suppress moiré no matter what halftone frequency input image signal is input.

Together with the other text area binarization section 3 and photo area binarization section 4, any kind of original image can be faithfully reproduced.

Next, other embodiments of the halftone area binarization section shown in FIGS. 5, 7, and 9 will be described.

First, the configuration example shown in FIG. 5 will be explained. In FIG. 5, the image signal i is an image signal quantized to 6 bits by the image reading section 1 shown in FIG. 3
It is converted into z-value using . The comparison conditions at this time are as shown in the figure; if the conditions are satisfied, 1 is output, and if not, 0 is output. The output of each gate is gate 30- (i) BI, 1) (i) BL2
) Gate 31a (i ≦81, 1) Book (i)
BL2) Book (i) BL3) Gate 32 Tomi (i)
BLl) earthquake (i≦Bl, 2) book (i) BL3).

This is illustrated in FIG. 6, where when the input image signal i is in the shaded area, 1 is output from the gate 30. Further, when it is within the horizontal line portion, O or 1 is output from the gate 31 or the gate 32 depending on the magnitude relationship between the input image signal i and the threshold value BL3. Note that the image signal i is (i≦BLI) (i≦BL2)
When (white part of the graph), O is output.

FIG. 7 is also a block diagram of another configuration example. Comparator 5-6
compares a predetermined constant threshold value T and the image signal l and outputs a binarized signal S, and when the z-valued signal S is 1, the switching switch 42
selects the output of gate 40, and when it is 0, selects the output of gate 41. The fixed threshold value can also be considered as a threshold value matrix with a very large period. That is, the logical formula when the output Out is 1 is 0ut=(i≧BLI)(i≦BL2)(i
≧T) + (i≧BLI) agriculture (i (T) + (i≦BL2) books (i (T)).

This is illustrated in FIG. 8, where the output Out is 1 when the image signal i is in the shaded area, and O otherwise.

FIG. 9 is also a block diagram of another configuration example. Z value conversion circuit 5
-1.5-3.5-5 are shown in Figures 13, 15, and 1, respectively.
Dither pattern 8L1, BL3, B shown in Figure 7
It has L5. The output of each gate is gate 50 wealth (i) BL5) book (i) BLI
) Gate 51= (i ≦BL5) Attack (i) B
LI) Book (i) BL3) Gate 52- (i) BL5
) Book (i≦BLI) Book (i) BL3).

This is diagrammed in Fig. 10. In Fig. 10, the one with a large period is the threshold BL5 in Fig. 17.
is (1) BL5) book (i) BLI) (shaded area) is 1
, (i≦BL5) low (i) BLl) or (i) BL5
) When (i≦BL1) (horizontal line portion), the result of determining whether the image signal i and the threshold value BL3 are large or small is output. However, since the dither pattern shown in FIG. 17 has an area of 17×17, it is larger in terms of circuitry compared to other embodiments, but it is not compared to the conventional example.

Although the four embodiments have been described above, similar results can be obtained using any of the circuits, but there are some differences in conversion characteristics. Therefore, it is natural to combine these methods, and a good result can be obtained by doing so.

[Effects] As explained above, according to the present invention, a plurality of threshold matrices are combined to eliminate the repetitive frequency components peculiar to each threshold matrix, so that a reproduced image faithful to the original without the occurrence of a moiré pattern of low frequency components can be obtained. can be obtained.

[Brief explanation of the drawing]

FIG. 1 is an overall block diagram of an embodiment to which the present invention is applied, FIG. 2 is a block diagram of a conventional example, and FIG. 3 is a block diagram of a halftone area binarization section of the embodiment. FIG. 4 is a density diagram illustrating the processing results of the configuration shown in FIG. 3; FIGS. 5, 7, and 9 are block diagrams of halftone area binarization units having other configurations; FIG. , FIG. 8, and FIG. 1θ show halftone area 2 having other configurations.
A density diagram illustrating the processing results of the value conversion section. Fig. 11 is a smoothing filter matrix diagram, Fig. 12 is a matrix diagram of an edge detection filter, and Figs. 13 to 17 are dither threshold values BLI to BL5.
FIG. In the figure, 5... Halftone area binarization unit, 10... 4 line delay circuit, 5-1 to 5-5... Binarization unit, 5-8... Comparator, 42... ...Selector switch, 20-24.30-33.
40-41.50-53...gate, i...image signal. Out... Output. Patent applicant Canon Co., Ltd. No. 35! l Fig. 4; Spin No. 5rIB No. 6vA Fig. 7 Fig. 8 Fig. 9 Fig. 10 ill Fig. 12 Fig. 13 Fig. 14

Claims (3)

[Claims] (1) A plurality of binarization means each having a threshold mactor having a different cycle and binarizing input image information, and outputting the output of the binarization means according to the density value of the input image information. An image processing device having a selection means for selecting/outputting. (2) The image processing apparatus according to claim 1, wherein the selection means is constituted by a gate circuit. (3) The image processing device according to claim 1, wherein one or more of the threshold value matrices are fixed threshold values.