JPH0637648A - Error correcter - Google Patents

Abstract

PURPOSE:To operate an error correction processing for a period of time equivalent to a data inputting and outputting period of time, and to shorten a processing period of time by independently operating a syndrome preparation, correction data writing, chain search, and arithmetic processing in parallel. CONSTITUTION:Data of one system are inputted from a data input and output terminal 8 synchronously with a start signal 9. A syndrome is prepared by a syndrome preparing circuit 1, and the preparation of the syndrome is operated synchronously with the input of the data. The prepared syndrome is read in a storage circuit 5, and the calculation of an error position polynomial is operated by an arithmetic circuit 4. The calculated error position polynomial is inputted to a chain search circuit 3, the detection of the error position is operated, the detected error position is read in the storage circuit 5, and the calculation of the error value is operated by the arithmetic circuit 4. The calculated result is outputted to a correction data writing circuit 2, and the correction of the data is operated through the input and output terminal 8. Thus, the error correction processing time can be shortened without increasing a circuit scale.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction device for decoding a Reed-Solomon code using a Chien search to correct an error.

[0002]

2. Description of the Related Art In a digital signal recording / reproducing apparatus such as a magnetic tape or an optical disk, an error correction code is used to correct a data error caused by a dropout on a recording medium. In particular, the Reed-Solomon code has excellent error correction capability and is used in many systems. In recent years, with the improvement of recording density, Reed-Solomon code having a large error correction capability, that is, a large minimum distance has been used.

Conventionally, when decoding a code with a large minimum distance, the Institute of Electronics, Information and Communication Engineers Technical Report IT88-65.
As described in (November, 1988), a method in which syndrome generation and chain search are performed by a dedicated circuit and other operations are performed by a microprogram has been used. This method is characterized in that the circuit scale is small.
As shown in, syndrome generation, error polynomial calculation,
Since the chain search and the calculation of the error value are sequentially performed, there is a problem that the processing time becomes long.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems of the prior art, to shorten the processing time, and
It is to provide an error correction device having a small circuit scale.

[0005]

The above object can be achieved by allowing the syndrome generation circuit, the Chien search circuit and the arithmetic circuit to operate independently and performing the respective processes in parallel.

[0006]

The function of the syndrome generation circuit is to generate the syndrome in synchronization with the input of data. The arithmetic circuit calculates the error locator polynomial from the syndrome generated at the previous timing in parallel with the generation of the syndrome, and inputs the result to the Chien search circuit. Then, the Chien search circuit detects the error position, and at the same time, the arithmetic circuit calculates the error value from the error position detected at the previous timing. As a result, the error correction processing time can be shortened without increasing the circuit scale.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. Reference numeral 1 is a syndrome generation circuit that generates a syndrome from input data, 2 is a correction data writing circuit that corrects data according to an operation result, 3 is a Chien search circuit that detects an error position from an error position polynomial, and 4 is an error position polynomial. And an arithmetic circuit for calculating an error value, 5 is a memory circuit for temporarily storing the arithmetic result and the like, 6 is a program control circuit for controlling the arithmetic circuit 4 and the memory circuit 5 by a micro program to perform a predetermined arithmetic operation, 7 Is a timing generation circuit for controlling the operation timing of each circuit. Reference numeral 8 is a data input / output terminal, 9 is an input terminal for a start signal which serves as a reference for correction processing operation, and 10 is an input terminal for an operation clock. One series of data is input from the data input / output terminal 8 in synchronization with the start signal 9. Then, the syndrome generation circuit 1 generates a syndrome. The generation of this syndrome is performed at the same time as the data input. The generated syndrome is read into the memory circuit 5, and the arithmetic circuit 4 calculates the error locator polynomial.
The calculated error locator polynomial is input to the Chien search circuit 3 and the error position is detected. The detected error position is read into the memory circuit 5, the error value is calculated by the arithmetic circuit 4, and the error value is input to the correction data writing circuit 2. Then, the data is corrected via the data input / output terminal 8.

FIG. 2 is a timing chart showing the correction processing timing. The data input at timing 11 is
Syndrome is generated in synchronization with the input. And 1
Calculation of error locator polynomial at timing 2 (operation 1), 1
Detection of error position by chain search at timing 3
The error value is calculated (operation 2) at the timing of 14 and 1
The data is corrected at the timing of 5.

In the syndrome generation circuit 1, the processing of one series is completed at the time when the generated syndrome is transferred to the storage circuit 5, so that the syndrome of the next series is continuously generated from the next start signal. In the arithmetic circuit 4, since the processing of the operation 1 ends at the time when the result of the error locator polynomial is output to the Chien search circuit, the error in the previous sequence is continuously used by using the error position detected by the Chien search circuit 3 at the previous timing. Calculate the value. In the chain search circuit 3,
At the time when the error position detection result is transferred to the storage circuit 5, the processing of one series is completed, so that the error position of the next series is continuously detected.

As described above, by performing data input / output (syndrome generation and data correction), calculation, and chain search independently and in parallel, data is error-corrected in a time equivalent to the input / output time. You can If the execution time of the operations 1 and 2 is longer than the data input / output time, the interval of the start signal may be increased according to the operation time.

FIG. 4 is a calculation control flow in the program control circuit 6. The calculation is started when the data input is completed. First, the syndrome data generated by the syndrome generation circuit 1 is transferred to the storage circuit 5, and the error locator polynomial is calculated using the data. Next, the Chien search circuit 3 confirms whether or not the detection of the error position of the previous sequence is completed. If it is completed, the detection result is transferred to the storage circuit 5 and the chain of the error position polynomial calculation result is confirmed. The transfer to the search circuit 3 is performed, and an instruction to start the error position detection operation is issued to the chain search circuit 3. And
An error value is calculated using the detection result of the error position of the previous series, and the result is output to the correction data writing circuit 2.

FIG. 5 shows an embodiment of the syndrome generation circuit 1. Reference numeral 16 is an addition circuit, 17 is a latch circuit, and 18 is a coefficient multiplication circuit. The syndrome can be generated by operating the latch circuit 17 in synchronization with the data input after resetting the latch circuit 17. Although a circuit for generating one syndrome is shown here, a plurality of circuits with different coefficients to be multiplied are actually used. For example, when the minimum code distance is 7, 6 circuits are used.

FIG. 6 shows another embodiment of the syndrome generation circuit 1. In FIG. 6, by providing the latch circuit 23 for storing the generated syndrome, the transfer of the syndrome data generated by the syndrome generation circuit 1 to the storage circuit 5 in the flow of FIG. 4 can be omitted.

FIG. 7 shows an embodiment of the correction data writing circuit 2. 24 is a latch circuit for storing an error value, 25
Is a latch circuit for latching uncorrected data, 26 is an adder circuit, and 27 is a buffer with output control. When the calculation of the error value is completed in the arithmetic circuit 4, the result is latched in the latch 24 and stored. To correct the data, first, the data to be corrected is input to the latch 25, the data and the error value stored in the latch 24 are added by the adder circuit 26 to generate the corrected data, and the corrected data is generated via the buffer 27. This is done by outputting. When there are a plurality of pieces of data to be corrected, the number of latches 24 may be prepared.

FIG. 8 shows an embodiment in which the Chien search circuit 3 corrects three words. 33 is a latch circuit, 3
4 is a coefficient multiplication circuit, 35 is an addition circuit, 36 is a control circuit for controlling the latch circuit 33, 37 is a register for storing the detected error position, and 38 is a buffer with output control. First, when the calculation of the error one polynomial is completed in the arithmetic circuit 4, the coefficient of each degree of the polynomial is latched in the corresponding latch 33. Next, the input of the latch 33 is switched to the coefficient multiplying circuit 34, and the latch is repeated for the code length of one series of codes. At this time, the control circuit 36 monitors the output of the adder circuit 35 and stores the number of latches when the value becomes 1 in the register 37 as an error position. After the processing is completed, the value stored in the register 37 is output via the buffer 38 in response to the request from the program control circuit 6.

[0017]

As described above, according to the present invention,
By enabling the syndrome generation circuit, the Chien search circuit, and the arithmetic circuit to operate independently, and performing the respective processes in parallel, it is possible to perform error correction processing on the data in a time equivalent to the input / output time. The processing time can be shortened without providing a circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an operation timing of the embodiment of FIG.

FIG. 3 is a diagram showing an operation flow of error correction processing.

FIG. 4 is a diagram showing an operation flow of a program control circuit.

FIG. 5 is a diagram showing an embodiment of a syndrome generation circuit.

FIG. 6 is a diagram showing another embodiment of the syndrome generation circuit.

FIG. 7 is a diagram showing an embodiment of a correction data writing circuit.

FIG. 8 is a diagram showing an embodiment of a chain search circuit.

[Explanation of symbols]

1 ... syndrome generation circuit, 2 ... correction data writing circuit,
3 ... Chien search circuit, 4 ... Arithmetic circuit, 5 ... Memory circuit,
6 ... Program control circuit.

Claims (2)

[Claims] 1. A syndrome generation circuit for generating a syndrome from input data, an arithmetic circuit for calculating an error locator polynomial and an error value from the syndrome, a Chien search circuit for detecting an error value from the error locator polynomial, and the error. The syndrome generation circuit and the correction circuit operate in synchronization with the input / output of data, and the arithmetic circuit and the Chien search circuit respectively include the syndrome generation circuit and the correction circuit. An error correction device which operates in parallel with the above operation. 2. The syndrome generation circuit, after outputting the generated syndrome, subsequently generates the next series of syndromes, and the arithmetic circuit calculates an error locator polynomial from the time when the syndrome is generated, When it is finished, the calculation result is output to the Chien search circuit, and subsequently, the error value is calculated using the error position of the previous sequence detected by the Chien search circuit and output to the correction circuit, 2. The error correction device according to claim 1, wherein the Chien search circuit outputs the detected error position and at the same time inputs the error position polynomial of the next sequence to detect the error position of the next sequence.