JPH0637315A - Manufacture of active matrix substrate - Google Patents

Abstract

PURPOSE:To provide a manufacture of a TFT having an insulating film which is very fine in property and excels in electrical characteristics. CONSTITUTION:An oxidizing gas is supplied to TEOS so as to cover a silicon thin film 2 on a transparent insulating substrate 1, SiO2 is accumulated thereon by a photo CVD method to form a gate insulating film 3. A gate electrode 4 is formed on the gate insulating film 3, and an impurity ions are implanted into the silicon thin film 2 to form contact layers 5a, 5b and a semiconductor layer 5c. A layer insulating film 6 is laminated all over the substrate so as to cover a gate electrode 4 and the gate insulating film 3 by the similar method to that for the gate insulating film 3. A source electrode 8 and a drain electrode 9 are so formed as to pass through the layer insulating film 6 and the gate insulating film 3 to interconnect the contact layers 5a, 5b. An ITO film is formed on the layer insulating film 6, and a picture element electrode 10 is formed by patterning and is connected with the drain electrode 9. An insulating film 6' on the layer insulating film 6 is formed with the similar material and method to those for the layer insulating film 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an active matrix substrate which constitutes a liquid crystal display device or the like in which picture element electrodes are arranged in a matrix and a switching element is connected to each picture element electrode. Regarding

[0002]

2. Description of the Related Art An active matrix substrate is provided in each of a plurality of source bus lines, a plurality of gate bus lines orthogonal to each source bus line, and each region formed by intersecting both bus lines. And a thin film transistor (Thin-Film-Transistor, hereinafter TF) as a switching element.
(Abbreviated as T) is connected. Figure 7 shows a conventional TFT
FIG.

This TFT has a silicon thin film 82 formed on a transparent insulating substrate 81 such as glass or quartz, a gate insulating film 83 formed over the entire surface of the substrate to cover the silicon thin film 82, and this gate insulating film. A gate electrode 8 branched from a gate bus line formed in contact with 83
4 and.

An interlayer insulating film 86 is laminated on the gate bus line and the gate electrode 84, and a source bus line 88 'is provided on the interlayer insulating film 86 orthogonal to the gate bus line.

The semiconductor layer 85c in the central portion of the silicon thin film 82 has a gate electrode 84 sandwiching the gate insulating film 83.
Is facing.

A source electrode 88 branched from a source bus line 88 'penetrating the interlayer insulating film 86 and the gate insulating film 83 is connected to one of both sides of the silicon thin film 82 excluding the semiconductor layer 85c, and the other is provided with an interlayer. A drain electrode 89 is connected through the insulating film 86 and the gate insulating film 83.

The silicon thin film 8 of the drain electrode 89
A pixel electrode 90 formed on and in contact with the interlayer insulating film 86 is connected to the end opposite to the side connected to 2.

[0008]

The gate insulating film of the TFT and the interlayer insulating film between the gate bus line and the source bus line are formed by a thermal oxidation method or a thermal C using a silane-based gas.
Si formed by VD method or plasma CVD method
An O ₂ film is used. In the thermal oxidation method, Si is thermally oxidized at a high temperature of 1000 ° C. or higher to form an SiO ₂ insulating film. The insulating film thus formed has characteristics that the film quality is dense, the defect density in the film is small, and that impurities are hardly present in the film. On the other hand, in the thermal CVD method using a silane-based material gas, in order to improve the film quality in forming the insulating film, the film formation temperature is set to 1000 ° C. or higher, and the insulating film formed by the thermal oxidation method is used. An insulating film having a quality similar to that of the film is obtained. But,
When forming a film at such a high temperature, if an inexpensive substrate having poor heat resistance is used, the substrate is softened by high heat. Therefore, the insulating film is formed at a low temperature of 600 ° C. or lower which is the softening point of the substrate. However, the insulating film formed at such a low temperature is inferior to the insulating film formed by the thermal oxidation method in the denseness of the film, the defect density in the film is large, and further the impurities are present. A film with low film quality is generated, and as a result, the withstand voltage decreases, the leak current increases,
The increase in the interface state density at the boundary between the semiconductor thin film and the insulating film causes carrier scattering and the like, resulting in deterioration of the electrical characteristics and reliability of the TFT.

Even if the film forming temperature is lower than the softening point of the substrate material, if the temperature is close to 600 ° C.,
Residual stress due to the difference in the coefficient of thermal expansion between the insulating film and the substrate causes warping, deformation, cracking of the insulating film, and the like in the substrate, and such defects in the substrate appear as large defects in the TFT. Such a defect of the substrate becomes more remarkable when the size of the substrate is increased. Therefore, the method of forming the insulating film by the thermal CVD method cannot be performed when the size of the substrate is increased.

Further, in the plasma CVD method, plasma accelerates the decomposition and generation reaction of the insulating film material, and the insulating film can be formed even at a low temperature of 600 ° C. or lower. Therefore, defects in the insulating film formed by the thermal CVD method are Although it is largely improved, since the film is formed under reduced pressure, the insulating film formed is inferior in the differential coverage and the portion formed on the differential sidewall becomes a thin and fragile film.

As described above, any of the CVD methods causes a TFT defect such as a decrease in breakdown voltage or an increase in electrical leakage between the gate electrode and the source portion of the TFT or between the gate electrode and the drain portion of the TFT.

Further, since the vapor phase reaction is dominant in the CVD method, particles are likely to be generated and pinholes are easily formed, so that electrical leakage increases, which is also caused by TF.
It leads to a big defect of T.

CVD of an interlayer insulating film between a source and a gate
Also when formed by the method, there is a problem that the formed insulating film is inferior in differential coverage and breakdown voltage for the same reason. The present invention solves such a problem of the conventional technique, and provides a method for manufacturing an active matrix substrate capable of forming a gate insulating film or an interlayer insulating film with few defects over a large area even at a relatively low temperature. The purpose is to

[0014]

According to the method of manufacturing an active matrix substrate of the present invention, a plurality of signal wirings and a plurality of scanning wirings sandwich an interlayer insulating film between them on a transparent insulating substrate. The pixel electrodes that drive the liquid crystal and the switching elements that drive the pixel electrodes are provided in the respective regions that are arranged orthogonal to each other and are surrounded by the adjacent signal lines and scanning lines. A method for manufacturing an active matrix substrate, wherein the element is a thin film transistor having a semiconductor layer and a gate electrode provided with an insulating film sandwiched therebetween, the insulating film supplying an organosilane compound having an alkoxyl group, and a CVD method. By supplying the organosilane compound having an alkoxyl group and forming the insulating film formed by the CVD method, the above object can be achieved.

In the method of manufacturing an active matrix substrate of the present invention, a plurality of signal wirings and a plurality of scanning wirings are arranged on a transparent insulating substrate so as to be orthogonal to each other with an interlayer insulating film interposed therebetween. A method for manufacturing an active matrix substrate having a picture element electrode for driving a liquid crystal and a switching element for driving the picture element electrode in each region surrounded by each adjacent signal wiring and each scanning wiring. The above object is achieved by forming the insulating film by a CVD method by supplying an organosilane compound having an alkoxyl group.

[0016]

According to the manufacturing method of the present invention, the decomposition of the material gas of the film and the decomposition and removal of the reaction product are sufficiently performed.
An insulating film having a dense film quality, excellent step coverage, and excellent electrical characteristics is formed even at a low temperature of ℃ or below.

[0017]

EXAMPLES Examples of the present invention will be described below.

[First Embodiment] FIG. 1 is a plan view showing the structure of a unit pixel of an active matrix substrate of the present invention, FIG.
2 is a sectional view taken along the line AA ′ of FIG.

A plurality of source bus lines 8'are arranged in parallel on the transparent insulating substrate 1 such as glass or quartz, and a gate bus line 4'is arranged orthogonal to each source bus line 8 '. It is set up. The pixel electrodes 10 are arranged in almost the entire area surrounded by the bus lines 4'and 8 ',
A TFT (thin film transistor) for driving the picture element electrode 10 is provided near one corner of the picture element electrode 10.

This TFT has a silicon thin film 2 formed on a transparent insulating substrate 1. Silicon thin film 2
Extends from the lower region of the source bus line 8 ′ to the lower region of the pixel electrode 10 in parallel with the gate bus line 4 ′. The silicon thin film 2 is covered with a gate insulating film 3 which is laminated on the entire transparent insulating substrate 1. A gate electrode 4 branched from a gate bus line 4 ′ is laminated at a position of the gate insulating film 3 with respect to the central portion of the silicon thin film 2.

The gate electrode 4 and the gate insulating film 3
An interlayer insulating film 6 is laminated on the entire surface of the substrate.

The silicon thin film 2 has a contact layer 5a and a contact layer 5b in which impurities are ion-implanted, and a semiconductor layer 5c in the center, on each side except the center facing the gate electrode 4. There is.

Contact holes 11 and 12 penetrating the gate insulating film 3 and the interlayer insulating film 6 are provided on the contact layer 5a and the contact layer 5b of the silicon thin film 2, respectively. Is provided with a source electrode 8, and the source electrode 8 is connected to a source bus line 8 ′ provided on the interlayer insulating film 6.

At the intersection of the source bus line 8'and the gate bus line 4 ', an interlayer insulating film 6 is laminated as shown in FIG.

A drain electrode 9 is provided in the contact hole 12 on the other contact layer 5b, and a part of the drain electrode 9 is laminated on the interlayer insulating film 6.

A drain electrode 9 is formed on the interlayer insulating film 6.
The picture element electrode 10 is laminated so that a part thereof is laminated. An insulating film 6 ′ that covers portions other than the pixel electrodes 10 is laminated on the interlayer insulating film 6. The insulating film 6'is made of the same material as the interlayer insulating film 6.

Such an active matrix substrate is manufactured as follows.

Amorphous silicon or polycrystalline silicon is laminated on the transparent insulating substrate 1 by a low pressure CVD method, a plasma CVD method or the like, and patterned to form a silicon thin film 2. At this time, when using polycrystalline silicon, a high quality film can be obtained by performing an annealing treatment. Next, the gate insulating film 3 is formed over the entire transparent insulating substrate 1. The gate insulating film 3 is formed of an organic silane compound having an alkoxyl group or SiO ₂ deposited by a plasma CVD method or an optical CVD method by supplying an oxidizing gas to an organic silane compound having an alkoxyl group. .

In this example, TEOS of the chemical formula Si (C ₂ H ₅ O) ₄ , which is a kind of organosilane compound having an alkoxyl group, was used.

When TEOS is used, it is considered that the reaction on the substrate surface is predominant during film formation, and in general, the step portion can be covered better as compared with the CVD method using a silane-based material gas. . Further, since the generation of particles in the vapor phase is relatively suppressed, the number of defects in the insulating film is reduced.

Further, in the thermal CVD method using TEOS,
Although the temperature of 750 ° C. or higher is required for the thermal decomposition of the mixed gas of TEOS and oxygen, in the plasma CVD method using ozone as the oxidizing gas, plasma promotes the decomposition and generation reaction of TEOS, and further ozone Since the active oxygen generated by the decomposition of TEOS also improves the decomposition efficiency of TEOS, 6
It is possible to form a predetermined insulating film even at a low temperature of 00 ° C. or lower.

The film forming temperature in this case is preferably 400.
C. or lower, more preferably 315.degree. C. or lower.

The gate insulating film 3 has a thickness of 200.
0 angstrom or less, preferably 100 to 1000
It is said to be Angstrom.

Next, a CVD method, a vapor deposition method, or a sputtering method is performed on the gate insulating film 3 using amorphous silicon doped with impurities serving as donors or acceptors, polycrystalline silicon, or refractory metals such as Cr and W. Then, the gate bus line 4'and the gate electrode 4 are formed by patterning.

At this time, the film thickness of the gate bus line 4'and the gate electrode 4 is preferably 1000 to 4000 angstrom.

Next, impurities of Group V element or its compound, or impurities of Group III element or its compound are accelerating voltage of 1 kV from above the gate electrode 4 and the gate insulating film 3 over the region where the silicon thin film 2 is formed. ~
Ion implantation is performed at 100 kV.

As a result, the gate electrode 4 of the silicon thin film 2
The semiconductor layer 5c in the region opposite to that, that is, the central portion of the semiconductor layer 5c is shielded by the gate electrode 4 and ion implantation is not performed, and the semiconductor layer 5c remains as a film component when the silicon thin film 2 is formed. Impurities are implanted in the respective regions at a high concentration to form contact layers 5a and 5b.

Next, the interlayer insulating film 6 is laminated over the entire transparent insulating substrate 1. The interlayer insulating film 6 has a film forming temperature of 600 ° C. or lower, preferably 400 ° C. or lower, and more preferably 315 ° C. or lower. In this example, a chemical formula Si, which is a kind of organosilane compound having an alkoxyl group, is used.
(C ₂ H ₅ O) ₄ TEOS was used. When the interlayer insulating film 6 is formed by the thermal CVD method, ozone may be used as the oxidizing gas. The thickness of the interlayer insulating film 6 is set to 2000 to 6000 angstroms or more.

Next, the contact hole 11 that penetrates the interlayer insulating film 6 and the gate insulating film 3 to reach one contact layer 5a of the TFT, and the other of the TFT that penetrates the interlayer insulating film 6 and the gate insulating film 3 The contact holes 12 reaching the contact layers 5b are formed respectively.

Al, Mo, C are formed so that the contact holes 11 and 12 are filled.
A source bus line 8'is formed by laminating a metal such as r on the interlayer insulating film 6 to form the source electrode 8 and the drain electrode 9 and patterning the metal.

Next, an ITO film having a thickness of 500 to 1000 angstrom is formed on the interlayer insulating film 6, and a drain electrode is formed in a predetermined region of each unit section surrounded by the source bus line 8'and the gate bus line 4 '. The pixel electrode 10 is formed by patterning so as to be partially connected to the pixel electrode 9. TF
The other contact layer 5b of T is electrically connected to the pixel electrode 10 via the drain electrode 9.

Finally, SiO ₂ is laminated on the entire surface of the substrate by the same material and method as the interlayer insulating film 6, and is patterned so as to remove the SiO ₂ on each pixel electrode 10 to form an insulating film 6 '.

As a result, an active matrix substrate is manufactured.

According to the manufacturing method of this embodiment, it is possible to obtain the gate insulating film 3 and the interlayer insulating film 6 which are dense and have few defects in the film and have excellent electric characteristics and high reliability.

[Second Embodiment] FIG. 4 is a sectional view of a TFT provided on an active matrix substrate according to a second embodiment of the present invention.

In this TFT, a contact layer 25a and a contact layer 25b are provided at appropriate intervals on a transparent insulating substrate 21 such as glass or quartz. Each contact layer 25a and contact layer 25b is composed of a silicon thin film 22 to which impurities serving as donors or acceptors are added.

In the gap between the contact layers 25a and 25b, the semiconductor layer 25c made of the silicon thin film 22 is formed.
Is laminated on the transparent insulating substrate 1 so as to cover the ends of the contact layers 25a and 25b on the side of the gaps.

The contact layer 25a and the contact layer 25b each have a thickness of about 500 to 2000 angstroms.

Further, the semiconductor layer 25c of the contact layer 25a
A source electrode 28 which is a part of the source bus line is provided on the side opposite to the side where a part of the contact layer is laminated, and the semiconductor layer of the contact layer 25b is provided. A drain electrode 29 is formed on the side opposite to the side where 25c is laminated so as to cover this side.

The contact layer 2 is formed on the transparent insulating substrate 21.
A gate insulating film 23 is entirely laminated so as to cover 5a, the semiconductor layer 25c, the contact layer 25b, the source electrode 28, and the drain electrode 29. A gate electrode 24 branched from the gate bus line is laminated on the gate insulating film 23 corresponding to the upper region of the semiconductor layer 25c.

An interlayer insulating film 26 is laminated over the entire surface of the substrate on the gate insulating film 23 excluding the gate bus line and the gate electrode 24, and the gate bus line and the gate electrode 24 are covered with the interlayer insulating film 26. .

Gate insulating film 23 on drain electrode 29
A contact hole 32 is formed in the contact hole 32, and a part of the pixel electrode 30 laminated at a predetermined position on the gate insulating film 23 enters the contact hole 32 and is connected to the drain electrode 29.

The method of manufacturing such a TFT is as follows.

Amorphous silicon or polycrystalline silicon containing impurities serving as donors or acceptors is deposited on the transparent insulating substrate 21 at a predetermined interval under reduced pressure CVD.
Method, plasma CVD method, or the like, and contact layers 25a and 25b are formed by patterning.

In the semiconductor layer 25c, the contact layer 25a and the contact layer 25b are contacted so that the contact layer 25a and the contact layer 25b are laminated at intervals so as to fill the space between the contact layer 25a and the contact layer 25b. Amorphous silicon or polycrystalline silicon is formed by the low pressure CVD method so as to cover the gap side portions of the layers 25b.
It is deposited by a plasma CVD method or the like. The thickness of the semiconductor layer 25c is preferably 2000 angstroms or less.

Annealing treatment is applied to polycrystalline silicon to obtain a high quality film.

Next, the source electrode 28 and the drain electrode 29
Are patterned on the transparent insulating substrate 21 by using Ti, Al, Mo, Cr and the like together with the source bus line.

The source electrode 28 is formed on the side of the contact layer 25a opposite to the side in contact with the semiconductor layer 25c so as to cover this side. The drain electrode 29 is formed on the side of the contact layer 25b opposite to the side in contact with the semiconductor layer 25c so as to cover this side. Each of the source bus line, the source electrode 28, and the drain electrode 29 is formed with a thickness of 2000 to 6000 angstrom.

Next, the semiconductor layer 25c, the contact layer 25a, the contact layer 25b, and the source electrode 28 described above.
The gate insulating film 23 is formed so as to cover the drain electrode 29 and the source bus line, but the method and material are the same as in the case of the first embodiment. Also in this embodiment, the density and the number of defects are small. A film with good film quality can be obtained.

On the gate insulating film 23, gate bus lines and gate electrodes 24 are formed by patterning over the entire surface of the substrate. The method and material are the same as in the case of Example 1, and a dense film with few defects and good film quality can be obtained.

At this time, the film thickness of the gate bus line and the gate electrode 24 is set to 1000 to 4000 angstrom.

An interlayer insulating film 26 is laminated on the gate bus line and the gate electrode 24 over the entire surface of the substrate. The method and material are the same as in the case of Example 1, and a dense film with few defects and good film quality can be obtained.

The thickness of the interlayer insulating film 26 is 2000 to 600.
It is considered to be 0 angstrom or more.

Next, the contact layer 25b becomes the semiconductor layer 25c.
The drain electrode 29 penetrates the interlayer insulating film 26 and the gate insulating film 23 at the position where the drain electrode 29 covers the end of the contact layer 25b at the end of the contact layer 5b opposite to the contact with the drain electrode 29. A contact hole 32 that reaches is formed.

Then, an ITO film having a thickness of 500 to 1000 angstrom is formed on the interlayer insulating film 26, and the pixel electrode 30 is patterned in a predetermined region of each unit section surrounded by the source bus line and the gate bus line. At the same time, it is formed and connected to the drain electrode 29 through the contact hole 32.

As a result, an active matrix substrate is manufactured.

Also according to the manufacturing method of this embodiment, it is possible to obtain the gate insulating film 23 and the interlayer insulating film 26 which are dense and have few defects in the film and have excellent electric characteristics and high reliability.

Further, in the present embodiment, it is not necessary to provide an insulating film on the interlayer insulating film 26 as in the first embodiment, and the first
The productivity is improved as compared with the embodiment of.

[Third Embodiment] FIG. 5 is a sectional view of a TFT provided on an active matrix substrate according to a third embodiment of the present invention.

This TFT is formed by forming a gate electrode 44 branched from a gate bus line provided on a transparent insulating substrate 41 such as glass or quartz, and covering the gate electrode 44 over the entire surface of the substrate. Of the gate insulating film 43, and a gate electrode 44 in contact with the gate insulating film 43.
A silicon thin film 42 formed at a position facing
It has a channel protective film 47 laminated on the central portion on the silicon thin film 42.

Then, an interlayer insulating film 46 is formed over the entire surface of the substrate so as to cover the silicon thin film 42 and the channel protective film 47 and contact the gate insulating film 43.

A central region of the silicon thin film 42 immediately below the channel protective film 47 is a semiconductor layer 45c, and both side portions except the semiconductor layer 45c are a contact layer 45a and a contact layer 45b.

Contact holes 51 and 5 are formed in the contact layers 45a and 45b so as to penetrate the interlayer insulating film 46.
2 is connected.

The source electrode 48 branched from the source bus line 48 'is connected to the contact layer 45a via the contact hole 51, and the drain electrode 49 is connected to the contact layer 45b via the contact hole 52. The pixel electrode 50 is stacked on the interlayer insulating film 46 in a predetermined region of each unit section surrounded by the source bus line 48 'and the gate bus line, and the drain electrode 49 is connected to the contact layer 45b. The end opposite to the end is connected to the drain electrode 49.

The contact layer 45b is electrically connected to the pixel electrode 50 via the drain electrode 49.

On the inter-layer insulation film 46, an insulation film 46 ′ covering a portion other than the pixel electrode 50 is laminated. Insulation film 4
6'is made of the same material as the interlayer insulating film 46.

The manufacture of such a TFT is as follows.

The gate bus line and the gate electrode 44 are formed on the transparent insulating substrate 41 by the same method and material as in the first embodiment of the present invention. In this case as well, an excellent and good low defect insulating film is formed. can get.

The film thickness of the gate bus line and the gate electrode 44 at this time is preferably 1000 to 4000 angstroms.

The silicon thin film 42 is made of amorphous silicon or polycrystalline silicon, and is formed on the gate insulating film 43 in a region facing the gate electrode 44 by a low pressure CVD method, a plasma CVD method or the like. At this time, a high-quality film can be obtained by annealing the polycrystalline silicon. The film thickness of the silicon thin film 42 is preferably 2000 angstroms or less.

Next, the contact layer 45a and the contact layer 4
5b is formed.

First, SiN _{x is formed on} the central portion of the silicon thin film 42.
A channel protective film 47 made of, for example, is formed with a thickness of 1000 to 3000 angstroms.

Thereafter, from above the channel protection film 47, for example, an impurity of a group V element or its compound or an impurity of a group III element or its compound is ion-implanted over the entire surface of the silicon thin film 42 at an acceleration voltage of 1 kV to 100 kV. .

As a result, the region of the silicon thin film 42 in which the channel protective film 47 is formed, that is, the semiconductor layer 45c at the center is blocked by the channel protective film 47 and ion implantation is not performed, and the film when the silicon thin film 42 is formed is formed. The components remain as the semiconductor layer 45c, and impurities are implanted at a high concentration in each of the regions on both sides except the semiconductor layer 5c to form the contact layer 45a and the contact layer 45b.

The insulating film 43 is covered with the channel protective film 47, the contact layer 45a and the contact layer 45b.
An interlayer insulating film 46 is laminated on the entire surface of the substrate.

The thickness of the interlayer insulating film 46 is 2000 to 600.
The thickness should be 0 angstrom or more. The method and material are the same as in the case of the first embodiment of the present invention, and in this case as well, the interlayer insulating film 6 which is dense and has few defects and good film quality can be obtained.

A contact hole 51 penetrating the interlayer insulating film 46 to reach the contact layer 45a and a contact hole 52 penetrating the interlayer insulating film 46 to reach the contact layer 45b are formed.

The source electrode 48 is provided in the contact hole 51, and the drain electrode 49 is provided in the contact hole 52.
Simultaneously with the pattern formation of the source bus line 48 ',
It is formed using Al, Mo, Cr or the like.

Next, an ITO film having a thickness of 500 to 1000 angstrom is formed on the interlayer insulating film 46, and the pixel electrode 50 is formed in a predetermined region of each unit section surrounded by the source bus line 48 'and the gate bus line. Is patterned and connected to the drain electrode 49. Finally, the insulating film 46 'is patterned over the entire surface of the substrate.

The method and material are the same as in the case of the first embodiment of the present invention, and an insulating film 46 'having a dense and good quality with few defects can be obtained.

As a result, an active matrix substrate is manufactured.

Also according to the manufacturing method of this embodiment, it is possible to obtain the gate insulating film 43 and the interlayer insulating film 46 which are dense and have few defects in the film, excellent electric characteristics and high reliability.

[Fourth Embodiment] FIG. 6 is a sectional view of a TFT provided on an active matrix substrate according to a fourth embodiment of the present invention.

The TFT is formed by forming a gate electrode 64 branched from a gate bus line provided on a transparent insulating substrate 61 such as glass or quartz, and covering the gate electrode 64 over the entire surface of the substrate. Of the gate insulating film 63 and the gate electrode 64 in contact with the gate insulating film 63.
A silicon thin film 62 formed at a position facing
It has a channel protective film 67 laminated in contact with the central portion of the silicon thin film 62.

A channel protective film 67 of the silicon thin film 62.
A contact layer 65a and a contact layer 65b are laminated on each of both side portions except the central portion where is laminated so as to cover each end portion of the channel protective film 67.

The gate insulating film 6 is formed so as to cover the channel protective film 67, the contact layer 65a and the contact layer 65b.
An interlayer insulating film 66 is formed on the entire surface of the substrate in contact with the substrate 3.

At positions where the interlayer insulating film 66 covers the contact layer 65a, there are provided contact holes 71 which penetrate the interlayer insulating film 66 and reach the contact layer 65a, and at positions where the interlayer insulating film 66 covers the contact layer 65b. A contact hole 72 penetrating the interlayer insulating film 66 and reaching the contact layer 65b is formed.

The source electrode 68 branched from the source bus line 68 'is formed so as to fill the contact hole 71, and the end of the source electrode 68 is connected to the contact layer 65a. The drain electrode 69 is formed so as to fill the contact hole 72, and the end portion of the drain electrode 69 is connected to the contact layer 65b.

A pixel electrode 70 is laminated on the interlayer insulating film 66 in each of predetermined regions of each unit section surrounded by the source bus line 68 'and the gate bus line.

The pixel electrode 70 is connected to the drain electrode 69 at the end of the drain electrode 69 opposite to the side connected to the contact layer 65b.

Such a TFT is manufactured as follows.

A gate bus line and a gate electrode 64 are laminated on the transparent insulating substrate 61, a gate insulating film 63 is formed over the entire surface of the substrate so as to cover the gate bus line and the gate electrode 64, and the gate insulating film 63 is further formed. The material and method are the same as those in the case of the third embodiment of the present invention until the silicon thin film 62 is formed on the upper surface of the silicon thin film 62 in the region facing the gate electrode 64.

In the central region of the formed silicon thin film 62, a channel protection film 67 made of SiN _x or the like is formed at a thickness of 1000-1000.
The contact layer 65a and the contact layer 65b are respectively formed on the regions of the silicon thin film 62 excluding the channel protective film 67, which are formed to have a thickness of 3000 angstroms. The contact layer 65a and the contact layer 65b are made of amorphous silicon doped with an impurity serving as a donor or an acceptor, or polycrystalline silicon, and have a film thickness of 1000 to 3000 angstroms. The portion is laminated so as to cover the end portion of the channel protective film 67.

An interlayer insulating film 66 is formed on the entire surface of the substrate on the gate insulating film 63 so as to cover the contact layer 65a, the contact layer 65b and the channel protective film 67.

The method and material are the same as in the case of the first embodiment of the present invention, and in this case as well, the interlayer insulating film 66 which is dense and has few defects and good quality can be obtained.

A contact hole 71 penetrating the interlayer insulating film 66 to reach the contact layer 65a and a contact hole 72 penetrating the interlayer insulating film 66 to reach the contact layer 65b are formed, and the source electrode 68 is formed in the contact hole 71. Further, the drain electrode 69 is formed in the contact hole 72 by using Al, Mo, Cr or the like at the same time as the pattern formation of the source bus line 68 '.

Then, an ITO film having a thickness of 500 to 1000 angstrom is formed on the interlayer insulating film 66, and a pixel electrode is formed in a predetermined area of each unit section surrounded by the source bus line 68 'and the gate bus line. 70 is patterned and connected to the drain electrode 69.

As a result, an active matrix substrate is manufactured.

Also according to the manufacturing method of the present embodiment, it is possible to obtain the gate insulating film 63 and the interlayer insulating film 66 which are dense and have few defects in the film and have excellent electric characteristics and high reliability.

Furthermore, in the present embodiment, there is no need to provide an insulating film on the interlayer insulating film 66 as in the first embodiment, and the first
The productivity is improved as compared with the embodiment of.

[0111]

As described in detail above, according to the present invention,
A gate insulating film and an interlayer insulating film can be formed at a low temperature of 600 ° C. or lower, and on an inexpensive substrate such as glass,
It is possible to obtain a gate insulating film and an interlayer insulating film which are uniform over a large area and have high film quality. Based on the above, a good interface between the gate insulating film and the silicon thin film of the thin film transistor can be obtained, so that the electrical characteristics of the thin film transistor are improved.

From the above, a highly reliable active matrix substrate having excellent display characteristics can be obtained.

[Brief description of drawings]

FIG. 1 is a plan view showing a configuration of a unit pixel of an active matrix substrate of the present invention.

FIG. 2 is a sectional view of a TFT of an active matrix substrate according to the first embodiment of the present invention.

FIG. 3 is a sectional view of an intersection of a gate bus line and a source bus line of an active matrix substrate according to the present invention.

FIG. 4 is a sectional view of a TFT of an active matrix substrate according to a second embodiment of the present invention.

FIG. 5 is a sectional view of a TFT of an active matrix substrate according to a third embodiment of the present invention.

FIG. 6 is a sectional view of a TFT of an active matrix substrate according to a fourth embodiment of the present invention.

FIG. 7 shows T of an active matrix substrate in a conventional example.
Sectional drawing of FT.

[Explanation of symbols]

1 transparent insulating substrate 2 silicon thin film 3 gate insulating film 4 gate electrode 4'gate bus line 5a contact layer (TFT source) 5b contact layer (TFT drain) 5c semiconductor layer 6 interlayer insulating film 6'insulating film 7 channel protection Film 8 Source electrode 8'Source bus line 9 Drain electrode 10 Pixel electrode 11 and 12 Contact hole

Claims (10)

[Claims] 1. A plurality of signal wirings and a plurality of scanning wirings are arranged on a transparent insulating substrate so as to be orthogonal to each other with an interlayer insulating film interposed therebetween, and each adjacent signal wiring and each wiring. A pixel electrode for driving liquid crystal and a switching element for driving the pixel electrode are provided in respective regions surrounded by the scanning wiring, and the switching element includes a semiconductor layer and a gate electrode provided with an insulating film interposed therebetween. A method of manufacturing an active matrix substrate comprising a thin film transistor having: 1. The method of manufacturing an active matrix substrate, wherein the insulating film is formed by a CVD method by supplying an organosilane compound having an alkoxyl group. 2. The method for manufacturing an active matrix substrate according to claim 1, wherein the CVD method is a plasma CVD method. 3. The method of manufacturing an active matrix substrate according to claim 1, wherein the CVD method is a thermal CVD method, and ozone (O ₃ ) gas is supplied together with the organic silane compound. 4. The method for producing an active matrix substrate according to claim 1, wherein the CVD method is a photo-CVD method involving irradiation with an energy beam, and an oxidizing gas is supplied together with the organic silane compound. 5. The method for manufacturing an active matrix substrate according to claim 4, wherein the oxidizing gas is any one of oxygen (O ₂ ) gas, ozone (O ₃ ) gas and nitric oxide (NO ₂ ) gas. 6. A plurality of signal wirings and a plurality of scanning wirings are arranged on a transparent insulating substrate so as to be orthogonal to each other with an interlayer insulating film interposed therebetween, and each adjacent signal wiring and each wiring. A method for manufacturing an active matrix substrate having a pixel electrode for driving a liquid crystal and a switching element for driving the pixel electrode in each region surrounded by a scanning wiring, wherein the interlayer insulating film has an alkoxyl group. A method for manufacturing an active matrix substrate formed by a CVD method by supplying a silane compound. 7. The method for manufacturing an active matrix substrate according to claim 6, wherein the CVD method is a plasma CVD method. 8. The method of manufacturing an active matrix substrate according to claim 6, wherein the CVD method is a thermal CVD method, and ozone (O ₃ ) gas is supplied together with the organic silane compound. 9. The method for manufacturing an active matrix substrate according to claim 6, wherein the CVD method is an optical CVD method involving irradiation with an energy beam, and an oxidizing gas is supplied together with the organic silane compound. . 10. The oxidizing gas is oxygen (O ₂ ) gas,
The method for manufacturing an active matrix substrate according to claim 9, wherein the active matrix substrate is one of ozone (O ₃ ) gas and nitric oxide (NO ₂ ) gas.