KR100294777B1 - Thin film transistor and its manufacturing method - Google Patents

Abstract

The thin film transistor of the present invention includes a source and a drain region formed on the insulating base region; And a conductive layer connected to the source and drain regions. The conductive layer has a laminated structure of an Al-containing metal film and an N-containing Mo film.

Description

Thin film transistor and method of manufacturing the same

The present invention relates to a thin film transistor (hereinafter referred to as "TFT") and a method of manufacturing the same. In particular, the present invention relates to a manufacturing process of a TFT used as a switching element for selecting pixels in a liquid crystal display device (hereinafter referred to as "LCD") or as a driver element for driving an LCD.

In an LCD, an active matrix substrate is provided by a plurality of TFTs arranged in a matrix form, a plurality of pixel electrodes made of an indium tin oxide (ITO) film corresponding to one of the TFTs, and a conductive layer connected to the source and drain regions. do. As the conductive layer including the source and drain electrodes and the source and drain wiring (hereinafter referred to as "source / drain electrode wiring"), an Al thin film is used.

The Al film is patterned using a resist to function as a source / drain electrode in a substrate having the above-described configuration. When the resist is developed with a developing solution, the developing solution causes a battery reaction between the Al film and the ITO film, whereby the Al film is etched.

Etching can be prevented, for example, as follows. An insulating film is deposited on the source / drain electrode wiring formed by patterning the Al film. A contact hole is provided through the insulating film so as to electrically contact the source / train electrode wiring with the pixel electrode located on the electrode wiring. Thereafter, an ITO film is deposited on the insulating film. However, during the deposition of the ITO film, a part of the Al film exposed through the contact hole penetrating through the insulating film is oxidized by oxygen atmosphere in the vapor deposition apparatus. As a result, there arises a problem that no ohmic contact is obtained between the ITO film and the source / drain electrode wiring.

In order to solve the above problem, the source / drain electrode embodiment is a two-layer structure including an Al film and Mo (molybnium) deposited on the Al film. In this case, etching can be prevented, and ohmic contact between the ITO film and the source / drain electrode wiring can be obtained.

In addition, when the source / drain electrode wiring has a Mo / Al two-layer structure, and the Mo film is deposited on the Al film, it is possible to suppress the generation of Al bumps, that is, hillocks or whiskers. The movement of the Al film is prevented to improve the reliability of the electrode wiring.

In the case where the source / drain electrode wiring has a Mo / Al two-layer structure, the two layers can be deposited continuously. In addition, the two layers can be wet etched simultaneously using a mixed solution comprising phosphoric acid, nitric acid, acetic acid and water. The above-described problems such as etching can be solved without increasing the number of processes.

However, since the etching rates of the Al film and the Mo film are different from each other, a problem occurs in that the pattern of the Mo film is shifted with respect to the pattern of the Al film as a result of the wet etching. In other words, the wiring width of the pattern of the Mo film or the Al film is smaller than the others.

For example, as a result of the wet etching, the lower layer film 21 of the source / drain electrode wiring can be more etched in the lateral direction than the upper layer film 22 as shown in FIG. 6 (a). When another film 23 (e.g., an insulating film or a protective film) is formed on the source / drain electrode wiring, the cavity 24 is located near the interface between the lower layer 21 and the upper layer 22 of the source / drain electrode wiring. ) And then a crack 25. In the next process, acids and the like penetrate into the cavities 24 or cracks 25 and cause etching to the source / drain electrode wiring. Therefore, a problem such as disconnection of wiring occurs.

On the contrary, as a result of the wet etching, the upper layer film 22 of the source / drain electrode wiring is etched more in the lateral direction than the lower layer film 21. As a result, the wiring width of the upper layer 22 pattern becomes smaller than that of the lower layer 21, as shown in FIG. 6 (b). In this case, the range covered by the ITO film 26 over the contact hole 23a provided on the source / drain electrode wiring is incomplete. Therefore, its contact resistance is very high, and it is difficult to obtain good electrical conductivity between the ITO film 26 and the source / drain electrode wiring.

As shown in FIG. 6 (b), the underlayer film 21 of the source / drain electrode wiring can be exposed in the contact hole 23a provided on the source / drain electrode wiring. In this case, when the position of the mask pattern is displaced in the mask alignment process for etching the ITO film 26, the portion 27 of the source / drain electrode distribution may, for example, etch the ITO film 26. Is etched by an etching solution or other acid used in the next process.

Further, in view of the reliability (that is, the strength of the structure) of the Al film of the Mo / Al two-layer structure of the source drain electrode wiring, when the etching shift of the Al film lower layer 21 is large, the cover film of the source / drain electrode wiring is deteriorated. There may be a problem. On the other hand, when the etching shift of the Mo film upper layer 22 having a Mo / Al two-layer structure is large, a problem arises in that the heat-resistant property of the Al film is deteriorated.

Japanese Patent Laid-Open No. 6-104241 discloses a method for etching a two-layer structure that controls the thickness ratio of the laminated films to reduce the amount of side etching. According to experiments conducted by the inventors of the present invention, in the case of a Mo / Al two-layer structure, the wiring width of the Mo film is smaller than the thickness of the Al film regardless of the thickness ratio.

1 is a cross-sectional view showing the configuration of a TFT according to Embodiments 1 to 4 of the present invention.

2 (a) to 2 (c), 3 (a) to 3 (c), 4 (a) and 4 (b) are according to embodiments 1 to 4 of the present invention. Sectional drawing showing a method for manufacturing a TFT.

5 (a) to 5 (c) are cross-sectional views showing a method for manufacturing a TFT according to Embodiment 4 of the present invention.

6 (a) and 6 (b) illustrate problems with conventional double metal layer techniques.

7 is a graph showing the relationship between the flow rate ratio of N ₂ / Ar and the etching rate (nm / min) of the Mo film during the sputtering process of the Mo film.

8 is a graph showing the relationship between the flow rate ratio of N ₂ / Ar and the amount of shift of the Mo film (μm) with respect to the Al film during the sputtering process of the Mo film.

9 is a graph showing the relationship between the flow rate ratio of N ₂ / Ar and the specific resistance (μΩcm) of the Mo film during the sputtering process of the Mo film.

The thin film transistor of the present invention includes a source and a drain region formed on the insulating base region; And a conductive layer connected to the source and drain regions, wherein the conductive layer has a laminated structure of an Al-containing metal film and an N-containing Mo film.

In one embodiment of the invention, the N-containing Mo film has a specific resistance in the range of about 65 to 195 μΩcm.

The thin film transistor of the present invention includes forming a two-layer structure of an Al-containing metal film and an N-containing Mo film, wherein the conductive layer is connected to a source and a drain region formed on an insulating base region, and the Mo film is N Deposited in a gas phase containing ₂ gases or NH ₃ gas.

In another embodiment of the present invention, the Mo film is deposited by sputtering in a gas phase including a mixed gas of Ar gas and N ₂ gas.

In another embodiment of the present invention, the Mo film can be deposited by the CVD method using a gas containing N ₂ or NH ₃ .

A method for manufacturing a thin film transistor of the present invention includes forming a conductive layer laminated with two layers of an Al-containing metal film and an N-containing Mo film, wherein the conductive layer is formed of a source and a drain formed on an insulating base region. Connected to the region, an N-containing Mo film is formed by introducing nitrogen into the film formed by Mo vapor deposition.

In another embodiment of the present invention, nitrogen is introduced into the film by annealing the film formed by Mo deposition in a gas phase containing N ₂ gas or NH ₃ gas.

In another embodiment of the present invention, nitrogen is introduced into the film formed by Mo deposition by an ion implantation method.

The two-layer conductive structure of the present invention includes an Al-containing conductive layer and an N-containing Mo layer connected to the Al-containing conductive layer, wherein the Al-containing conductive layer and the N-containing Mo layer have almost the same etching rate. .

The method for producing a two-layer conductive structure of the present invention includes forming an Al-containing conductive layer; Forming an N-containing Mo layer connected to the Al-containing conductive layer; And etching the Al-containing conductive layer and the N-containing layer, wherein the etch rates of the Al-containing conductive layer and the N-containing layer are about the same.

Hereinafter, the function of the present invention will be described.

According to the present invention, the conductive layer connected to the source and drain regions has a two-layer structure of an Al-containing metal film and an N (nitrogen) -containing Mo film. In such a case, the etching rate of the Mo film becomes almost similar to that of the Al containing metal film. Therefore, the conductive layer of the two-layer structure can be etched in a state in which the shift amount of the Mo film is minimized relative to the Al film.

Accordingly, the present invention described below provides (1) a TFT which forms a conductive layer which functions as a source / drain wiring in a state where the Mo / Al two-layer structure is etched and the shift amount of the Mo film with respect to the Al film is minimized. And (2) an advantage of providing a method for manufacturing the TFT.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

First, the basic principle of the present invention will be described.

According to the present invention, the Mo film is deposited on or under the Al-containing metal film by sputtering in a mixed gas containing Ar (argon) gas and N ₂ gas. At this time, the flow rate of the N ₂ gas is about 10 to 70% of the inflow rate of Ar gas. Thus, a conductive layer for forming source / drain electrode wirings is formed.

Further, according to the present invention, the Mo film is deposited on or under the Al-containing metal film by the CVD method in a gas phase containing N ₂ gas or NH ₃ gas.

According to the present invention, after the Mo film is deposited on or below the Al-containing metal film, nitrogen has an ion implantation process in a gas phase containing a N ₂ gas or NH ₃ gas, having a processing temperature in the range of about 450 to 600 ° C. Or it is introduced into the Mo film through an annealing process.

According to this treatment process, an N-containing Mo film having a specific resistance in the range of about 65 to 195 μΩcm can be deposited. Therefore, the amount by which the Mo film is shifted with respect to the Al film can be minimized as a result of the wet etching process.

Specifically, as can be seen in FIG. 7, as the flow rate ratio of N ₂ / Ar increases during Mo film deposition, the etching rate of the Mo film decreases, i.e., close to the etching rate of the Al film. Therefore, the amount by which the Mo film is shifted with respect to the Al film as a result of the wet etching can be minimized.

Hereinafter, during the deposition of the Mo film, the amount of change in the amount by which the Mo film upper layer is shifted with respect to the Al alloy metal film lower layer as a result of the wet etching by the flow rate ratio of N ₂ / Ar will be described with reference to the graph of FIG. 8.

The x-axis of the graph shown in FIG. 8 represents the flow rate ratio of N ₂ / Ar during Mo film deposition, while the y-axis shows the width difference of the measured wiring between the Al film and the Mo film on the Al film after the wet etching process. 1/2, i.e., the shift amount (µm) of the Mo film relative to the Al film on one side surface. Here, the thickness of the Al alloy metal film is 500 nm, while the thickness of the Mo film is about 150 nm. As can be seen from FIG. 8, as the N ₂ / Ar flow rate increases during Mo film sputtering, the amount of shift of the Mo film relative to the Al film decreases.

Japanese Laid-Open Patent Publication No. 6-104241 discloses a method of controlling the shift amount of an Mo film having a Mo / Al two-layer structure with respect to an Al film by controlling the thickness ratio of two films. On the other hand, in comparison with the above-described method, the present invention controls the etching rate of the Mo film and the Al film (so that the two etching rates are close to each other), so that a larger process margin (i.e., freedom in the process) is achieved. Fig. 1) becomes possible.

9 is a graph showing the relationship between the N ₂ / Ar flow rate ratio (indicated by the x-axis) and the specific resistance (μΩcm) (indicated by the y-axis) of the Mo film during sputtering of the Mo film. As can be seen in FIG. 9, as the N ₂ / Ar flow rate increases during the Mo film sputtering process, the resistivity of the Mo film also increases. However, since the source / drain wiring has an Al / Mo two-layer structure and aluminum is a metal having a low resistance, the resistance of the source / drain wiring is kept small overall.

For example, an Mo film is deposited in a gas phase with an Ar gas inflow rate of about 20 sccm and an N ₂ gas inflow rate of about 10 sccm, and the resistivity of the Mo film is very high, reaching about 154 μΩcm. However, the source / drain wiring has a two-layer structure of the Mo film and the Al film thus grown, and when the thickness of the Mo film is about 150 nm and the thickness of the Al film is about 500 nm, the specific resistivity of the entire two-layer structure is generally treated. Compared with the resistance of the two-layer structure of the Al film and the Al film, it increases by an appropriate percentage of about 10 to 15%.

Therefore, by forming the source / drain electrode wirings to have a two-layer structure of N-induced Mo film and Al film, it is possible to minimize the amount of shifting of the Mo film relative to the Al film when the Mo film and the Al film are etched simultaneously. . Therefore, while suppressing the substantial increase in the wiring resistance, it is possible to enhance the reliability of the source / drain electrode wiring.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following examples. On the other hand, the drawings used in connection with the following embodiments are cross-sectional views schematically showing TFTs as switching elements that constitute an essential part of the pixels of the liquid crystal display panel.

Example 1

1 is a cross-sectional view showing the configuration of a TFT according to Embodiment 1 of the present invention. 2 (a) to 2 (c), 3 (a) to 3 (c), 4 (a) and 4 (b) are TFTs according to Embodiment 1 of the present invention. Is a cross-sectional view showing a method for manufacturing a semiconductor, and each figure shows a cross section of a TFT after each process step for manufacturing a TFT.

In FIG. 1, reference numeral 100 denotes a TFT according to Embodiment 1 of the present invention. The SiO ₂ layer 2 is provided on the glass substrate 1. The semiconductor layer 3 is provided on the SiO ₂ layer 2. The gate electrode 5 is provided on the central region of the semiconductor layer 3 and the gate insulating film 4. End portions of the semiconductor layer 3 form a source region 3a and a drain region 3b. This part is located directly under the gate electrode 5, and the central part of the side of the semiconductor layer 3 is located therebetween, and is located laterally spaced apart from each other. The semiconductor layer 3 and the gate electrode 5 are covered with the interlayer insulating film 6. The source / drain electrode wiring 10 is provided on the interlayer insulating film 6 and is electrically connected to the source and drain regions through the contact holes 7.

The source / drain electrode wiring 10 has a two-layer structure of the lower layer 8 of the Al alloy metal film and the upper layer 9 of the N-containing Mo film. The surface of the source / drain electrode wiring 10 and the interlayer insulating film 7 are covered with the surface protective layer 11. The pixel electrode 13 is provided on the surface protective layer 11. The pixel electrode 13 penetrates through the surface protection layer 11 and is electrically connected to the source / drain electrode wiring 10 through the contact hole 12.

Hereinafter, a method for manufacturing a TFT will be described.

As shown in FIG. 2 (a), the SiO ₂ layer 2 is deposited on the glass substrate 1 to have a thickness of about 100 nm, thereby preventing scattering of impurities from the glass engine 1. The silicon layer is about 50 nm thick and processed to form the semiconductor layer 3.

Next, as shown in FIG. 2 (b), another SiO ₂ film (which forms the gate insulating film 4) is deposited over the entire surface of the substrate. A metal having low resistance and excellent thermal resistance is deposited on the gate insulating film 4 to correspond to a predetermined region of the semiconductor layer 3 located below the gate insulating film 4 and patterned to form the gate electrode 5. do.

Subsequently, as shown in FIG. 2 (c), n ⁺ ion implantation for forming the source region 3a and the drain region 3b uses a mixed gas containing PH ₃ gas and H ₂ gas in the gas phase. And an acceleration voltage of 80 keV and the amount thereof is about 5E14 / cm 2.

Thereafter, the semiconductor layer 3 is activated by laser irradiation having an energy intensity of about 350 mj / cm 2 using an Xe-Cl excimer laser at room temperature in an air vapor phase. Thereafter, an interlayer insulating film 6 is deposited on the entire surface of the substrate. Contact holes 7 corresponding to the source and drain regions and other contact holes (not shown) corresponding to the gate electrode 5 are then provided (see also third (a)).

Next, as shown in FIG. 3 (b), the Al alloy metal film 8 is grown to a thickness of about 500 nm in a gas phase with an Ar gas inflow rate of about 50 ccm and a gas pressure of about 3.0 x 10 ^-3 Torr. The Mo film 9 has a thickness of about 150 nm on the Al film 8 in a gas phase having an Ar gas inflow rate of about 20 sccm, an N ₂ gas inflow rate of about 10 sccm, and a gas pressure of about 3.0 x 10 ^-3 Torr. It is grown to be thick. Al film 8 and Mo film 9 are continuously deposited by sputtering. Although the inflow rate of N ₂ gas is not limited to the above-mentioned value, it is preferable that it is about 10 to 70% of the inflow rate of Ar gas. Thereafter, the Al film and the Mo film are patterned by wet etching to form the source / drain electrode wiring 10.

Wet etching is performed by dipping the layer into a mixed solution containing phosphoric acid, nitric acid, acetic acid, and water. Since the Mo film and the Al film can be etched using this etching solution, these films can be etched simultaneously in the same etching bath. In other words, the two films can be etched in a single process.

The Mo film sputtered in the gas phase containing no N ₂ gas has an etching rate higher than that of the Al film. Therefore, as the Al film becomes thicker, the amount by which the Mo film is etched increases, thereby increasing the amount of shift of the Mo film relative to the Al film.

On the other hand, according to the present invention, the Mo film forming the Mo / Al two-layer structure together with the Al film can be deposited in the gas phase containing N ₂ gas. Thus, the amount by which the Mo film is shifted with respect to the Al film as a result of the wet etching process can be minimized.

Another method for forming an N-inflow Mo film is Mo deposited with nitrogen under conditions where the inflow rate of N ₂ gas is about 10 sccm, the acceleration voltage is 80 keV, the RF power is about 180 W and the amount is about 1.8E15 / cm 2. Ion implanting the membrane; And annealing the deposited Mo film in the gas phase containing N ₂ gas. This method can be applied to the manufacturing steps for the above-described TFT having two-layer source / drain electrode wiring.

Therefore, the source / drain electrode wiring 10 having the Mo / Al two-layer structure is formed so that the amount of the Mo film shifts with respect to the Al film as a result of the wet etching process as shown in FIG. 3 (c) is minimized. .

Thereafter, as shown in FIG. 4 (a), the contact hole 12 penetrates through the protective layer 11 to obtain electrical conductivity between the source / drain electrode wiring 10 and the subsequently formed pixel electrode 13. After provided, the protective layer 11 is deposited over the entire surface of the substrate to cover the source / drain electrode wiring 10.

As a result, as shown in FIG. 4 (b), an ITO film is deposited on the protective layer 11 and then patterned to form the pixel electrode 13. Thus, the manufacturing of the TFT 100 is completed.

Example 2

Hereinafter, a TFT and a method of manufacturing the same according to Embodiment 2 of the present invention will be described.

In Example 2, the same process as shown in Figs. 2 (a) to 2 (c), and described in Example 1 is carried out, and the contact hole 7 is shown in Fig. 3 (a). As shown, it is provided through the interlayer insulating film 6 and the gate insulating film 4. Subsequently, as shown in FIG. 3 (b), an Al alloy metal film 8 is deposited on the interlayer insulating film 6 to a thickness of about 500 nm. The Mo film 9 is made of Al film by CVD under the condition that the inflow rate of MoF ₆ gas is about 70 sccm, the inflow rate of N ₂ gas is about 500 sccm, the gas pressure is about 30 Torr and the process temperature is about 430 ° C. 8) deposited to a thickness of about 150 nm to form an N-containing Mo film 9. In this step, NH ₃ gas may be used instead of N ₂ gas.

Next, as shown in FIG. 3 (c), the Al film 8 and the Mo film 9 are patterned by wet etching, whereby Mo / in a state in which the shift amount of the Mo film with respect to the Al film is minimized. A source / drain electrode wiring 10 having an Al two-layer structure is formed.

The following steps for completing the manufacture of the TFT 100 (see FIG. 1) of Embodiment 2 are the same as those described in Embodiment 1 and shown in FIGS. 4 (a) and 4 (b).

Example 3

Hereinafter, a TFT and a method of manufacturing the same according to Embodiment 3 of the present invention will be described.

In Example 3, the same process as shown in Figs. 2 (a) to 2 (c) and described in Example 1 is performed, and the contact holes 7 are as shown in Fig. 3 (a). Likewise provided through the interlayer insulating film 6 and the gate insulating film (4). Then, as shown in FIG. 3 (b), the Al alloy metal film 8 has an interlayer insulating film having a thickness of about 500 nm in a gas phase in which Ar gas inflow rate is about 50 sccm and gas pressure is about 0.4 Pascal. 6) grow on phase. The Mo film 9 is grown on the Al film 8 to a thickness of about 150 nm in a gas phase with an Ar gas inflow rate of about 50 sccm and a gas pressure of about 0.4 Pascals. In this step, the two layers are continuously deposited by sputtering or the like.

The deposited Mo film is subjected to a lamp annealing process under conditions in which the inflow rate of N ₂ gas is about 1000 sccm, the gas pressure is about 10 Torr, and the process temperature is about 500 ° C. for about 2 minutes. In this way, nitrogen enters the Mo film. In this step, NH ₃ gas may be used instead of N ₂ gas. Although the process temperature is not limited to 500 ° C., it is preferred to be in the range of about 450 to 600 ° C.

After the two-layer structure of the N-containing Mo film and the Al film is formed as shown in FIG. 3 (b), the two layers are patterned by wet etching, thereby as shown in FIG. 3 (c). A source / drain electrode wiring 10 having a Mo / Al two-layer structure is formed in a state in which the shift amount of Mo with respect to the Al film is minimized.

The following process of completing the manufacture of the TFT 100 (see FIG. 1) of Example 3 is described in Example 1, and is the same as that shown in FIGS. 4 (a) and 4 (b).

Example 4

In the following, a TFT and a method of manufacturing the same according to Embodiment 4 of the present invention will be described.

In Example 4, the same process as shown in Figs. 2 (a) to 2 (c) is performed, and the same as that described in Example 1 is performed, and the contact hole 7 is shown in Fig. 5 (a). It is provided through the interlayer insulating film 6 and the gate insulating film 4. Thereafter, as shown in FIG. 5 (b), the Al film or the Al alloy metal film 8 has a thickness of about 500 nm in a gas phase in which the inflow rate of Ar gas is about 50 sccm and the gas pressure is about 0.4 Pascal. It is deposited on the interlayer insulating layer 6. The Mo film 14 is deposited on the Al film 8 at a thickness of about 150 nm in a gas phase with an Ar gas inflow rate of about 50 sccm and a gas pressure of about 0.4 Pascals. In this step, both layers are deposited successively by sputtering.

Thereafter, the deposited pure Mo film 14 containing only Mo was subjected to N ₂ gas inflow rate of about 10 sccm, acceleration voltage of 80 keV, RF power of about 180 W, and the amount of about 1.8E15 / cm 2. As shown in FIG. 5 (c), ion implantation is performed together with nitrogen. Nitrogen flows into the pure Mo film 14, and an N-containing Mo film 9 is formed.

After the N-containing Mo film 9 and the Al film or the Al alloy metal film 8 are formed as shown in FIG. 5 (c), the two layers are patterned by wet etching, so as to provide the Al film. In a state where the shift of the Mo film is minimized, as shown in FIG. 3 (c), the source / drain electrode wiring 10 having a Mo / Al two-layer structure is formed.

The following steps for completing the fabrication of the TFT 100 (see FIG. 1) of Embodiment 4 are described in Embodiment 1, and are the same as those shown in FIGS. 4 (a) and 4 (b).

Although the intrinsic value of the specific resistance of the Mo film is not given above, the specific resistance of the Mo film is set within the range of about 65 to 195 μΩcm in each of the above-described embodiments. By using an N-containing Mo film having a specific resistance within this range, it is possible to minimize the amount of the Mo film shifting with respect to the Al film as a result of the wet etching process.

In the above-described embodiment, the source / drain electrode wiring may have a two-layer structure in which the Mo film is deposited on the Al film, and the source / drain electrode wiring may have a two-layer structure in which the Al film is deposited on the Mo film according to a specific application. . In such a case, the N-containing Mo film can be used to minimize the amount of the Mo film shifting with respect to the Al film as a result of the wet etching process.

As described above, according to the present invention, the source / drain electrode wiring on the LCD substrate on which a plurality of TFTs are arranged in a matrix form has a two-layer structure of an Al-containing metal film and an Mo film. Therefore, it is possible to improve the reliability of the source / drain electrode wirings, and it is also possible to improve the production yield of the manufacturing process by using such TFTs.

In addition, the Mo film is deposited in a gas phase containing N ₂ gas. Thus, the two-layer wiring of the Al film and the Mo film is simultaneously patterned by wet etching, and a high precision delicate pattern process of manufacturing the source / drain electrode wiring with the shift amount of the Mo film minimized with respect to the Al film can be performed. have.

Various modifications will be apparent to and will be readily made by those skilled in the art without departing from the scope and spirit of the invention. Therefore, the claims of the present invention are not limited to the above description, and the claims should be construed broadly.

Claims (14)

A source and drain region formed over the insulating base region; And a conductive layer connected to the source and drain regions, wherein the conductive layer has a laminated structure of an Al-containing metal film and an N-containing Mo film, and the N-containing Mo film is about 65 to 195 μΩcm Thin film transistors having a specific resistance in the range. Forming a conductive layer of a two-layer structure of an Al-containing metal film and an N-containing Mo film, wherein the conductive layer is connected to a source and a drain region formed on an insulating base region. And the N-containing Mo film is deposited by sputtering in an atmosphere containing a mixed gas of Ar gas and N ₂ gas, and the flow rate of N ₂ is about 10 to 70% of the flow rate of Ar gas. Forming a conductive layer of a two-layer structure of an Al-containing metal film and an N-containing Mo film, wherein the conductive layer is connected to a source and a drain region formed on an insulating base region. The N-containing Mo film is deposited by a CVD method using a gas containing N ₂ or NH ₃ , further comprising simultaneously etching the Mo film and the Al-containing metal film in the same etching bath. Way. Forming a conductive layer of a two-layer structure of an Al-containing metal film and an N-containing Mo film, wherein the conductive layer is connected to a source and a drain region formed on an insulating base region. The N-containing Mo film is formed by annealing a film formed by Mo deposition in an atmosphere containing N ₂ gas or NH ₃ gas, and further simultaneously etching the Mo film and the Al-containing metal film in the same etching bath. Thin film transistor manufacturing method comprising. Forming a conductive layer of a two-layer structure of an Al-containing metal film and an N-containing Mo film, wherein the conductive layer is connected to a source and a drain region formed on an insulating base region. And the N-containing Mo film is formed by ion implantation into a film formed by Mo deposition, further comprising simultaneously etching the Mo film and the Al-containing metal film in the same etching bath. Forming an Al-containing conductive layer; Forming an N-containing Mo layer connected to the Al-containing conductive layer; And etching the Al-containing conductive layer and the N-containing layer, wherein the etching rates of the Al-containing conductive layer and the N-containing layer are substantially the same. Manufacturing method. The method for producing a two-layer conductive structure according to claim 6, wherein the step of forming an N-containing Mo film is performed prior to the step of etching the Al-containing conductive layer and the N-containing Mo layer. A method of manufacturing a thin film transistor, comprising: forming a semiconductor layer on an insulating base region; Forming a gate electrode insulated from a portion of the semiconductor layer; Forming a source and a drain region in the semiconductor layer, wherein the source and drain regions are spaced apart from each other by a portion of the semiconductor layer from which the gate electrode is insulated; Forming an interlayer insulating film covering the gate electrode and the source and drain regions; Forming a conductive layer having a two-layer structure in contact with the source and drain regions through a contact hole formed in the interlayer insulating layer, wherein the conductive layer of the two-layer structure includes an aluminum-containing conductive film and a nitrogen-containing molybdenum film ; And patterning the aluminum-containing conductive film and the nitrogen-containing molybdenum film of the two-layered conductive layer in a single etching process to form a source / drain electrode. The method of claim 8, wherein the aluminum-containing conductive film and the nitrogen-containing molybdenum film are patterned by etching in the same etching bath. The method of claim 8, wherein the nitrogen-containing molybdenum film is formed by sputtering in an atmosphere containing a mixed gas of Ar gas and N ₂ gas. The method of claim 8, wherein the nitrogen-containing molybdenum film is deposited by chemical vapor deposition using a gas containing N ₂ or NH ₃ . The method of claim 8, wherein the nitrogen-containing molybdenum film is formed by annealing a film formed by molybdenum deposition in an atmosphere containing N ₂ gas or NH ₃ gas. 9. The method of claim 8, wherein the N-containing molybdenum film is formed by ion implantation into a film formed by molybdenum deposition. Forming a conductive layer of a two-layer structure of an Al-containing metal film and an N-containing Mo film, wherein the conductive layer is connected to a source and a drain region formed on an insulating base region. The N-containing Mo film is deposited by sputtering in an atmosphere containing a mixed gas of Ar gas and N ₂ gas, and the flow rate of N ₂ is about 10 to 70% of the flow rate of Ar gas, and the Mo in the same etching bath. And simultaneously etching the film and the Al-containing metal film.