JP3744293B2 - Electro-optical device manufacturing method and electro-optical device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The technical field of the present invention belongs to a manufacturing method of an electro-optical device and a technical field of the electro-optical device, and particularly to a manufacturing method of a capacitor electrode that increases a storage capacity without increasing a formation area of the capacitor electrode.
[0002]
[Prior art]
Conventionally, an electro-optical device, such as a liquid crystal device, is configured by sandwiching a liquid crystal layer between an array substrate and a counter substrate. The array substrate includes a plurality of scanning lines and data lines crossing each other, a plurality of thin film transistors (hereinafter referred to as TFTs) as switching elements corresponding to each of these intersections, and pixels electrically connected to the thin film transistors. The electrode is arranged on the substrate. On the other hand, the counter substrate is configured by disposing a counter electrode on the substrate. In a liquid crystal device, display is performed using an optical change of a liquid crystal layer due to a potential difference between a counter electrode and a pixel electrode.
[0003]
In such a liquid crystal device, when a scanning signal is supplied to the gate electrode of the TFT via the scanning line, the TFT is turned on, and an image signal is supplied to the pixel electrode via the data line. A storage capacitor is formed in parallel with the liquid crystal capacitor so that the voltage of the image signal supplied to the pixel electrode is maintained even when the TFT is turned off. The storage capacitor is formed, for example, from a capacitor electrode in which a part of the semiconductor layer of the TFT is extended, and a capacitor line disposed opposite to the capacitor electrode via an insulating film. The capacitor line is formed, for example, in the same layer as the scanning line, and is disposed substantially parallel to the scanning line.
[0004]
[Problems to be solved by the invention]
In this type of electro-optical device, there is a strong demand for a high-quality display image. For this purpose, it is extremely important to increase the definition of the image display area or to reduce the pixel pitch and increase the pixel aperture ratio.
[0005]
However, as the pixel pitch becomes finer, the size of the electrode and the width of the wiring are limited by the production technology, so the ratio of these wirings and electrodes to the image display area is relatively increased. There is a problem that the pixel aperture ratio becomes low. Furthermore, when the pixel pitch is miniaturized as described above, it becomes difficult to make the above-mentioned storage capacity that must be built in a limited substrate region sufficiently large.
[0006]
The present invention has been made in view of the above-described problems, and provides a method for manufacturing a capacitor electrode that increases the storage capacity without increasing the area of the capacitor electrode that forms the storage capacitor. Is an issue.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, a method of manufacturing an electro-optical device according to the present invention includes a pixel electrode, and a first capacitor electrode and a second capacitor electrode provided via an insulating film corresponding to the pixel electrode. In the method of manufacturing the electro-optical device disposed on the substrate, the first capacitor electrode or the second capacitor electrode includes a step of forming a polysilicon film on the substrate, and a temperature of 860 ° C. or higher. POCl_ThreeAnd a step of diffusing P into the polysilicon film using a diffusion source as a diffusion source.
[0008]
According to such a configuration of the present invention, POCl at a temperature of 860 ° C. or higher._ThreeThrough the step of diffusing P into the polysilicon film using as a diffusion source, a polysilicon film having a roughened film surface can be obtained. Therefore, when the first capacitor electrode and the second capacitor electrode are arranged via the insulating film to form a storage capacitor, a polysilicon film having a roughened film surface is formed on at least one capacitor electrode. By using it, the surface of the capacitor electrode in contact with the insulating film is roughened, so that the surface area of the capacitor electrode involved in forming the storage capacitor can be increased as compared with the case of a flat surface. As a result, the storage capacity can be increased. As a result, a large storage capacitor can be obtained even when the area of the capacitor electrode in the substrate is small, and an electro-optical device having a high pixel aperture ratio can be obtained.
[0009]
According to another electro-optical device manufacturing method of the present invention, a pixel electrode, a first capacitor electrode and a second capacitor electrode provided on a substrate via an insulating film corresponding to the pixel electrode, In the method of manufacturing the electro-optical device, the first capacitor electrode or the second capacitor electrode includes a step of forming a polysilicon film on the substrate, and a phosphor oxide on the polysilicon film. And a step of diffusing P in the phosphor oxide into the polysilicon film at a temperature of 860 ° C. or higher.
[0010]
According to such a configuration of the present invention, a polysilicon film having a roughened film surface is obtained by performing a step of diffusing P in the phosphor oxide into the polysilicon film at a temperature of 860 ° C. or higher. Obtainable. Therefore, when the first capacitor electrode and the second capacitor electrode are arranged via the insulating film to form a storage capacitor, a polysilicon film having a roughened film surface is formed on at least one capacitor electrode. By using it, the surface of the capacitor electrode in contact with the insulating film is roughened, so that the surface area of the capacitor electrode involved in forming the storage capacitor can be increased as compared with the case of a flat surface. As a result, the storage capacity can be increased. As a result, a large storage capacitor can be obtained even when the area of the capacitor electrode in the substrate is small, and an electro-optical device having a high pixel aperture ratio can be obtained.
[0011]
The film made of phosphorous oxide is POCl._ThreeIt can be formed by supplying vapor with a diffusion source on the polysilicon film.
[0012]
Furthermore, a natural oxide film having a thickness of 10 nm or less is formed on the surface of the polysilicon film. By adopting such a configuration, even when the surface of the polysilicon film is naturally oxidized and a natural oxide film is formed, P can be efficiently incorporated into the polysilicon film by reducing the film thickness to 10 nm or less. Can diffuse.
[0013]
Further, the diffusion of P into the polysilicon film is performed at a temperature of 900 ° C. or higher. With such a configuration, there is an effect that the storage capacity can be further increased.
[0014]
Further, the diffusion is performed in a batch type diffusion furnace. With such a configuration, it is possible to process a plurality of substrates at once and to improve the throughput.
[0015]
Further, on the substrate, scanning lines and data lines arranged to cross each other, and each of the intersections are electrically connected to the pixel electrode, and are provided via the scanning lines and the insulating film. A switching element having a semiconductor layer, wherein the first capacitor electrode is formed by extending the semiconductor layer, and the second capacitor electrode is in the same layer as the scanning line, and substantially It is characterized by being formed in parallel. The scan line and the second capacitor electrode may be formed by diffusing the P in the polysilicon film. As described above, the first capacitor electrode can be formed by extending the semiconductor layer constituting the switching element, and the second capacitor electrode can be formed in the same layer as the scanning line and substantially in parallel. As a result, the storage capacitor is formed by the semiconductor layer and the capacitor line as the second capacitor electrode through the insulating film. In addition, a polysilicon film having a roughened surface can be used as the scanning line and the second capacitor electrode.
[0016]
The electro-optical device of the present invention is manufactured by the above-described method for manufacturing an electro-optical device. According to such a configuration, an electro-optical device having a high pixel aperture ratio that can be applied to high definition can be obtained.
[0017]
According to another electro-optical device of the invention, a pixel electrode, and a first capacitor electrode and a second capacitor electrode provided via an insulating film corresponding to the pixel electrode are disposed on a substrate. In the optical device, a surface of the first capacitor electrode or the second capacitor electrode that is in contact with the insulating film is roughened so that a surface roughness Ra is 0.2 μm or more and 0.5 μm or less. It is characterized by.
[0018]
According to such a configuration of the present invention, when the first capacitor electrode and the second capacitor electrode are arranged via the insulating film to form the storage capacitor, the film surface is rough on at least one of the capacitor electrodes. By using the surfaced electrode, the surface of the capacitor electrode in contact with the insulating film is roughened, so that the surface area of the capacitor electrode involved in the formation of the storage capacitor can be reduced compared to the flat surface. It can be taken big. As a result, the storage capacity can be increased. As a result, a large storage capacitor can be obtained even when the area of the capacitor electrode in the substrate is small, and an electro-optical device having a high pixel aperture ratio can be obtained. Here, the surface roughness may be 0.2 μm or more and 0.5 μm or less. By setting the thickness to 0.2 μm or more, the storage capacity can be reliably increased, and by setting the thickness to 0.5 μm or less, the storage capacity can be reliably increased.
[0019]
The first capacitor electrode or the second capacitor electrode having the roughened surface has a porous film quality. As described above, a porous film-like electrode can be used as the capacitor electrode, whereby an electrode having a roughened surface can be obtained.
[0020]
The first capacitor electrode or the second capacitor electrode having the roughened surface may be a polysilicon film in which P is diffused.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings, taking a liquid crystal device as an electro-optical device as an example.
[0022]
(Structure of this embodiment of electro-optical device)
A configuration of a liquid crystal device as an electro-optical device according to the present invention will be described with reference to FIGS. FIG. 1 is an equivalent circuit of various elements and wirings in a plurality of pixels formed in a matrix that constitutes an image display area of the liquid crystal device, and FIG. 2 is a data line, a scanning line, a pixel electrode, a light shielding film, and the like. 3 is a plan view of a plurality of adjacent pixel groups of a TFT array substrate as a switching element substrate on which is formed, and FIG. 3 is a cross-sectional view taken along line AA ′ of FIG. In FIG. 3, the scale of each layer and each member is different in order to make each layer and each member recognizable on the drawing.
[0023]
In FIG. 1, TFTs 30 for controlling the pixel electrodes 9a are respectively formed in a plurality of pixels arranged in a matrix constituting the image display area of the liquid crystal device in this embodiment, and an image signal is supplied. The data line 6 a to be connected is electrically connected to the source of the TFT 30. The image signals S1, S2,..., Sn written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each group to a plurality of adjacent data lines 6a. good. Further, the scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2,..., Gm are applied to the scanning line 3a in a pulse-sequential manner in this order at a predetermined timing. It is configured. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the image signal S1, S2,..., Sn supplied from the data line 6a is obtained by closing the switch of the TFT 30 as a switching element for a certain period. Write at a predetermined timing. Image signals S1, S2,..., Sn written to the liquid crystal via the pixel electrode 9a are held for a certain period with a counter electrode (described later) formed on a counter substrate (described later). . The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gradation display. Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode.
[0024]
In FIG. 2, on the TFT array substrate of the liquid crystal device, a plurality of transparent pixel electrodes 9a (outlined by dotted line portions 9a ′) are provided in a matrix, and the vertical and horizontal boundaries of the pixel electrodes 9a are provided. A data line 6a, a scanning line 3a, and a capacitor line 3b are provided along each line. The data line 6a is electrically connected to a source region to be described later in the semiconductor layer 1a made of a polysilicon film or the like through the contact hole 5, and the pixel electrode 9a is in a region indicated by a diagonal line rising to the right in the drawing. The conductive layer 80 (hereinafter referred to as a barrier layer) that is formed and functions as a buffer is relayed to the drain region to be described later in the semiconductor layer 1a via the first contact hole 8a and the second contact hole 8b. Electrical connection. In addition, the scanning line 3a is disposed so as to face the channel region 1a 'in the semiconductor layer 1a, and the scanning line 3a functions as a gate electrode. As described above, the TFT 30 in which the scanning line 3a is arranged to face the channel region 1a 'as the gate electrode is provided at each intersection of the scanning line 3a and the data line 6a. Capacitor line 3b has a main line portion extending substantially linearly along scanning line 3a, and a protruding portion protruding upward (in the drawing, upward) along data line 6a from a location intersecting data line 6a. . These scanning lines 3a and capacitance lines 3b are made of, for example, a polysilicon layer into which P ions, which are group V elements, are diffused, and the surfaces thereof are roughened.
[0025]
Further, the first light shielding film 11a is provided so as to pass below the scanning line 3a, the capacitor line 3b, and the TFT 30. More specifically, in FIG. 2, each of the first light shielding films 11a is formed in a stripe shape along the scanning line 3a, and a portion intersecting with the data line 6a is formed wide in the lower part in the figure. These wide portions are provided at positions covering channel regions 1a ′ of the respective TFTs as viewed from the TFT array substrate side.
[0026]
Next, as shown in the cross-sectional view of FIG. 3, the liquid crystal device 62 includes a TFT array substrate 60 and a counter substrate 61 disposed to face the TFT array substrate 60. The substrate 10 of the TFT array substrate 60 is a quartz substrate, for example, and the substrate 20 of the counter substrate 61 is a glass substrate or a quartz substrate, for example.
[0027]
In the TFT array substrate 60, a pixel electrode 9a is provided on the substrate 10, and an alignment film 16 subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9a. The pixel electrode 9a is made of a transparent conductive thin film such as an ITO (Indium Tin Oxide) film. The alignment film 16 is made of an organic thin film such as a polyimide thin film. On the other hand, the counter substrate 61 is provided with, for example, a counter electrode 21 over the entire surface of the glass substrate 20, and an alignment film 22 subjected to a predetermined alignment process such as a rubbing process is provided below the counter electrode 21. It has been. The counter electrode 21 is made of a transparent conductive thin film such as an ITO film. The alignment film 22 is made of an organic thin film such as a polyimide thin film.
[0028]
A space between the TFT array substrate 60 and the counter substrate 61 arranged so that the pixel electrode 9a and the counter electrode 21 face each other is surrounded by a sealing material (not shown) formed in a rectangular shape around the substrate. Liquid crystal, which is an example of an electro-optical material, is sealed in the space, and a liquid crystal layer 50 is formed. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one kind or several kinds of nematic liquid crystals are mixed.
[0029]
The TFT array substrate 60 is provided with a pixel switching TFT 30 that controls switching of each pixel electrode 9a at a position adjacent to each pixel electrode 9a.
[0030]
As shown in FIG. 3, the counter substrate 61 may be provided with a second light shielding film 23 called a black mask or a black matrix in a non-opening region of each pixel. Therefore, incident light does not enter the channel region 1a ′, the source side LDD region 1b, and the drain side LDD region 1c of the semiconductor layer 1a of the pixel switching TFT 30 from the counter substrate 61 side. Furthermore, the second light-shielding film 23 has functions of improving contrast and preventing color mixture of color materials when a color filter is formed.
[0031]
Further, as shown in FIG. 3, a first light shielding film 11 a is provided between the TFT array substrate 60 and each pixel switching TFT 30 at a position facing each pixel switching TFT 30. The first light-shielding film 11a and the second light-shielding film 24 are preferably a single metal, alloy, metal silicide, or the like containing at least one of Ti, Cr, W, Ta, Mo, and Pb, which are preferably opaque high melting point metals. Consists of If comprised from such a material, the 1st light shielding film 11a will not be destroyed or melt | dissolved by the high temperature process in the formation process of the pixel switching TFT30 performed after the formation process of the 1st light shielding film 11a on the TFT array substrate 60. You can Since the first light-shielding film 11a is formed, the channel region 1a ′ of the pixel switching TFT 30 and the source-side LDD region 1b that are easily excited by the reflected light (returned light) from the TFT array substrate 60 side. The incident on the drain side LDD 1c can be prevented in advance, and the characteristics of the pixel switching TFT 30 are not deteriorated by the generation of the photocurrent resulting from this.
[0032]
Further, a base insulating film 12 is provided between the first light shielding film 11 a and the plurality of pixel switching TFTs 30. The base insulating film 12 is provided to electrically insulate the semiconductor layer 1a constituting the pixel switching TFT 30 from the first light shielding film 11a. Further, the base insulating film 12 has a function as a base film for the pixel switching TFT 30 by being formed on the entire surface of the TFT array substrate 60. That is, it has a function of preventing deterioration of the characteristics of the pixel switching TFT 30 due to roughness during polishing of the surface of the TFT array substrate 60 and dirt remaining after cleaning. The base insulating film 12 is made of, for example, highly insulating glass such as NSG (non-doped silicate glass), a silicon oxide film, a silicon nitride film, or the like. The base insulating film 12 can also prevent the first light shielding film 11a from contaminating the pixel switching TFT 30 and the like.
[0033]
In the present embodiment, the semiconductor layer 1a extends from the high-concentration drain region 1e to serve as the first capacitor electrode 1f, and a part of the capacitor line 3b facing the second capacitor electrode serves as the second capacitor electrode. The first storage capacitor 70a is configured by extending from the position facing the scanning line 3a and forming a first dielectric film sandwiched between these electrodes. Further, a part of the barrier layer 80 facing the second capacitor electrode is used as a third capacitor electrode 80b, and a first interlayer insulating film 81 is provided between these electrodes. The first interlayer insulating film 81 also functions as a second dielectric film, and a second storage capacitor 70b is formed. The first and second storage capacitors 70a and 70b are connected in parallel through the first contact hole 8a to form the storage capacitor 70.
[0034]
In FIG. 3, the pixel switching TFT 30 has an LDD structure, and includes a scanning line 3a, a channel region 1a ′ of the semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a, the scanning line 3a and the semiconductor layer. Gate insulating film 2 that insulates 1a, data line 6a, low concentration source region (source side LDD region) 1b and low concentration drain region (drain side LDD region) 1c of semiconductor layer 1a, high concentration source region of semiconductor layer 1a 1d and a high concentration drain region 1e. A corresponding one of the plurality of pixel electrodes 9 a is connected to the high concentration drain region 1 e through the barrier layer 80. In this embodiment, the data line 6a is composed of a light-shielding and conductive thin film such as a low resistance metal film such as Al or an alloy film such as metal silicide. A second contact hole 5 leading to the high-concentration source region 1d and a contact hole 8b leading to the barrier layer 80 are formed on the barrier layer 80 and the second dielectric film (first interlayer insulating film) 81, respectively. An interlayer insulating film 4 is formed. The data line 6a is electrically connected to the high concentration source region 1d through the contact hole 5 to the high concentration source region 1d. Further, on the data line 6 a and the second interlayer insulating film 4, a third interlayer insulating film 7 in which a contact hole 8 b to the barrier layer 80 is formed is formed. The pixel electrode 9a is electrically connected to the barrier layer 80 via the contact hole 8b, and is further electrically connected to the high-concentration drain region 1e via the contact hole 8a via the barrier layer 80. The above-described pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 7 thus configured.
[0035]
The pixel switching TFT 30 preferably has an LDD structure as described above, but may have an offset structure in which impurity ions are not implanted into the low concentration source region 1b and the low concentration drain region 1c, and the gate electrode 3a is masked. Alternatively, a self-aligned TFT in which impurity ions are implanted at a high concentration to form high concentration source and drain regions in a self-aligning manner may be used.
[0036]
In the present embodiment, the capacitor line 3b is formed of a polysilicon film in which P is diffused, and the surface thereof is roughened so that the surface roughness Ra is 0.2 μm, for example. As a result, the gate insulating film 2 and the first interlayer insulating film 81 are in contact with the roughened surface. In the present embodiment, since the surface in contact with the gate insulating film 2 of the capacitance line 3b is roughened, the surface area of the surface in contact with the insulating film is increased compared to the case where the surface is not roughened, The first storage capacity 70a is increased by about 1.02. Furthermore, in the present embodiment, since the surface of the capacitor line 3b that contacts the first interlayer insulating film 81 is also roughened, the second storage capacitor 70b is increased as compared with the case where the surface is not roughened. As a result, since the first and second storage capacitors 70a and 70b are connected in parallel to form a storage capacitor, the total capacity of the first and second storage capacitors 70a and 70b is about 2 as compared with the case where the surface of the capacitor line 3b is not roughened. The storage capacity can be increased 04 times.
[0037]
As described above, in the configuration in which the storage capacitor is formed by disposing the two capacitance electrodes through the insulating film, the surface of the at least one electrode of the two capacitance electrodes that contacts the insulating film is roughened. The surface area of the surface is increased, and the storage capacity can be increased. Therefore, the storage capacity can be increased as compared with the conventional case without changing the formation area of the capacity electrode on the substrate. Further, in the present embodiment, by providing the barrier layer 80, the storage capacitor can be formed by stacking the first storage capacitor 70a and the second storage capacitor 70b, and the high pixel aperture ratio can be maintained. However, the storage capacity can be increased.
[0038]
(Configuration of diffusion furnace used in manufacturing the embodiment of the electro-optical device)
The polysilicon layer having a roughened surface constituting the capacitance line is formed by patterning a roughened polysilicon film formed on the entire surface of the substrate into a predetermined shape. FIG. 8 is a schematic longitudinal sectional view showing an example of a diffusion furnace used when the surface of the polysilicon film is roughened while diffusing P in the polysilicon. Although FIG. 8 shows an example of a horizontal diffusion furnace, a vertical diffusion furnace may naturally be used. The roughened polysilicon film is formed by the batch type diffusion furnace 51 shown in the figure, and POCl_ThreeThis liquid is used as a diffusion source to diffuse P into the polysilicon film.
[0039]
As shown in FIG. 8, the diffusion furnace 51 includes a quartz tube 58 and a quartz boat 53 that is disposed in the quartz tube 58 and accommodates the substrate 10 on which a plurality of polysilicon films are formed with a predetermined gap. Is provided. Further, a heater 52 for heating the quartz tube 58 is provided around the quartz tube 58. Outside the quartz tube 58, POCl, which is a liquid diffusion source 56, is provided._ThreeContainer 59, POCl accommodated in container 59_ThreeA first supply pipe 55 for supplying nitrogen gas from a supply source (not shown) is provided therein. Then, POCl dissolved in the container 59 up to the saturated vapor pressure._ThreeIs further provided as a second supply pipe 54 for supplying oxygen gas into the quartz pipe 58 from a supply source (not shown). Also works. Further, an exhaust pipe 57 is provided for exhausting the gas in the quartz tube 58 by an exhaust means (not shown) to set the processing space in a predetermined reduced pressure atmosphere.
[0040]
In this diffusion furnace 51, POCl_ThreeBy flowing nitrogen gas into the liquid diffusion source, the diffusion source is dissolved to the saturated vapor pressure. Further, by simultaneously flowing oxygen, the surface of the polysilicon film on the substrate is made of phosphorous oxide (P₂O_Five) Is formed. This phosphorus oxide serves as a diffusion source, and P is diffused into the polysilicon film.
[0041]
(Manufacturing process in this embodiment of electro-optical device)
Next, a manufacturing process of the liquid crystal device in the embodiment having the above-described configuration will be described with reference to FIGS. 4 to 7 are process diagrams showing the respective layers on the TFT array substrate side in each process corresponding to the A-A 'cross section of FIG. 2 as in FIG. FIG. 8 is a schematic cross-sectional view of a diffusion furnace used when forming scanning lines and capacitance lines, and FIG. 9 is a diagram for explaining a method for forming a roughened polysilicon film.
[0042]
First, as shown in step (1) of FIG. 4, a substrate such as a quartz substrate, hard glass, or silicon substrate, here a substrate 10 made of a quartz substrate is prepared. First, the substrate 10 is preferably N.₂Annealing is performed in an inert gas atmosphere such as (nitrogen) and at a high temperature of about 900 to 1300 ° C., and pretreatment is performed so as to reduce distortion generated in the TFT array substrate 60 in a high-temperature process to be performed later. That is, the substrate 10 is heat-treated in advance at the same temperature or higher in accordance with the temperature at which the high temperature treatment is performed at the maximum temperature in the manufacturing process. Then, a metal alloy film such as a metal such as Ti, Cr, W, Ta, Mo, and Pb, or a metal silicide is sputtered on the entire surface of the TFT array substrate 60 processed in this manner to a thickness of about 100 to 500 nm. Preferably, the light shielding film 11 having a thickness of about 200 nm is formed. An antireflection film such as a polysilicon film may be formed on the light shielding film 11 in order to reduce surface reflection.
[0043]
Next, as shown in step (2), a resist mask corresponding to the pattern of the first light shielding film 11a (see FIG. 2) is formed on the formed light shielding film 11 by photolithography, and the resist mask is interposed through the resist mask. By etching the light shielding film 11, the first light shielding film 11a is formed.
[0044]
Next, as shown in step (3), TEOS (tetra-ethyl ortho-silicate) gas, TEB (tetra-ethyl wafer boat) is formed on the first light-shielding film 11a by, for example, normal pressure or low-pressure CVD. The base insulating film 12 made of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed using a rate gas, TMOP (tetra-methyl-oxy-phosphate) gas, or the like. To do. The film thickness of the base insulating film 12 is, for example, about 500 to 2000 nm.
[0045]
Next, as shown in step (4), the flow rate is about 0.4 to 0.6 l / min on the base insulating film 12 in a relatively low temperature environment of about 450 to 550 ° C., preferably about 500 ° C. An amorphous silicon film is formed by low pressure CVD (for example, CVD at a pressure of about 20 to 40 Pa) using monosilane gas, disilane gas, or the like. Thereafter, an annealing process is performed in a nitrogen atmosphere at about 600 to 700 ° C. for about 1 to 10 hours, preferably 4 to 6 hours, so that the polysilicon film 1 has a thickness of about 50 to 200 nm, preferably Is solid-phase grown to a thickness of about 100 nm. As a method for solid phase growth, annealing using RTA (Rapid Thermal Anneal) may be used, or laser annealing using an excimer laser or the like may be used.
[0046]
At this time, when an n-channel type pixel switching TFT 30 is formed as the pixel switching TFT 30 shown in FIG. 3, Vb such as Sb (antimony), As (arsenic), P (phosphorus), etc. is formed in the channel region. A group element dopant may be slightly doped by ion implantation or the like. When the pixel switching TFT 30 is a p-channel type, a dopant of a group III element such as B (boron), Ga (gallium), or In (indium) may be slightly doped by ion implantation or the like. Note that the polysilicon film 1 may be directly formed by a low pressure CVD method or the like without going through an amorphous silicon film. Alternatively, the polysilicon film 1 may be formed by implanting silicon ions into a polysilicon film deposited by a low pressure CVD method or the like to make it amorphous (amorphized) and then recrystallizing it by annealing or the like.
[0047]
Next, as shown in step (5), a semiconductor layer 1a having a predetermined pattern including the first capacitor electrode 1f as shown in FIG. 2 is formed by a photolithography process, an etching process, or the like.
[0048]
Next, as shown in step (6), by thermally oxidizing the first capacitor electrode 1f together with the semiconductor layer 1a constituting the pixel switching TFT 30 at a temperature of about 900 to 1300 ° C., preferably about 1000 ° C. Then, a thermal oxide thin film 2a having a relatively thin thickness of about 30 nm is formed, and as shown in step (7), an insulating film 2b made of a high temperature oxide thin film (HTO film) or a nitride thin film is formed by a low pressure CVD method or the like. A first dielectric film 2 for forming a storage capacitor is formed simultaneously with the gate insulating film 2 of the pixel switching TFT 30 having a multilayer structure including a thermally oxidized thin film 2a and an insulating film 2b, deposited to a relatively thin thickness of 50 nm. . As a result, the first capacitor electrode 1f has a thickness of about 30 to 150 nm, preferably about 35 to 50 nm, and the gate insulating film 2 (first dielectric film) has a thickness of about 30 to 150 nm. The thickness is 20 to 150 nm, preferably about 30 to 100 nm. By shortening the high-temperature thermal oxidation time in this way, it is possible to prevent warpage due to heat, particularly when a large substrate of about 8 inches is used. However, the gate insulating film 2 having a single layer structure may be formed only by thermally oxidizing the polysilicon film 1.
[0049]
Next, as shown in step (8), after a resist layer 500 is formed on the semiconductor layer 1a excluding a portion to be the first capacitor electrode 1f by a photolithography process, an etching process, etc., for example, a dose of P ions is reduced to about 3 × 10¹²/ Cm²The first capacitor electrode 1f may be reduced in resistance by doping.
[0050]
Next, as shown in step (9), after removing the resist layer 500, the polysilicon film 3 into which P ions whose surface has been roughened is introduced has a thickness of about 100 to 500 nm, preferably about 100 nm. A film is formed to a thickness of 300 nm. A detailed method for forming the polysilicon film will be described below with reference to FIGS. FIG. 9 is a partial cross-sectional view showing a region where a semiconductor layer is formed.
[0051]
First, as shown in FIG. 9A, after removing the resist layer 500, a polysilicon film 100 is deposited on the gate insulating film 2 by a low pressure CVD method or the like. As shown in FIG. 8, a plurality of substrates 10 on which the polysilicon film 100 is deposited are accommodated in a quartz boat 53 with a predetermined gap. The quartz boat 53 is inserted into the quartz tube 58 of the diffusion furnace 51 that has been heated to a temperature of 700 ° C. by the heater 52 in advance. After the quartz boat 53 is inserted, the quartz tube 57 is exhausted by the exhaust tube 57. Further, nitrogen gas is supplied into the quartz tube 57 using the second supply pipe 54, and at the same time, the temperature in the processing space is raised to 950 ° C. by the heater 52 and left for about 1 hour until the substrate temperature is stabilized. Until the substrate temperature is stabilized, a natural oxide film may be formed on the polysilicon film 100, and it is desirable to suppress the film thickness of the natural oxide film to 10 nm or less. By suppressing the film thickness to 10 nm or less, P can be efficiently diffused into the polysilicon film in a later step.
[0052]
Next, as shown in FIG. 8, POCl which is a liquid diffusion source 56 is used._ThreeThe diffusion source 56 is dissolved up to the saturated vapor pressure by flowing nitrogen gas through the first supply pipe 55 from a nitrogen gas supply source (not shown). POCl dissolved to this saturated vapor pressure_ThreeAt the same time, nitrogen gas and oxygen gas are supplied into the quartz tube 57 through the second supply pipe 54 at a flow rate ratio of about 7: 1 for about 20 minutes. At this time, the temperature in the quartz tube 57 is maintained at 950 ° C.
[0053]
As a result, as shown in FIG. 9B, the surface of the polysilicon film 100 on the substrate 10 has a glassy state phosphorous oxide (P₂O_Five) 101 is formed. The phosphor oxide 101 serves as a diffusion source, reacts with Si of the polysilicon film, P is diffused into the polysilicon film, and the porous polysilicon film 3 as shown in FIG. Is formed.
[0054]
Next, as shown in FIG. 9 (4), the phosphorus oxide (P₂O_Five) 101 is removed by a wet etching method using anhydrous HF or the like. Thereby, the polysilicon film 3 whose surface is roughened is exposed. The surface of the polysilicon film 3 is roughened on the surface in contact with the gate insulating film 2 and the exposed surface.
[0055]
After the formation of the roughened polysilicon film 3, as shown in step (10) of FIG. 5, the roughened polysilicon film 3 is formed by a photolithography process, an etching process, etc. using a resist mask. Etching into a predetermined pattern as shown in FIG. 2 forms the capacitor line 3b together with the scanning line 3a.
[0056]
Next, as shown in step (11), when the pixel switching TFT 30 shown in FIG. 3 is an n-channel TFT having an LDD structure, the low concentration source region 1b and the low concentration drain region are first formed in the semiconductor layer 1a. In order to form 1c, the scanning line 3a (gate electrode) is used as a mask and a dopant of a group V element such as P is formed at a low concentration (for example, P ions are added to 1 to 3 × 10 6¹³/ Cm²Dope). As a result, the semiconductor layer 1a under the scanning line 3a becomes a channel region 1a '. The resistance of the capacitor line 3b and the scanning line 3a is further reduced by doping the impurities.
[0057]
Next, as shown in step (12), in order to form the high concentration source region 1d and the high concentration drain region 1e constituting the pixel switching TFT 30, the resist layer 600 is scanned with a mask wider than the scanning line 3a. After forming on the line 3a, a dopant of a group V element such as P is also used at a high concentration (for example, P ions are added to 1 to 3 × 10¹⁵/ Cm²Dope). When the pixel switching TFT 30 is a p-channel type, B or the like is used to form the low concentration source region 1b and the low concentration drain region 1c, the high concentration source region 1d and the high concentration drain region 1e in the semiconductor layer 1a. Doping is performed using a group III element dopant. For example, an TFT having an offset structure may be used without doping at a low concentration, or a self-aligned TFT may be formed by an ion implantation technique using P ions, B ions, or the like using the scanning line 3a as a mask. The resistance of the capacitor line 3b and the scanning line 3a is further reduced by doping the impurities.
[0058]
In parallel with the element forming process of these TFTs 30, peripheral circuits such as a data line driving circuit and a scanning line driving circuit having a complementary structure composed of an n-channel TFT and a p-channel TFT are provided as a TFT array substrate 60. You may form in the upper peripheral part. Thus, if the semiconductor layer 1a constituting the pixel switching TFT 30 is formed of polysilicon in this embodiment, the peripheral circuit can be formed in almost the same process when the pixel switching TFT 30 is formed, which is advantageous in manufacturing. It is.
[0059]
Next, as shown in step (13), after removing the resist layer 600, the capacitor line 3b, the scanning line 3a, and the gate insulating film 2 (first dielectric film) are formed by a low pressure CVD method, a plasma CVD method, or the like. A first interlayer insulating film 81 made of a high-temperature oxide thin film (HTO film) or a nitride thin film is deposited to a relatively thin thickness of 10 nm to 200 nm. However, the first interlayer insulating film 81 may be formed of a multilayer film, and the first interlayer insulating film 81 can be formed by various known techniques generally used for forming a gate insulating film of a TFT. . In the case of the first interlayer insulating film 81, if it is made too thin as in the case of the second interlayer insulating film 4, the parasitic capacitance between the data line 6a and the scanning line 3a will not increase, and the gate insulation in the TFT 30 will not occur. When the film 2 is made too thin, a unique phenomenon such as a tunnel effect does not occur. The first interlayer insulating film 81 functions as a second dielectric film between the second capacitor electrode 3b and the barrier layer 80 to be formed later. As the second dielectric film 81 is made thinner, the second storage capacitor 70b becomes larger. Therefore, on the condition that defects such as film breakage do not occur after all, the thickness is 50 nm or less thinner than the gate insulating film 2. If the second dielectric film 81 is formed so as to have an extremely thin insulating film, the effect of this embodiment can be increased.
[0060]
Next, as shown in the step (14), a contact hole 8a for electrically connecting the barrier layer 80 to be formed later and the high-concentration drain region 1e is formed by dry etching such as reactive ion etching or reactive ion beam etching. It is formed by etching. Since such dry etching has high directivity, a contact hole 8a having a small diameter can be opened. Alternatively, wet etching advantageous for preventing the contact hole 8a from penetrating the semiconductor layer 1a may be used in combination. This wet etching is also effective from the viewpoint of providing a taper for making a better contact with the contact hole 8a.
[0061]
Next, as shown in step (15), a metal or metal such as Ti, Cr, W, Ta, Mo and Pb is formed on the entire surface of the high-concentration drain region 1e viewed through the first interlayer insulating film 81 and the contact hole 8a. A metal alloy film such as silicide is deposited by sputtering to form a conductive film 80 ′ having a thickness of about 50 to 500 nm. If the thickness is about 50 nm, there is almost no possibility of penetrating through the second contact hole 8b later. Note that an antireflection film such as a polysilicon film may be formed on the conductive film 80 'in order to reduce surface reflection. The conductive film 80 'may be a doped polysilicon film or the like for stress relaxation.
[0062]
Next, as shown in step (16) of FIG. 6, a resist mask corresponding to the pattern of the barrier layer 80 (see FIG. 2) is formed on the formed conductive film 80 ′ by photolithography, and the resist mask is formed. Then, the conductive layer 80 ′ is etched to form the barrier layer 80 including the third capacitor electrode 80a.
[0063]
Thereafter, NSG, PSG (phosphorus silicate glass), BSG (boron silicate glass) are used to cover the first interlayer insulating film 81 and the barrier layer 80 by using, for example, atmospheric pressure or reduced pressure CVD method or TEOS gas. Then, a second interlayer insulating film 4 made of a silicate glass film such as BPSG (boron phosphorus silicate glass), a nitride thin film or an oxide thin film is formed. The film thickness of the second interlayer insulating film 4 is preferably about 500 to 1500 nm. If the thickness of the second interlayer insulating film 4 is 500 nm or more, the parasitic capacitance between the data line 6a and the scanning line 3a is not excessive or hardly causes a problem.
[0064]
Next, in step (17), annealing is performed at about 1000 ° C. for about 20 minutes in order to activate the high concentration source region 1d and the high concentration drain region 1e, and then the contact hole 5 for the data line 6a is opened. Make a hole. Further, contact holes for connecting the scanning lines 3 a and the capacitor lines 3 b to wirings (not shown) in the substrate peripheral region can be formed in the second interlayer insulating film 4 by the same process as the contact holes 5.
[0065]
Next, as shown in step (18), a low resistance metal such as light-shielding Al or a metal silicide or the like is formed on the second interlayer insulating film 4 by sputtering or the like as a metal film 6 to have a thickness of about 100 to 500 nm. Deposit to a thickness, preferably about 300 nm.
[0066]
Next, as shown in step (19), the data line 6a is formed by a photolithography process, an etching process, or the like.
[0067]
Next, as shown in step (20) of FIG. 7, a silicate glass such as NSG, PSG, BSG, or BPSG is used to cover the data line 6a by using, for example, atmospheric pressure or reduced pressure CVD method or TEOS gas. A third interlayer insulating film 7 made of a film, a nitride thin film, an oxide thin film or the like is formed. The thickness of the third interlayer insulating film 7 is preferably about 500 to 1500 nm.
[0068]
Next, as shown in step (21), a contact hole 8b for electrically connecting the pixel electrode 9a and the barrier layer 80 is formed by dry etching such as reactive ion etching or reactive ion beam etching. Further, wet etching may be used to form a taper.
[0069]
Next, as shown in step (22), a transparent conductive thin film 9 such as an ITO film is deposited on the third interlayer insulating film 7 to a thickness of about 50 to 200 nm by sputtering or the like. As shown in (23), the pixel electrode 9a is formed by a photolithography process, an etching process, or the like. When the liquid crystal device is used for a reflective liquid crystal device, the pixel electrode 9a may be formed from an opaque material having a high reflectance such as Al.
[0070]
Subsequently, after applying a polyimide alignment film coating solution on the pixel electrode 9a, the alignment film 16 (see FIG. 3) is subjected to a rubbing process so as to have a predetermined pretilt angle and in a predetermined direction. Is formed. Thereby, the wafer 10a is in a state where a plurality of TFT array substrates 60 are formed.
[0071]
On the other hand, with respect to the counter substrate 61 shown in FIG. 3, the glass substrate 20 and the like are first prepared, and the second light shielding film 23 and the frame light shielding film as the frame are sputtered with, for example, metal chromium, and then a photolithography process and an etching process. It is formed through. The second light-shielding film and the frame light-shielding film may be formed from a material such as resin black in which carbon or Ti is dispersed in a photoresist in addition to a metal material such as Cr, Ni, or Al. If the light shielding region is defined on the TFT array substrate 60 by the data line 6a, the barrier layer 80, the first light shielding film 11a, etc., the second light shielding film 23 on the counter substrate 61 can be omitted.
[0072]
Then, the counter electrode 21 is formed by depositing a transparent conductive thin film such as ITO to a thickness of about 50 to 200 nm by sputtering or the like on the entire surface of the glass substrate 20. Further, after applying a polyimide-based alignment film coating solution over the entire surface of the counter electrode 21, the alignment film 22 (see FIG. 3) is formed by performing a rubbing process so as to have a predetermined pretilt angle and in a predetermined direction. Then, the counter substrate 61 is manufactured.
[0073]
Finally, the TFT array substrate 60 and the counter substrate 61 are bonded together with a sealing material (not shown) so that the alignment films 16 and 22 face each other, and a plurality of types, for example, are formed in the space between both substrates by vacuum suction or the like. Liquid crystal formed by mixing the nematic liquid crystals is sucked to form a liquid crystal layer 50 having a predetermined thickness, whereby a liquid crystal device is obtained.
[0074]
In the present embodiment, in the method for forming the polysilicon film constituting the capacitor line 3b, the processing temperature at the time of P diffusion into the polysilicon film is 950 ° C., but it is 860 ° C. or more, more preferably 900 ° C. or more. It ’s fine. By performing P diffusion in such a temperature range, a polysilicon film having a roughened surface can be obtained, and a large storage capacity can be obtained by using such a polysilicon film as a capacitor electrode. be able to.
[0075]
Here, the change in the storage capacity due to the difference in the processing temperature during the diffusion of P will be described with reference to FIG. In FIG. 10, the horizontal axis represents the processing temperature, and the vertical axis represents the accumulated capacity value. In addition, the measured value of the storage capacity described in FIG. 10 is measured by using the liquid crystal device having the structure in which the barrier layer 80 is not formed in the configuration of the liquid crystal device described above. Specifically, a through hole is formed in the second interlayer insulating film 4 and the third interlayer insulating film 7, and the pixel electrode 9a and the semiconductor layer 1a are connected by this through hole. The second storage capacitor 70b is not formed, and only the first storage capacitor 70a is formed.
[0076]
As shown in FIG. 10, when the processing temperature is set to 860 ° C. or higher, the storage capacity is significantly higher than that of a liquid crystal device manufactured by processing at a processing temperature of 850 ° C., which has been conventionally performed. It can be seen that it is increasing. It can also be seen that the storage capacity is further increased by setting the processing temperature to 900 ° C. or higher.
[0077]
As described above, according to the present invention, in the configuration in which the storage capacitor is formed by disposing the two capacitance electrodes via the insulating film, the surface that contacts the insulating film of at least one of the two capacitance electrodes is rough. By increasing the surface area, the surface area of the surface increases and the storage capacity can be increased. Therefore, the storage capacity can be increased as compared with the conventional case without changing the pixel aperture ratio. Further, in the present embodiment, by providing the barrier layer 80, the storage capacitor can be formed by stacking the first storage capacitor 70a and the second storage capacitor 70b, and the high pixel aperture ratio can be maintained. However, the storage capacity can be increased.
[0078]
In the present embodiment, the barrier layer 80 is formed as a relay electrode for connecting the semiconductor layer 1a and the pixel electrode 9a. However, without using the barrier layer 80, the second interlayer insulating film 4 and the third layer It is also possible to form a through hole in the interlayer insulating film 7 and connect the pixel electrode 9a and the semiconductor layer 1a through the through hole. In this case, the second storage capacitor 70b described above is not formed, and only the first storage capacitor 70a is formed. Even when such a structure in which a plurality of storage capacitors are not stacked is used, a large storage capacitor can be obtained by roughening the surface of the capacitor electrode as in the present invention.
[0079]
In the present embodiment, the TFT semiconductor layer is extended and used as the first capacitor electrode. However, the first capacitor electrode may be formed in a separate process from the formation of the TFT semiconductor layer. . Thereby, a roughened polysilicon film can be used as the first capacitor electrode. In this case, since both of the two capacitor electrodes forming the storage capacitor have a roughened surface, the storage capacitor is more in comparison with the case where only one of the capacitor electrodes has a roughened surface. Is increased.
[0080]
In the present embodiment, the capacitor line is used as the second capacitor electrode. However, for example, a scan line can be used as the second capacitor electrode without using the capacitor line.
[Brief description of the drawings]
FIG. 1 is an equivalent circuit of various elements, wirings, and the like provided in a plurality of matrix pixels that form an image display region in a liquid crystal device that is an embodiment of an electro-optical device.
FIG. 2 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, light shielding films and the like are formed in the liquid crystal device according to the embodiment.
FIG. 3 is a cross-sectional view taken along the line A-A ′ of FIG.
FIG. 4 is a process diagram (part 1) illustrating a manufacturing process of the liquid crystal device according to the embodiment in order.
FIG. 5 is a process diagram (part 2) illustrating the manufacturing process of the liquid crystal device according to the embodiment in order.
FIG. 6 is a process diagram (part 3) illustrating the manufacturing process of the liquid crystal device according to the embodiment in order.
FIG. 7 is a process diagram (part 4) illustrating the manufacturing process of the liquid crystal device according to the embodiment in order.
FIG. 8 is a schematic longitudinal sectional view of a diffusion furnace used for P diffusion into a polysilicon film.
FIG. 9 is a diagram illustrating a method for forming a polysilicon film having a roughened surface according to the embodiment.
FIG. 10 is a diagram showing a relationship between processing temperature and storage capacity during P diffusion.
[Explanation of symbols]
1 ... Semiconductor layer
1f ... first capacitor electrode
2 ... Gate insulation film
3 ... Roughened polysilicon film
3a ... scan line
3b: Capacitance line (second capacitor electrode)
9a: Pixel electrode
10 ... Quartz substrate
30 ... TFT for pixel switching
51 ... Diffusion furnace
52 ... Heater
54 ... Second supply pipe
55. First supply pipe
56 ... POCl_Three
59 ... Container
60 ... TFT array substrate
80 ... Barrier layer
81. First interlayer insulating film
100: polysilicon film
101 ... Phosphorylated film

Claims (5)

A pixel electrode on the substrate;
A scan line and a data line arranged to cross each other;
A switching element which is formed corresponding to the pixel electrode at each intersection and has a semiconductor layer provided via the scanning line and the insulating film;
A second capacitor electrode formed in the same layer as the scanning line and substantially in parallel ;
A first capacitor electrode formed by extending the semiconductor layer and corresponding to the pixel electrode with respect to the second capacitor electrode via an insulating film;
In the manufacturing method of the electro-optical device in which
The first capacitor electrode or the second capacitor electrode is:
Forming a polysilicon film on the substrate;
By supplying nitrogen gas and oxygen gas onto the polysilicon film simultaneously with supply of vapor using POCl ₃ as a diffusion source,
Forming a film of phosphorus oxide on the polysilicon film;
Diffusing P in the phosphor oxide into the polysilicon film;
A step of performing wet etching on the polysilicon film with anhydrous HF,
A method for manufacturing an electro-optical device, wherein   The method of manufacturing an electro-optical device according to claim 1, wherein the diffusion is performed in a batch type diffusion furnace. An electro-optical device manufactured by the method for manufacturing an electro-optical device according to claim 1 . The surface of the first capacitor electrode or the second capacitor electrode in contact with the insulating film is roughened so that the surface roughness Ra is 0.2 μm or more and 0.5 μm or less. The electro-optical device according to claim 3 . The electro-optical device according to claim 4 , wherein the first capacitor electrode or the second capacitor electrode having the roughened surface has a porous film quality.

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