JPH0637117A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To stably form a uniform two-stage recessed structure between lots or wafers by separately forming the upper and lower recessed areas of the two-recessed structure in two processes. CONSTITUTION:A pattern which decides the width W2 and gate length Lg of an upper recessed area 4 is formed on a semiconductor active layer 2 by applying a photoresist 3 to the layer 2. The area 4 and a dummy gate 5 are formed by dry etching the layer 2 by the RIE method, etc., by using the photoresist 3 as a mask. Then, after partially etching off an insulator 6 in the area 4 by using a photoresist 7 as a mask, a lower recessed area 8 is formed by etching the layer 2 which has become a dummy gate 8 and the substrate 1 below the layer 2. In the two-stage recessed area 9 formed in such a way, a T-shaped gate electrode 10 is formed. Therefore, a semiconductor device having a stable performance can be manufactured at a high yield.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a two-step recess type gate electrode.

[0002]

2. Description of the Related Art (Prior Art 1) As a conventional method of manufacturing a compound semiconductor field effect transistor having a two-step recess type gate electrode, for example, FIGS. 14 (a) to 14 (c) to FIG.
A method based on the process sectional views of (a) to (c) is known. That is, ion implantation of impurities or the like is performed on the GaAs compound semiconductor substrate 31 to form a semiconductor active layer 32, and an insulating film such as a nitride film (SiN) or an oxide film (SiO) or a photo film is formed on the semiconductor active layer 32. After forming the spacer layer 33 made of a resist, a photoresist 34 for performing gate patterning is laminated thereon. Next, with the gate pattern of the photoresist 34 as a mask, the spacer layer 33 is covered with C
It is removed by etching by the RIE method using F4 + O2 gas to form an opening 35 having a width L of 0.5 .mu.m as shown in FIG. When the spacer layer 33 is formed of a photoresist as described above, a different type from the photoresist 34 laminated thereon is used.

Next, the semiconductor active layer 32 is wet-etched by a desired amount through the opening 35 using the photoresist 34 as a mask to form a lower recess region 36a as shown in FIG. 14 (b). The depth t1 of the lower recess region 36a is about 0.1 μm when the thickness of the semiconductor active layer 32 is 0.5 μm. The recess width W1 of the lower recess region 36a is about 0.5 depending on the etching method and the type of etching solution.
Is about 0.7 μm. Next, as shown in FIG. 14 (c), only the spacer layer 33 is covered with a buffered hydrofluoric acid solution so that both sides are approximately 0.2 μm.
Side etching is performed gradually. Then spacer layer 3
The upper recess region 36b is formed by wet-etching the semiconductor active layer 32 again using 3 as a mask, and the two-step recess region 36 as shown in FIG. 15A is obtained.

2 for forming the upper recess region 36b
Two-step recess region 36 obtained by the second etching
Of the upper recess 36b has a depth t2 of 0.
2 μm, width W2 is 1.1 μm, lower recess 36a
Has a depth t1 equal to the depth of the first etching of 0.1
μm. However, the width W1 'of the lower recess 36a is
Is about 0.9 .mu.m in isotropic wet etching, which is wider than the width W1 initially formed.

After that, as shown in FIG. 15B, a gate electrode metal 37a is deposited on the photoresist 34 and through the opening 35 into the two-step recess region 36 by vacuum deposition or the like, and then the photoresist 34 is lifted off. , And by removing the gate electrode metal 37a thereon,
A semiconductor device is obtained by forming a gate electrode 37 having a gate length Lg (approximately the same value as the width L of the opening 35) in a two-step recess region 36 as shown in FIG. 15C. Although not shown, a field effect transistor (FET) is formed by forming a drain electrode and a source electrode on both sides of the position of the gate electrode 37 in any step before and after the above step.

(Conventional Example 2) FIG. 6 is a cross-sectional view showing a field effect transistor (MESFET) having a two-step recess type metal Schottky junction gate electrode, which is a kind of compound semiconductor device targeted by the present invention. 16 is shown in FIG.
FIG. 41 is a cross-sectional view showing main forming steps of a conventional method for forming the two-step recessed gate electrode of FIG.
Is a wafer (compound semiconductor substrate), and 46 is an active layer formed in its surface region. 42 (42a, 42
b) is an ohmic electrode formed on the active layer 46,
Reference numeral 4 is an upper recess, 45 is a lower recess, and 43 is a gate electrode formed in the lower recess 45. Also,
In FIG. 16, 52 is an insulating film and 62 is a resist. However, except for FIG. 6, the active layer 46 is not shown because it is considered as a part of the wafer 41.

In the MESFET and the like shown in FIGS. 6 and 16, the voltage applied to the gate electrode 43 and the ohmic electrodes 42a and 42b must be increased in order to increase the output. In order to increase the breakdown voltage as described above, there is a method of making the active layer 46 in the vicinity of the gate electrode 43 thin so that the depletion layer easily spreads laterally in the vicinity of the gate electrode 43 when the gate electrode 43 is biased. As one of the methods, there is a method of forming a two-step recess type gate structure. Next, the conventional forming method will be described.

As shown in FIG. 16 (a), an insulating film 52 made of SiO2 is formed on the entire surface of the wafer 41 so as to have a thickness of about 0.1 .mu.m.
A VD method or the like is used for deposition, a resist 62 having a thickness of about 0.5 μm is formed thereon, and an opening pattern having an opening width of 0.5 μm is formed near the gate electrode formation site. Next, in FIG.
As shown in (b), using the resist 62 as a mask, the lower insulating film 5 is formed.
Wet etching with 2 using hydrofluoric acid or CHF
Etching is performed by dry etching using 3 + O2 gas or the like. Next, as shown in FIG. 16C, the wafer 41 is etched with the insulating film 52 as a mask by wet etching using tartaric acid or the like, or dry etching using chlorine-based gas, and a recess with a depth of about 0.1 μm is formed. 47 is formed. Next, as shown in FIG. 16D, the insulating film 52 is selectively side-etched with hydrofluoric acid or the like to widen the opening of the insulating film 52. Next, as shown in FIG. 16E, the wafer 41 is etched by wet etching using tartaric acid or the like with the insulating film 52 as a mask, and the lower recess 47 is further lowered to a depth of about 0.3 μm. Lower recess 45 with a width of about 0.9 μm, depth of about 0.1 μm, width of about 1.4-
An upper recess 44 of 2.4 μm is formed. Next, in FIG.
As shown in (f), Ti / Au is used as the metal for the gate electrode.
By vapor-depositing the like and performing the lift-off method, the structure shown in FIG. 16 (g) having the gate electrode 43 having a gate width of about 0.5 μm and a gate height of about 0.5 μm, that is, the structure of FIG. 6 is formed. It

(Prior art example 3) FIG. 17 is a view showing still another example of a conventional two-step recess forming method of this kind of two-step recess type field effect transistor, in which 71 is a semiconductor substrate and 78 is a semiconductor substrate. An active layer, 72 is an ohmic electrode, 73 is an insulating film, 74 is a resist, 75 is a first recess, 76 is a second recess, and 77 is a Schottky metal.

Next, the manufacturing process will be described. In FIG. 3A, after forming the source, drain and ohmic electrodes 72 on the active layer 78 formed on the semiconductor substrate 71,
An insulating film 73, for example, a SiN film is formed on the entire surface. Then F
A resist pattern 74 having an opening is formed at a position where the ET gate electrode is desired to be formed.

Next, as shown in FIG. 1B, after the insulating film 73 in the resist opening is etched by SF6 plasma treatment or the like, the exposed GaAs of the active layer 78 is changed to a proper Ga.
As etching solution, for example, H2 SO4: H2 O2: H2
Etching is performed with O = 3: 1: 1 to obtain a first recess 75.

Next, as shown in FIG. 3C, the insulating film 73 is side-etched by immersing it in an appropriate etching solution, for example, 30% HF solution. In this state, when it is immersed in the GaAs etching solution described above, a second recess 76 is obtained in addition to the first recess 75 that is etched deeper. The etching shape is a two-step structure as shown in FIG. Becomes

Next, a Schottky metal 77 such as Ti
/ Pt / Au = 500 Å / 500 Å / 5000 Å
It is in the state of (e). Next, in the lift-off process, the resist 74
And unnecessary metal on it are removed, and the state of Fig. (F) is obtained.

[0014]

A compound semiconductor field effect transistor device having a conventional two-step recess can be obtained by the above method. However, when forming the two-step recess, the spacer layer 33 or the insulating layer 52, The side etching of 73 controls the etching amount by the immersion time of the etching solution or etching gas supplied through the openings of the photoresists 34, 62, 74, but the supply of the etching solution is not uniform within the wafer surface. Or the control of the side etching amount becomes unstable because the etching rate changes due to the adhesive force of the semiconductor active layer / spacer layer (insulating layer) / photoresist, and the side etching amount varies between lots and wafers. There were variations. Since the widths of the first and second recesses are determined by the side etching amount of the insulating film, there is a problem that the recess shape greatly varies due to the variation of the side etching amount. Further, if the recess shape varies or fluctuates due to the variation in the side etch amount between lots or wafers, the source resistance Rs and the gate / drain withstand voltage V that determine the characteristics of the FET are generated.
It caused gd0 to scatter, which caused a decrease in yield.

The present invention has been made in order to solve the above problems, and it is possible to stably form a two-step recess structure that is uniform between lots and between wafers, and has high device characteristics. It is an object of the present invention to obtain a method for manufacturing a semiconductor device that can achieve uniformity and reduce element cost. Another object of the present invention is to obtain a method of manufacturing a semiconductor device capable of forming a T-type gate electrode.

[0016]

[Means for Solving the Problems] Claim 1 of the present invention
In the method of manufacturing a semiconductor device having a stepped recess, patterning for determining the width W2 of the upper recess and the gate length Lg is first performed on the semiconductor active layer by applying a photoresist, and the semiconductor active layer is subjected to the RIE method using the photoresist as a mask. Dry etching is performed to form an upper recess region and a dummy gate, and then an insulator is embedded in the upper recess region, and then an opening wider than the dummy gate is formed on the semiconductor active layer including the upper surface of the recess by photoresist. Is formed by coating and patterning, the insulating material in the upper recess region is partially removed by etching using the photoresist as a mask, and then the semiconductor active layer serving as a dummy gate and the semiconductor substrate thereunder are etched to form a lower portion. A two-step recess is obtained by forming a recess area.
A T-shaped gate electrode is formed in the step recess region by vacuum evaporation and lift-off.

In the method for manufacturing a semiconductor device having a two-step recess structure according to a second aspect of the invention, a dummy gate and a sidewall are formed of an insulating film on a semiconductor active layer, and then exposed on both sides of the sidewall. Photoresist is applied on the semiconductor active layer so as to expose the dummy gate and the sidewall, and then only the sidewall is selectively removed by dry etching, and then the photoresist and the dummy gate are used as a mask for wet etching. Etching the semiconductor active layer to form the upper recess,
After the photoresist is removed once, the photoresist is applied again on the semiconductor active layer including the upper recess region to cue the dummy gate, and only the dummy gate is selected by wet etching using the photoresist as a mask. To form a lower recess region by wet etching the semiconductor active layer underneath to form a lower recess region, and form a gate electrode by vacuum evaporation and lift-off in the second recess region. Is.

In the method of manufacturing a semiconductor device having a two-step recess structure according to a third aspect of the present invention, the side etching amount is constant when the insulating film is side-etched to form the upper step recess in the conventional method. The insulating film is previously etched to a predetermined size on the substrate. That is, more specifically, the step of forming an insulating film having a size corresponding to the size of the upper recess on the semiconductor substrate, and the lower recess at the central portion of the insulating film on the substrate having the insulating film. A step of forming a resist having an opening corresponding to the size of, a step of etching the insulating film by using the resist as a mask and opening, and a step of etching the substrate by using the insulating film having the opening as a mask. A step of forming a recess, a step of removing the insulating film having the opening, and a step of etching the substrate using the resist as a mask to form a two-step recess including an upper step recess and a deeper step lower step recess And a step of forming a gate electrode on the lower recess of the two-step recess by vapor deposition lift-off using the resist.

In the method for manufacturing a semiconductor device having a two-step recess structure according to claim 4 of the present invention, PMGI (polymethyl glutar imide), which is difficult to mix with a resist, is used instead of the insulating film, and the PMGI side is used. The etching rate is controlled by exposure, and after that, development is removed by an alkaline developer to a desired width. That is, more specifically, a step of coating and exposing PMGI (polymethyl glutar imide) on a semiconductor substrate, and a resist pattern having an opening corresponding to the size of the lower recess on the substrate. Forming and etching the PMGI to form a PMGI pattern having the same degree of opening; etching the substrate using the PMGI as a mask to form a lower recess; and opening the PMGI. By developing, a step of expanding the size of the opening to a size corresponding to the upper recess, and etching the substrate using the PMGI as a mask to form a two-stage recess consisting of an upper recess and a deeper lower recess. And a step of forming a gate electrode on the lower recess of the two-step recess by vapor deposition lift-off using the resist. Is Dressings.

The method of manufacturing a semiconductor device having a two-step recess structure according to a fifth aspect of the present invention is to obtain a two-step recess structure by using light irradiation assisted etching without using side etching.

A method of manufacturing a semiconductor device having a two-step recess structure according to a sixth aspect of the present invention comprises a step of forming a resist pattern having an overhang shape at an opening forming portion on a semiconductor active layer on a semiconductor substrate, Next, a step of etching the semiconductor active layer using the upper opening of the resist pattern as a mask using photo-assisted etching to obtain a first recess, and subsequently etching only by a chemical reaction without using light to open the resist The process includes the step of using the lower part as a mask to obtain a second recess and a deeper first recess.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a two-step recess structure, which comprises the steps of forming a resist pattern having an overhang shape in an opening forming portion on a semiconductor active layer of a semiconductor substrate, A step of obtaining a second recess by performing etching only by a chemical reaction without light using the lower portion of the resist opening as a mask, and a step of performing the photo-assisted etching using the upper portion of the resist opening as a mask And a step of obtaining a recess.

[0023]

In the method of manufacturing a semiconductor device having a two-step recess according to the first and second aspects of the present invention, the two-step recess region is formed separately from the upper recess and the lower recess to control the recess size individually. Therefore, the two-step recess having the specified shape can be reliably formed, and the T-type gate electrode can be easily obtained.

In the method of manufacturing a semiconductor device according to a third aspect of the present invention, the insulating film is previously etched to a desired size,
Since the width of the upper recess is regulated, the shape of the second recess can be controlled with high accuracy, and the element performance becomes uniform. In the method for manufacturing a semiconductor device according to claim 4 of the present invention, the etching amount of PMGI can be controlled with high precision to a level of about 0.01 μm / sec by exposure. As a result, the recess shape can be made highly uniform.

In the method of manufacturing a semiconductor device having a two-step recess structure according to the fifth, sixth and seventh aspects of the present invention, the recess width is defined by the upper opening width using the overhang-shaped resist pattern as a mask. Since the first recess is formed by using assist etching, and the second recess is formed by wet etching so that the recess width is defined by the lower opening width of the resist pattern, the insulating film is side-etched to form the second recess. The second recess width does not vary as in the method of obtaining the recess.

[0026]

Embodiments of the present invention will now be described in detail with reference to the drawings. Embodiment 1 FIGS. 1 (a) to 1 (d) and FIGS. 2 (a) to 2 (d) are sectional views showing an embodiment of the invention of claim 1 in the order of steps. As shown in FIG. 1 (a), a semiconductor active layer 2 is formed on a GaAs semiconductor substrate 1, a photoresist 3 is applied on the semiconductor active layer 2, and an opening pattern corresponding to the upper recess width W2 and its A pattern corresponding to the gate length Lg is formed in the opening pattern.

Next, using the photoresist 3 patterned as described above as a mask, the semiconductor active layer 2 is etched by dry etching by the RIE method using SF6 + SiCl4 gas to form an upper portion as shown in FIG. 1 (b). The recesses corresponding to the portions on both sides of the recess region 4 are formed, and the dummy gate 5 is formed between the recesses, and then the photoresist 3 is removed. Since the width W2 of the upper recess region 4 is previously determined when the photoresist 3 is applied and the pattern is formed as shown in FIG. 1A, the recess shape is not constant due to the variation in the side etching amount of the spacer layer. The problems of the conventional method are solved.

Next, as shown in FIG. 1C, an insulating film such as a nitride film (SiN), an oxide film (SiO) or a nitrided oxide film (SiON) and a photoresist are provided in the upper recess region 4 as an insulator 6. And then planarize the surface, and then an opening pattern having a width wider than the width Lg of the dummy gate 5 and narrower than the width W2 of the upper recess is formed on the semiconductor active layer 2 including the upper recess region 4 in which the insulator 6 is buried. A resist 7 is formed by coating (FIG. 1 (d)). When the insulator 6 in the upper recess region 4 is formed of photoresist, it is necessary to prevent the photoresist in the recess from being developed at the time of developing the photoresist 7 formed thereon. Therefore, it is preferable to use different resist materials for both.

Next, after partially removing the insulator 6 in the upper recess region 4 by dry etching using the photoresist 7 as a mask as shown in FIG. 2A, the insulation remaining in the upper recess region 4 is removed. As shown in FIG. 2B, the lower recess 8 is formed by etching the dummy gate 5 and the semiconductor active layer 2 thereunder with the substance 6 as a mask with a tartaric acid-based or phosphoric acid-based etching solution. Two-step recess 9
Is obtained. After that, by depositing the gate electrode metal 10a in the two-step recess 9 and on the photoresist 7 by a vacuum evaporation method, and removing the unnecessary gate electrode metal 10a together with the photoresist 7 by lift-off, the structure shown in FIG.
The T-shaped gate electrode 10 is provided in the two-step recess 9 as shown in (c).
A semiconductor device having is obtained. The insulator 6 in the upper recess 4 may be removed by dry etching or wet etching to obtain the form shown in FIG. 2 (d).

In the first embodiment as described above, since the two-step recess region is formed by completely dividing into two steps of the upper recess region and the lower recess region, the conventional two-step recess forming method is used. As described above, variations in the side etching of the insulating layer do not cause variations in the recess shape of the upper and lower recesses, and the width of the lower recess formed first is widened by the etching for forming the upper recess. Therefore, the two-step recess can be stably formed. Further, since the insulator 6 is used to separate the formation of the upper recess and the lower recess, the lower portion is thinned by this insulator 6,
A T-shaped gate electrode having a thick upper portion can be easily obtained, and a semiconductor device having a small gate resistance and an improved withstand voltage and stable performance can be manufactured with high yield.

Example 2 FIGS. 3 (a) to 3 (d), 4 (a) to 4 (c) and 5 (a) to 5 (c)
FIG. 4 is a cross-sectional view showing one embodiment of claim 2 in the order of steps. As shown in FIG. 3A, first, an insulating film 1 such as SiN or SiON is formed on the upper surface of the semiconductor active layer 2 formed on the semiconductor substrate 1.
1 is formed, a photoresist 12 is applied on the insulating film 11, and patterning is performed. Then, using this photoresist 12 as a mask, the insulating film 11 in the other portion is removed by dry etching such as RIE (FIG. 3 (b)), and then the photoresist 12 is removed as shown in FIG. 3 (c). Then, a dummy gate 13 is formed on the semiconductor active layer 2. The width of the dummy gate 13 determines the length Lg of the gate electrode formed later.

Next, the insulating film 14 is formed on the entire surface of the dummy gate 13 and the semiconductor active layer 2 by plasma CVD using a material different from the insulating film forming the dummy gate 13, for example, SiO 2. To form. Then E
By removing the insulating film on both ends of the dummy gate 13 and the semiconductor active layer 2 by dry etching such as CR (Electron Cyclotron Resonance) etching, sidewalls 15 ′ having a desired width are formed on both sides of the dummy gate 13.
15 is formed as shown in FIG.

Next, as shown in FIG. 4B, a photoresist 16 is applied on the semiconductor active layer 2 so that the dummy gate 13 and the sidewalls 15 and 15 are located. Then, after selectively removing only the side walls 15 and 15 by dry etching by the RIE method, the semiconductor active layer 2 is etched with a tartaric acid-based or phosphoric acid-based etching solution using the photoresist 16 and the dummy gate 13 as a mask. , Upper recess 1 as shown in Fig. 4 (c)
7 and dummy gate 18 are formed.

After the photoresist 16 in FIG. 4 (c) is once removed, a new photoresist 19 is applied on the semiconductor active layer 2 so that the dummy gate 18 is cued as shown in FIG. 5 (a). To do. Next, using the photoresist 19 as a mask, only the dummy gate 13 is selectively removed by etching with a buffered hydrofluoric acid solution, and then the dummy gate 18 and the semiconductor active layer 2 thereunder are tartaric acid-based or phosphoric acid-based. The lower recess 20 is formed in the semiconductor active layer 2 as shown in FIG. 5 (b) by etching using a system etching solution, and the upper recess 17 and the lower recess 20 form a two-step recess region 21. To be

After that, the gate electrode metal 10a is vapor-deposited in the two-step recess region 21 and on the photoresist 19, and the unnecessary gate electrode metal 10a is lifted off together with the photoresist 19, so that as shown in FIG. ,
A semiconductor device having the gate electrode 10 formed in the two-step recess region 21 can be obtained.

In the second embodiment, as in the first embodiment, the two-step recess region is formed in two steps, that is, the upper recess region and the lower recess region. The two-step recess can be stably formed without the lower recess width changing as in the formation. Also, a photoresist 19 for forming the lower recess is formed.
Is formed so as to fill the space where the substrate is etched using the dummy gate 13 as a mask, the T-type gate electrode can be easily formed, and the gate resistance is small and the withstand voltage is improved. A semiconductor device can be manufactured with high yield.

The wet etching process using an etching solution such as tartaric acid-based or phosphoric acid-based or buffered hydrofluoric acid in Examples 1 and 2 is not limited to these, and may be dry etching. It is possible. Further, as the gate electrode metal, Al, WSi,
Ti / Al, Ti / Mo / Al, Ti / Mo / Ti / A
It is possible to use one or two or more kinds of laminated metal such as u.

Embodiment 3 An embodiment of a method of manufacturing a semiconductor device according to claim 3 will be described below with reference to the drawings. FIG. 6 is a sectional view of a compound semiconductor field effect transistor having a two-step recess type gate according to this embodiment, and FIG. 7 is a sectional view showing the main steps of its manufacturing method. In FIG. 6, 41 is a GaAs semiconductor substrate, and 46 is
Is an active layer formed on the semiconductor substrate 41, 44 is an upper recess, 45 is a lower recess, and 42a and 42b are ohmic electrodes. Further, in FIG. 7, 50 is an insulating film and 60 is a resist.

Next, the manufacturing method will be described. Figure (a)
As shown in FIG. 3, an insulating film such as SiO 2 is formed on the upper surface of the semiconductor substrate 41, a photoresist is applied on the insulating film, and this is patterned into a width of about 1 to 2 μm. By etching the insulating film, the size of 1 to 2 corresponding to the upper recess is obtained.
An insulating film 50 having a width of μm is formed. Next, as shown in FIG. 6B, a resist 60 is applied on this to a thickness of about 0.5 μm to form a resist 60 opening pattern having a width of about 0.5 μm corresponding to the gate electrode pattern. Next, as shown in FIG. 3C, the insulating film 10 is etched by wet etching using hydrofluoric acid or dry etching such as CHF3 + O2 gas using the resist 60 as a mask.
An opening corresponding to the gate electrode pattern is formed at 0. At this time, the opening width of the insulating film 50 is about 0.6 μm. Further, with the insulating film 50 as a mask, the semiconductor substrate 1 is etched by wet etching using tartaric acid or the like or dry etching using chlorine-based gas to a depth of about 0.1.
A recess 47 having a width of 0.5 μm and a width of about 0.5 to 0.7 μm is formed. Here, when wet etching is performed, it is etched in the depth direction, and at the same time, depending on the plane orientation of the substrate material, the etching solution, etc. Since the opening width of the recess 47 is wider than the 0.5 μm opening pattern,
From the viewpoint of improving the dimensional controllability, it is more desirable to use dry etching including etching of the insulating film. Next, as shown in FIG. 3D, the insulating film 50 having a width of about 1 to 2 μm is completely removed by hydrofluoric acid or the like. Next, as shown in FIG. 2E, the semiconductor substrate 1 is etched by wet etching using an etching solution such as tartaric acid, and the lower recess 47 is further lowered to a depth of about 0.3 μm and a width. Lower recess 45 of about 0.9 μm, depth of about 0.1 μm, width of about 1.4 to 2.4 μ
m upper recesses 44 are formed. Next, as shown in FIG. 6F, a metal for the gate electrode 43 such as Ti / Au is deposited and lifted off, so that a two-step recess gate can be formed as shown in FIG.

In the method of manufacturing a compound semiconductor device having a two-step recess in the present embodiment, the insulating film 50 is etched and left to have a desired size on the compound semiconductor substrate 41, and the resist 60 is applied thereto. The lower recess is formed by using the opening formed by the above step, the insulating film 50 is etched, and then the substrate 41 is etched to form the second recesses 44 and 45. The upper recess is formed according to the dimensions of the insulating film 50. Since the dimension of 44 is defined, the recess shape can be formed with good dimensional uniformity, and thus the element performance can be made uniform. Therefore, the non-defective rate can be improved, and the cost of the element can be greatly reduced.

Embodiment 4 FIG. 8 is a cross-sectional view of the main steps of an embodiment of a method for manufacturing a compound semiconductor field effect transistor device having a two-step recess type gate according to the fourth aspect of the present invention, which is the same as FIG. Shows the same thing, 51 is PMGI and 61 is a resist.

Next, the manufacturing method will be described. Figure (a)
As shown in FIG. 3, PMGI 51 is applied on the semiconductor substrate 41 to a thickness of about 0.1 μm, and 1 W / wavelength is used by using light having a wavelength of 300 nm or less, particularly 280 nm (Deep UV light).
The entire surface is exposed with an exposure energy of cm2. PMGI
Is not a scale that has a property of being difficult to mix with an optical exposure resist used in a later step, but has a property of being exposed to DeepUV light and being developed with an alkali developing solution like a general optical exposure resist. Is. Next, in FIG. 2B, the optical resist 61 is adjusted to about 0.5.
After being applied to a thickness of μm, the semiconductor substrate 41 is exposed / developed and patterned so as to have an opening having a width of about 0.5 μm to be a gate pattern. At this time, PMGI51
Is developed with an alkaline developer and opens.

Next, as shown in FIG. 6C, the wafer 41 is etched by wet etching using tartaric acid or the like, or dry etching using chlorine-based gas with the resist 61 as a mask, to a depth of about 0.1 μm. The recess 47 is formed. Here, as described above, it is preferable to use dry etching from the viewpoint of improving dimensional controllability. Next, Figure (d)
As described above, PMGI51 is developed with an alkali developer containing 2.38 weight percent of TMAH (tetramethylammonium hydroxide). At this time, by performing the exposure under the above-mentioned exposure conditions, it is possible to control the etching rate of PMGI with respect to the alkaline developing solution to a level of about 100 angstrom / sec. 8 μm) is a time for obtaining a desired value, for example, 0.2 μm to 0.3
If you want to perform extra etching in the horizontal direction of μm, 20
The PMGI resist 51 opening having a desired width can be obtained by immersing in the etching solution for about 30 seconds and performing development. Next, as shown in FIG. 3E, the wafer 41 is etched with tartaric acid or the like using the resist 61 as a mask, and the depth is about 0.
Lower recess 45 of 3 μm and width of about 0.9 μm, and upper recess 4 of depth about 0.1 μm and width of 1.4 to 2.4 μm.
4 is formed. The following is Ti, which is the metal for the gate electrode
By depositing / Au or the like and performing a lift-off method, the structure of FIG. 6 having the recess gate electrode 43 having a gate width of about 0.5 μm and a gate height of about 0.5 μm is formed.

In this embodiment, in the method of manufacturing a compound semiconductor field effect transistor device having a two-step recess, the upper-step recess dimension is defined by using an insulating film instead of an insulating film with high controllability. That is, the etching rate for the alkaline developer is 100.
Since PMGI that can be controlled to the angstrom / sec level is used, the dimensional uniformity of the recess shape can be greatly improved and the device performance can be made uniform, which can improve the yield rate and, in turn, the device cost. The effect is that you can do it.

Embodiment 5 FIG. 9 shows a method of manufacturing a semiconductor device according to an embodiment of claim 6, wherein 71 is a semiconductor substrate of GaAs or the like,
Reference numeral 78 is an active layer formed on the semiconductor substrate 71, 72 is an ohmic electrode forming source and drain electrodes, and 75.
Is the lower first recess, 76 is the upper second recess, 7
7 is a Schottky metal formed on the lower recess 75,
Reference numeral 84 is a resist. The dimensions of each part in the drawing are as follows: the active layer thickness is 2000 to 6000 angstroms, the resist opening width is 0.1 to 1 μm, and the difference between the upper opening width and the lower opening width is 0.1 to 0.3 μm. The depth of the first recess is 500 to 1500 angstroms, the depth of the second recess 6 is 1000 to 2000 angstroms, and the gate electrode width is the same as the upper opening width of the resist.

Next, the manufacturing method will be described. In FIG. 3A, the semiconductor active layer 7 formed on the semiconductor substrate 71.
After forming the source, drain and ohmic electrodes 72 on the gate electrode 8, a resist pattern 84 having an opening in a desired region of the portion where the gate Schottky electrode is formed is formed. Here, the resist pattern 84 has an overhang-shaped cross-sectional profile, that is, the upper opening A.
Is narrower and the lower opening B is wider.

Here, the overhang profile shape of the resist 14 can be easily obtained by using an image reversal resist or a negative type resist as the resist. This is because in these resists, the resist remains where the light hits, so when the light is applied to the resist from above, the light attenuates in the film thickness direction,
This is because the range exposed to light is narrowed at a deep position, and thus an overhang profile having a wide lower opening and a narrow upper opening can be easily obtained.

Further, this overhang-shaped resist 8
When forming 4, in order to improve the light shielding property,
If an arbitrary metal film is formed on the resist 84, the amount of the light reaching a deeper place becomes smaller and the overhang shape can be obtained more easily.

Then, the semiconductor active layer 78 is etched by using photo-assisted etching to obtain a first recess structure 75 having a depth of about 0.05 to 0.15 μm as shown in FIG. At this time, since the resist 84 has an overhang shape, etching is performed for the upper opening width A of the resist 84. Here, as shown in FIG. 12, the photo-assisted etching is a liquid 9 having a property that the semiconductor etching reaction proceeds only when excited by light.
1. For example, if the substrates 71 and 78 are GaAs, H2 S
O4 + H2 O, HCl aqueous solution, C6 H2 (OH) 2 (S
This is performed by irradiating the etched portion with light while being immersed in O3 Na) 2 + H2 O (tartaric acid) or the like. Alternatively, as shown in FIG. 13, if a gas that allows the semiconductor etching reaction to proceed only when excited by light, for example, if the substrates 71 and 78 are GaAs, room temperature C
It is also possible to carry out etching by placing the wafer in the l2 gas atmosphere 92 and irradiating the portion to be etched with light. In either case, the light used has a wavelength of 70
Light below 00 Angstroms can be used.

Next, a normal etching not using light is performed.
For example, sulfuric acid type etchant, H2 SO4: H2 O2: H
2 O = 3: 1: 1, by performing the above-mentioned overhang-shaped resist 84 on the substrate 71,
As shown in (c), a second recess 76 having a depth of about 0.1 to 0.2 μm can be obtained in addition to the first recess 75 further digging in the depth direction. At this time, since the etching of the second recess is performed using the lower opening portion of the resist 84 having a wide opening width B as a mask,
The etching is performed wider than the recess 75, and as a result, a two-step recess structure including the lower recess 75 and the upper recess 76 is obtained.

Next, as shown in FIG. 6D, a Schottky metal 77 is vapor-deposited on the entire surface and lift-off is performed to form a gate electrode 73, thereby obtaining a desired FET as shown in FIG.

In the manufacturing method of this embodiment as described above, after the first recess 75 is formed by using the light assist etching, the second recess 76 is then formed by using the wet etching.
Therefore, the width of the second recess 76 is determined by the width B of the lower opening of the photoresist pattern 84 and the property of isotropic etching of wet etching, and the second recess is formed by side etching the insulating film. There is no variation in the second recess shape as in the obtaining method. Also, the figure
In the steps of (b) to (c), the width of the first recess 75 is expanded by the lateral extension of the wet etching, but the width of the first recess 75 before the extension is defined by the photo-assisted etching. Since the rate of the spread is also determined by the type of etching, there is almost no variation in the recess shape due to the spread. Therefore, in this embodiment, it is possible to stably form a two-step recess structure that is uniform between lots and between wafers, and it is possible to make the element characteristics highly uniform and reduce the element cost.

Embodiment 6 FIG. 10 shows a method for manufacturing a semiconductor device according to an embodiment of the present invention. In Embodiment 5, the first recess 75 is first formed by photo-assisted etching, and then the normal recess is formed. The second recess 76 was formed by the wet etching of Example 1. In the sixth embodiment, as shown in FIG. 10, the formation of the second recess 76 by the wet etching is performed first (see FIG.
(in (b)), and then the first recess 75 is formed (in FIG. (c)) by photo-assisted etching. Also in this embodiment, as in the case of the fifth embodiment, the width of the second recess is determined by the width B of the lower opening of the photoresist pattern 84 and the ratio of the lateral etching spread due to the wet etching. There is no variation. Therefore, similar to the fifth embodiment, the two-step recess structure can be formed uniformly and stably between lots and wafers, and the device characteristics can be made highly uniform and the device cost can be reduced. Further, in this embodiment, since the lower first recess is formed after the upper second recess is formed, the width of the lower recess 75 is equal to the upper opening width A of the photoresist pattern 84. Therefore, the two-step recess shape can be more stably formed.

Embodiment 7 FIG. 11 shows a method for manufacturing a semiconductor device according to Embodiment 7 of the present invention. This Embodiment 7 relates to a method for obtaining the overhang resist profile shape shown in FIGS. It is a thing. As shown in FIG. 11A, first, an insulating film 90 having a tapered shape is formed, and then, as shown in FIG. 11B, a resist pattern 84 having an opening is provided in the insulating film 90. Next, heat treatment is performed at 150 to 200 ° C. to cause thermal sagging of the resist 84 and to fill the gap between the resist 84 and the insulating film 90, thereby obtaining the state of FIG. Next, the insulating film 90 is etched by a suitable etching method,
For example, remove by dipping in 30% HF aqueous solution,
The state shown in Figure (d) is obtained.

[0055]

As described above, according to the present invention,
The two-step recess area is divided into the upper recess area and the lower recess area.
Since the two-step recess is formed separately, the two-step recess can be stably formed without changing the lower recess width unlike the conventional two-step recess formation. Further, the T-type gate electrode can be easily obtained in the formation of the gate electrode, and the semiconductor device having stable performance can be manufactured with high yield.

In the method of manufacturing a compound semiconductor device having a two-step recess, the insulating film defining the upper recess dimension is etched to a desired size. Alternatively, instead of the insulating film, the etching rate is changed by exposure. Since PMGI that can improve the controllability of the device is adopted, the dimensional uniformity of the recess shape can be improved and the device performance can be made uniform, which can improve the yield rate and greatly reduce the device cost. There is an effect.

Further, according to the method of manufacturing a semiconductor device of the present invention, the first recess of the two-step recess structure is formed by photo-assisted etching. Therefore, the second recess is formed by using the side etch of the insulating film. There is an effect that the two-step recess structure can be manufactured with good uniformity without causing variations as in the conventional method of forming.

[Brief description of drawings]

1A to 1D are process sectional views showing an embodiment (embodiment 1) of a method for manufacturing a semiconductor device according to claim 1 of the present invention.

2A to 2D are process sectional views subsequent to FIGS. 1A to 1D of the first embodiment.

3 (a) to 3 (d) are process sectional views showing an embodiment (Embodiment 2) of the method for manufacturing a semiconductor device according to claim 2 of the present invention.

4A to 4C are process sectional views subsequent to FIGS. 3A to 3D of the second embodiment.

5 (a) to 5 (c) are process cross-sectional views subsequent to FIGS. 4 (a) to 4 (c) of the second embodiment.

FIG. 6 is a cross-sectional view of a two-stage recess type MOSFET which is a compound semiconductor device obtained by the methods of Examples 3 and 4 of the present invention and the method of Conventional Example 2.

FIG. 7 is a process sectional view showing an embodiment (embodiment 3) of the method for manufacturing a semiconductor device according to claim 3 of the present invention.

FIG. 8 is a process sectional view showing an embodiment (Embodiment 4) of the method for manufacturing a semiconductor device according to claim 4 of the present invention.

FIG. 9 is a process sectional view showing an embodiment (embodiment 5) of the method for manufacturing a semiconductor device according to claim 6 of the present invention.

FIG. 10 is a process sectional view showing an embodiment (embodiment 6) of the method for manufacturing a semiconductor device according to claim 7 of the present invention.

FIG. 11 is a process sectional view showing a manufacturing process for manufacturing an overhang-shaped resist pattern of Examples 5 and 6.

FIG. 12 is a diagram showing an example of photo-assisted etching in Examples 5 and 6.

FIG. 13 is a diagram showing an example of photo-assisted etching in Examples 5 and 6.

14A to 14C are process cross-sectional views showing a conventional method for manufacturing a semiconductor device.

15A to 15C are process cross-sectional views subsequent to FIGS. 6A to 6C showing a conventional method for manufacturing a semiconductor device.

FIG. 16 is a cross-sectional view of main manufacturing steps of another example of the conventional method for manufacturing a semiconductor device.

FIG. 17 is a cross-sectional view of main manufacturing steps of another example of the conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

1 Semiconductor Substrate 2 Semiconductor Active Layer 3 Photoresist 4 Upper Recess Region 5 Dummy Gate 6 Insulator 7 Photoresist 8 Lower Recess Region 9 2 Step Recess Region 10 Gate Electrode 11 Insulating Film 12 Photoresist 13 Dummy Gate 14 Insulating Film 15 Sidewall 16 Photoresist 17 Upper Recess Region 18 Dummy Gate 19 Photoresist 20 Lower Recess Region 21 Two-Step Recess Region 41 Wafer 42 Ohmic Electrode 43 Gate Electrode 44 Upper Recess 45 Lower Recess 46 Active Layer 47 Recess 50 Insulating Layer 60 Resist 51 PMGI 61 Resist 71 semiconductor substrate 78 semiconductor active layer 72 ohmic electrode 84 photoresist pattern 75 first recess 76 second recess 77 gate electrode 91 semiconductor etch only when excited by light Liquid that has the property of advancing reaction 92 Normal temperature Cl2 gas atmosphere

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Takahide Ishikawa 4-1-1 Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Corp. Optical & Microwave Device Laboratory (72) Inventor Yutaka Nagai 4-1-1 Mizuhara, Itami City, Hyogo Prefecture Address Mitsubishi Electric Corp. Optical / Microwave Device Laboratory

Claims (8)

[Claims] 1. A method of manufacturing a two-step recess type field effect transistor having a gate electrode in a lower recess of a two-step recess, wherein a photoresist is applied on a semiconductor active layer formed on a semiconductor substrate and patterned. Forming an opening at a position where a gate electrode is formed at a position where the upper recess is formed, and a dummy gate having a desired size by etching the semiconductor active layer through the opening using the photoresist as a mask. Forming recesses corresponding to both sides of the upper recess so as to leave the upper recess in the center, encapsulating an insulator in the two recesses of the upper recess, and the upper recess and the semiconductor active layer encapsulating the insulator. A step of forming an opening wider than the dummy gate on the surface of the substrate by applying and patterning a photoresist, The photoresist is used as a mask to perform a dry etching through the opening to partially remove the insulating material in the two recesses, and the remaining insulating film is used as a mask to etch the dummy gate and the semiconductor layer thereunder to form a lower recess. Forming a gate to form a two-step recess, and vacuum-depositing a gate electrode metal in a lower recess region of the two-step recess to lift off to form a gate electrode. Manufacturing method. 2. A method of manufacturing a two-step recess type field effect transistor having a gate electrode in a lower recess of a two-step recess, wherein a dummy gate made of an insulating film is formed on a semiconductor active layer formed on a semiconductor substrate. A step of forming a sidewall made of an insulating film made of a material different from that of the dummy gate on both sides of the dummy gate, and applying a photoresist on the semiconductor active layer on both sides of the sidewall, and then selecting only the sidewall Of the semiconductor active layer through the opening using the photoresist and the dummy gate as a mask to form recesses on both sides of the upper recess, and the upper recess. After coating a photoresist on the semiconductor active layer containing it, a dummy gate is selected using the photoresist as a mask. Of the gate electrode metal by vacuum vapor deposition of the gate electrode metal in the two-step recess region by lift-off the gate electrode. And a step of forming the semiconductor device. 3. A method of manufacturing a two-step recess type field effect transistor having a gate electrode in the lower recess of the two-step recess, wherein an insulating film having a size corresponding to the size of the upper step recess is formed on a compound semiconductor substrate. And a step of forming a resist having an opening corresponding to the size of the lower recess at the central portion of the insulating film on the substrate having the insulating film, and using the resist as a mask to form the insulating film. A step of etching and opening, a step of etching the substrate using the insulating film having the opening as a mask to form a lower recess, a step of removing the insulating film having the opening, and the substrate using the resist as a mask. By etching the upper recess and the deeper lower recess. 2
A method of manufacturing a semiconductor device, comprising: a step of forming a stepped recess; and a step of forming a gate electrode on the lower stepped recess of the two-stepped recess by vapor deposition lift-off using the resist. 4. A method of manufacturing a two-step recess type field effect transistor having a gate electrode in the lower recess of the two-step recess, wherein PMGI (polymethyl glutar imide) is applied and exposed on a compound semiconductor substrate. And a resist pattern having an opening corresponding to the size of the lower recess on the substrate, and the PMGI
To form a PMGI pattern having a similar opening, a step of etching the substrate using the PMGI as a mask to form a lower recess, and the opening of the PMGI to develop the opening. A step of expanding the dimension to a size corresponding to the upper recess, and a step of etching the substrate with the PMGI as a mask to form an upper recess, and a deeper lower recess.
A method of manufacturing a semiconductor device, comprising: a step of forming a stepped recess; and a step of forming a gate electrode on the lower stepped recess of the two-stepped recess by vapor deposition lift-off using the resist. 5. A method of manufacturing a two-step recess type field effect transistor having a gate electrode in the lower recess of the two-step recess, wherein the first recess, which is the lower step recess, is formed using photo-assisted etching. A method of manufacturing a semiconductor device, which comprises obtaining a recess structure. 6. The method of manufacturing a semiconductor device according to claim 5, wherein a step of forming a resist pattern having an overhang shape in the opening formation portion on the semiconductor active layer on the semiconductor substrate, and then using photo-assisted etching is used. Then, a step of etching the semiconductor active layer by using the upper opening of the resist pattern as a mask to obtain a first recess, and then etching only by a chemical reaction without using light as a mask of the lower opening of the resist is performed. A method of manufacturing a semiconductor device, comprising: a second recess; and a step of obtaining a deeper first recess. 7. The method of manufacturing a semiconductor device according to claim 5, wherein a step of forming a resist pattern having an overhang shape in the opening forming portion on the semiconductor active layer of the semiconductor substrate, and then a chemical reaction without using light. A step of obtaining a second recess by performing etching only by using the lower part of the opening of the resist as a mask, and a step of obtaining the first recess by performing photo-assisted etching using the upper part of the opening of the resist as a mask. A method of manufacturing a semiconductor device, comprising: 8. The method of manufacturing a semiconductor device according to claim 6, wherein the step of forming the overhang-shaped resist includes the step of forming an insulating film having a tapered cross-sectional shape, and the insulating film pattern portion. It is characterized by comprising a step of forming a resist pattern having an opening, a step of causing thermal sag by heating the resist to press-bond it to the side surface of the insulating film, and a step of etching and removing the insulating film. Manufacturing method of semiconductor device.