JPH0636622B2 - Time switch - Google Patents

Description

The present invention relates to a time switch, and particularly to a high-quality audio device,
The present invention relates to a method of configuring a one-stage link time switch (T1 stage time switch) for exclusively exchanging and distributing broadband information such as video conference images and color facsimiles.

[Conventional technology]

When accommodating only subscribers who use a plurality of time slots with a certain fixed length on the time division highway, a centralized arrangement for accommodating the time slots of one subscriber in consecutive time slots and the time distributed periodically There are distributed arrangements for accommodating in slots, one example of each is shown in FIGS. 2 and 3.

FIGS. 2 and 3 each show a case in which one frame has 16 time slots and each subscriber has four time slots. In the figures, A ₁ A ₂ A ₃ A ₄ , B ₁ B ₂ B ₃ B ₄ , C ₁ C ₂ C
₃ C ₄ , D ₁ D ₂ D ₃ D ₄ represent data of subscribers 1, 2, 3, ₄ respectively, and each delimiter represents a break of a time slot. In FIG. 2, the data of each subscriber is continuously arranged every four time slots, and in FIG. 3, the data of each subscriber is distributed every four time slots.

Next, since the address space of the memory required for time switching becomes equal to the number of time slots for one frame, 16 addresses are required for the memory in the centralized arrangement shown in FIG. Also, in the distributed arrangement shown in FIG.
Since the data of all subscribers (4 subscribers) is repeatedly displayed for each time slot, the address of the memory required for the time switch only needs to be 4 addresses, which should be reduced to 1/4 of that in FIG. You can

Now, consider a case where the time-sharing highways are centrally arranged. FIG. 4 shows an mN × mN T1 stage time switch in which N multiplex time switches are arranged in a matrix of m in the vertical direction and m in the horizontal direction. In FIG. 4, T "11 ', ~ T"1m', ~
Each of T ″ m1 ′ and T ″ mm ′ is an N-multiplexed time switch, and SEL21 and SEL2m are selectors. Time switch T "11 ', ~ T"1m', ~ T "m
1 ', to T "mm' are all N-multiplexed, and the memory address space has a capacity of N addresses.
1, IHW3m is input highway, OHW41, ~ OH
W4m is an output highway and has a 1-frame N time slot configuration.

[Problems to be solved by the invention]

The above-mentioned conventional mN × mN T1 stage time switch (4th
(Shown in the figure), the memory capacity required as a whole is m ² N because the address space per time switch T ″ is N and the number of time switches T ″ is m × m.
It has the disadvantage that the memory amount and the hardware amount rapidly increase as the switch size increases.

[Means for solving problems]

The time switch of the present invention has N multiple time switches vertically m.
In a time switch of mN × m′N arranged in a matrix of m and lateral m ′, the time switch performs switching in units of a plurality of time slots, the number of time slots serving as a switching unit is constant, and When all time slots are accommodated in consecutive time slots on the incoming highway and outgoing highway of the time switch, the incoming highway of the time switch cycles through all the time slots that are the switching units one by one. First time slot accommodation conversion means that is distributed in a distributed manner, and second time slot accommodation that centralizes all time slots of switching units distributed in the output highway of the time switch in the continuous time slots. And a conversion means.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the time switch of the present invention. In the figure, T51 to T5m are first time slot accommodation conversion means, which is a circuit for converting a centrally arranged time-division highway into a distributed arrangement, and a data memory for storing one frame of data on the time-division highway. , And a holding memory that stores in and out time slot replacement rule information. T61, to T6m are second time slot accommodating and converting means, which is a circuit for converting the distributed time-division highways into a centralized arrangement, a data memory for storing one frame of data on the time-division highways, and an input / output circuit. A holding memory that stores outgoing time slot replacement rule information. T'11, ~ T'1m, ~ T '
Each of m1 to T'mm is a time switch, and accommodates time-division highways arranged in a distributed manner. IHW31,
~ IHW3m is input highway, OHW41, ~ OHW
4 m is an output highway, and data of each subscriber is centrally arranged in a 1-frame N time slot configuration. F
HW71, ~ FHW7m, ~ BHW81, ~ BHW8m
Is a connection highway in which data of each subscriber is distributed in a 1-frame N time slot configuration.

Next, the operation of this embodiment will be described. For example, second
As shown in FIGS. 3 and 4, when one frame is composed of 16 time slots and the data of each subscriber is composed of 4 time slots, the time slot accommodation conversion means T51 to T5.
The data memory of m, T61, to T6m has 16 address spaces, and the time switches T'11, to T'1m, to T '.
The data memory of m1 to T'mm and the holding memory each have four address spaces. The time slot accommodation converting means T51, ...
The format is converted into the format shown in FIG. 3, and the time slot accommodation conversion means T61, to T6m perform the format conversion from FIG. 3 to FIG. Time switch T'11, ~
In T'1m, ~ T'm1, ~ T'mm, the highway of the format shown in Fig. 3 is accommodated, the data for 4 time slots is stored in the data memory, and the order of the data is changed according to the information in the holding memory. Output. The output highway data remains in the format shown in FIG. However, the order of An, Bn, Cn, Dn (n = 1 to 4) is variable, and the only requirement is that the format is such that data for four subscribers is repeatedly accommodated in every four time slots. .

Here, the memory amount required in the mN × mN T1 stage time switch shown in FIG. 1 is calculated. Each of the time slot accommodation conversion means T51, to T5m, T61, to T6m accommodates a time-division highway that is centrally arranged, so that one frame is required as the address space of the memory and N addresses are required. Time switch T'11,
Since ~ T'1m, ~ T'm1, ~ T'mm accommodate the distributed time-division highways, N addresses are not required. For example, assuming that the number of time slots as a switching unit, that is, the number of time slots used by one subscriber is k, the time switches T'11, to T'1.
N / k is sufficient as the memory address space required for m, ~ T'm1, ~ T'mm. This is because the data for all subscribers is included in the time slot for N / k frames, and if all the memory for N / k frames are prepared, the switching for all subscribers becomes possible. Therefore,
The memory amount (address space) required in the mN × mN T1 stage time switch is 2 mN addresses in total in the time slot accommodation converting means T51, ~ T5m, T61, ~ T6m, time switch T'11, ~ T'1m, ~. T'm
The total of 1 to T'mm is m ² N / k address, and the total is (2mN + m ² N / k) address.

Here, the memory amount (address space) required by the conventional mN × mN T1 stage time switch (shown in FIG. 4) and the mN × mN T1 stage time switch (shown in FIG. 1) of the present invention is compared. Then, the conventional time switch: the time switch of the present invention = m ² N: (m ² N / k + 2mN) = m: (m / k + 2) Therefore, if the value of the number of time slots k used by one subscriber is 2 or more and the value of the matrix size m is 3 or more, the memory capacity of the T1 stage time switch of mN × mN of the present invention is the same as the conventional mN ×. It can be made smaller than the memory amount of the T1 stage time switch of mN. For example, if the most general value “6” is used as the value of k, the memory amount reduction effect of the time switch of the present invention is 3 when m = 4 as compared with the conventional time switch.
3%, 50% when m = 6, and a large amount of memory, that is, a large amount of hardware can be reduced.

In this embodiment, the time switch matrix is set to m in both the vertical and horizontal directions and has the same value, that is, (m = m '). However, only one embodiment is shown here, and the matrix has the same vertical and horizontal directions. There is no need for a value (ie m ≠
m ').

〔The invention's effect〕

As described above, according to the present invention, the time switch performs switching in units of a plurality of time slots, the number of time slots serving as a switching unit is constant, and all the time slots in the switching unit are the input highway and the output highway of the time switch. When the time slots are accommodated in consecutive time slots above, all the time slots, which are switching units, are cyclically distributed one by one on the input side highway of the time switch, and the switching is distributed on the output side highway of the time switch. By allocating all time slots of a unit to consecutive time slots, mN ×
There is an effect that the amount of memory required for each time switch constituting the m′N time switch can be greatly reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a time switch showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of centralized highways, and FIG. 3 is a diagram showing an example of distributed highways. FIG. 1 is a block diagram showing an example of a conventional mN × mN T1 stage time switch. 11, ~ 1m, m1, ~ mm ... Time switch (T '),
21, ~ 2m ... selector (SEL), 31, ~ 3m ... input highway (IHW), 41, ~ 4m ... output highway, 51, ~ 5m, 61, ~ 6m ... time slot accommodation conversion means (T), 71, ~ 7m ... Connection highway (FH
W), 81 to 8 m ... Connection highway (BHW).

Claims (1)

[Claims] 1. A mN × m′N time switch in which N multiplex time switches are arranged in a matrix of m in the vertical direction and m ′ in the horizontal direction, and the time switch is switched in a unit of a plurality of time slots to form a switching unit. When the number of time slots is constant and all the time slots of the switching unit are accommodated in consecutive time slots on the time switch input side highway and the output side highway, the input side highway of the time switch is A first time slot accommodating and converting means for periodically arranging all the time slots, which are switching units, one by one,
A time switch comprising: second time slot accommodation conversion means for centrally arranging all time slots of a switching unit distributedly arranged on the output side highway of the time switch in the continuous time slot.