JPH0636450A - Motor control signal generating circuit - Google Patents

Abstract

PURPOSE:To provide a motor control signal generating circuit, which easily changes the respective set/reset values of motor acceleration/deceleration signals, for an optical disk reproducing device. CONSTITUTION:A computing circuit 22 computes the address difference of the contents of an address register 20 in which the contents are updated in synchronization with the clock signals extracted from an optical disk driven by a motor and an address register 21 in which the contents are updated in synchronization with a clock having a constant period. The circuit 22 outputs the result of the computations to a buffer register 23. A motor acceleration/ deceleration signal generating circuit 24 performs the respective set/reset of acceleration/deceleration signals based on the normal value of the address difference set in the buffer register 23 and the address difference set in a dip switch 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor control circuit for an optical disk reproducing apparatus, and more particularly to a motor control signal generating circuit capable of arbitrarily setting a prescribed value for control.

[0002]

2. Description of the Related Art FIG. 1 is an overall configuration diagram of an optical disk reproducing apparatus for a CD (Compact Disk). In the figure, 10 is a disk-shaped optical disk, which is rotated by a motor 11. 12 is a pickup, which is the EF stored in the optical disc
A digital audio signal modulated into an M (Eight to Fourteen Modulation) signal is read by a laser. Reference numeral 13 denotes a servo control circuit, which is a focus servo that causes the laser to be focused on the optical disk on the pickup 12, and a tracking servo that prevents the pickup 12 from moving to the left and right from a track formed in a spiral on the optical disk 10. And the CLV (Cons
The rotation servo that controls the rotation speed of the motor 11 is performed so that it becomes tant Linear Verocity). 14 is the above EF
Reference numeral 15 denotes an EFM signal demodulation circuit for demodulating the EFM signal which has been synchronously detected and writing it in the RAM 16.
Demodulation of this EFM signal and writing to RAM16 are EF
It is performed in synchronization with the bit clock signal extracted from the M signal. Reference numeral 17 is a correction circuit for an error that has occurred in the EFM signal on the transmission line, and RAM is synchronized with the crystal system clock signal.
The data demodulated from 16 is read, corrected, and then written in the RAM 16 again. Reference numeral 18 denotes an audio output circuit, which reads the data corrected in synchronization with the crystal system clock signal from the RAM 16 and reproduces and outputs the audio signal, or outputs the data as it is. These R
A write / read address for the AM 16 is generated by the address circuit 19.

By the way, the bit clock signal contains jitter whose period varies due to uneven rotation of the motor 11 and warp of the optical disk 10. Therefore, if the signal obtained by demodulating the EFM signal is reproduced as it is, jitter is included. Therefore, in the above reproducing apparatus, the demodulated signal is once written in the RAM 16 and then read in synchronization with the crystal system clock signal having a constant period to remove the jitter from the demodulated EFM signal for reproduction.

Furthermore, until the PLL is disengaged by a search or the like and the PLL is locked after the search and the rotation servo is stabilized, a write / write operation is generated by a motor control signal generation circuit in synchronization with a crystal system clock signal having a constant cycle. The motor 11 is configured so that the write address generated in synchronization with the bit clock signal precedes the read address with a constant difference.
Control the rotation speed of. The rotation control of the motor 11 is performed in addition to the rotation servo for CLV.

FIG. 6 is a block diagram showing the configuration of a motor control signal generating circuit incorporated in the address circuit 19. In the figure, 60 is an address register in which a write address generated in synchronization with a bit clock signal is set, and 61 is an address register in which a write / read address generated in synchronization with a crystal system clock signal is set. is there. Reference numeral 62 denotes an arithmetic circuit, which takes in addresses from the bit clock signal system address register 60 and the crystal clock signal system address register 61, calculates the address difference, and outputs it to the 4-bit buffer register 63. Reference numeral 64 denotes a motor acceleration / deceleration signal generation circuit that sets and resets each acceleration / deceleration signal of the motor when the specified value of the preset address difference and the actual address difference of the buffer register 63 match, The acceleration / deceleration signal is output to the servo control circuit 13.

The operation of the motor acceleration / deceleration signal generation circuit 64 will be described with reference to FIGS. 4 (a) and 4 (b) using a specific example. The reference value of the address difference at this time is 6.5. First, as shown in (a), the write speed of the demodulated signal becomes slow due to some factor, and the bit clock signal system address register 60 and the crystal system address register are
When the address difference of 61 falls below the standard value and becomes the specified value 3,
The signal generation circuit 64 sets the motor acceleration signal. As a result, the speed of reading data from the disk 10 is increased, the speed of writing the demodulated signal is increased, and the address difference is increased. And when the address difference reaches the specified value 7,
The signal generation circuit 64 resets the acceleration signal. Also,
As shown in (b), when the writing speed of the demodulated signal becomes faster and the address difference exceeds the reference value and reaches the specified value 10, the signal generation circuit 64 sets the motor deceleration signal. As a result, the reading of data from the disk 10 becomes slower, the writing speed of the demodulation signal becomes slower, and the address difference decreases. Then, when the address difference reaches the specified value 6, the signal generation circuit 64 resets the deceleration signal.

FIG. 7 shows a circuit for setting / resetting the motor deceleration signal in the signal generating circuit 64, which operates in positive logic. In the figure, a logic circuit 70 surrounded by a broken line outputs a voltage on the Hi side at a logic level when a decimal value 6 is input as a 4-bit digital signal. The logic circuit 71 surrounded by the broken line is 4
H when the decimal value 10 is input as a bit digital signal
Outputs the voltage on the i side. The inputs of the logic circuits 70 and 71 are both connected to the buffer register 63. 72 is RS
It is a flip-flop, and the reset terminal R has a logic circuit 70.
Is input, the output of the logic circuit 71 is input to the set terminal S, and the deceleration signal is output to the output terminal Q.

As described above, the set / reset value of the motor deceleration signal is set by the logic gate, and similarly, the set / reset value of the acceleration signal is set by the logic gate. Therefore, in the motor control signal generation circuit of the optical disc reproducing apparatus, the set / reset values of the motor acceleration / deceleration signals are fixed and cannot be changed. For this reason, depending on the type of motor used, even if it exceeds the reset value due to its inertia, it will rotate too far, and eventually the control signal in the opposite direction will be set, and this will be repeated many times. There was a problem that it did not converge. For this reason, the motors that can be actually used are limited.

[0009]

As described above, the conventional motor control signal generation circuit has a fixed set / reset value for each of the acceleration / deceleration signals, so that the motors that can be used are limited. Therefore, even if a designer tries to design many optical disk playback devices (such as low-end models or high-end models) by using an integrated circuit having a motor acceleration / deceleration signal generation circuit, there is a limitation on the type of motor. There was a problem of being done.

The present invention has been made to solve the above problems, and an object thereof is to provide a motor control signal generation circuit for an optical disk reproducing apparatus capable of easily changing set / reset values of respective acceleration / deceleration signals of a motor. Is to provide.

[0011]

A motor control signal generating circuit according to the present invention includes a first address register whose contents are updated in synchronization with a clock signal extracted from a storage medium driven by a motor, and a constant period. A second address register whose contents are updated in synchronization with a clock signal having
Arithmetic means for calculating the difference between the contents of the first and second address registers, a buffer register for storing the arithmetic result of the arithmetic means, and means for arbitrarily setting the first to fourth prescribed values. , Means for generating a motor acceleration signal when the content of the buffer register is less than or equal to a first specified value, and canceling the motor acceleration signal when the content of the buffer register is greater than or equal to a second specified value; When the content is equal to or more than the third specified value, a motor deceleration signal is generated, and when the content of the buffer register is equal to or less than the fourth specified value, the motor deceleration signal is released.

[0012]

With the motor control signal generation circuit having the above-described structure, the value of generation / release of the acceleration / deceleration signal of the motor can be arbitrarily set, and the motor is optimized by setting the value according to the performance of the motor. Can be controlled.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings.

FIG. 2 is a block diagram corresponding to FIG. 6 of a motor control signal generating circuit according to an embodiment of the present invention. This circuit is incorporated in the address circuit 19 of the optical disk reproducing apparatus described with reference to FIG. It is what is done. In the figure, 20 is an address register in which a write address generated in synchronization with the bit clock signal is set,
21 is write / generated in synchronization with the crystal system clock signal
It is an address register in which a read address is set. This bit clock signal is extracted from the EFM signal stored in the optical disc 10 rotated by the motor 11 of the optical disc reproducing apparatus. Reference numeral 22 denotes an arithmetic circuit, which takes in addresses from the bit clock signal system address register 20 and the crystal clock signal system address register 21, calculates the address difference, and outputs it to the 4-bit buffer register 23. Reference numeral 24 is a motor acceleration / deceleration signal generation circuit, and a specified value of the address difference is set by 4-bit DIP switches 25, 25 .... The motor acceleration / deceleration signal generation circuit 24 sets and resets the acceleration / deceleration signals of the motor according to the difference between the address difference set in the buffer register 23 and the specified value to accelerate / decelerate.
The deceleration signal is output to the servo control circuit 13 shown in FIG.

The motor acceleration / deceleration signal generation circuit 24 is provided with four digital comparators in order to compare the address difference set in the buffer register 23 with the specified value of the address difference when setting / resetting each acceleration / deceleration signal. ing. FIG. 3 is a circuit diagram showing a connection state of the digital comparator 30, the buffer register 23 and the DIP switch 25. Digital comparator 30 has A0-A3 and B0-B
3 sets of 2 4-bit digital input terminals,
Depending on the magnitude of the digital value A input to A3 and the digital value B input to B0 to B3, A> B, A = B, A <B
Detect the state of. Then, the logic level Hi-side voltage is output to the output terminal corresponding to the detection state, and the Low-side voltage is output to the non-corresponding terminals. Further, the output terminals of A> B and A = B are connected to the input of an OR circuit (not shown) so that the state of A ≧ B can be detected. Also, A ≦ B
When detecting the state of, the output terminal O of A <B and A = B
It may be input to the R circuit. The input terminals of A0 to A3 are connected to the dip switch 25, and the input terminals of B0 to B3 are connected to the buffer register 23. The state of the DIP switch 25 in the figure corresponds to a digital value of "1010" in positive logic, and this digital value can be set to an arbitrary value by changing the connection of each of the four contacts of the DIP switch. Further, the digital value input to the input terminals of A0 to A3 may be set by a microcomputer instead of the DIP switch 25.

The operation of the motor control signal generating circuit shown in FIG. 2 will be described with reference to FIGS. 4 (a) and 4 (b) using a concrete example. The reference value of the address difference at this time is 6.5. First, as shown in (a), due to some factors, EFM
Demodulation of signal The writing speed of the signal becomes slower, and bit clock signal system address register 20 and crystal system address register
When the address difference of 21 falls below the reference value and becomes equal to or less than the specified value 3 set in the first digital comparator 30, the signal generation circuit 24 sets the motor acceleration signal. As a result, the reading of data from the disk 10 becomes faster, so the writing speed of the demodulation signal to the RAM 16 of FIG. 1 becomes faster and the address difference increases. Then, when the address difference becomes equal to or larger than the specified value 7 set in the second digital comparator 30, the signal generation circuit 24 resets the acceleration signal. Further, as shown in (b), when the writing speed of the demodulated signal becomes faster and the address difference exceeds the reference value and becomes equal to or larger than the specified value 10 set in the third digital comparator 30, the signal generation circuit 24 causes the motor deceleration signal. Set. As a result, the reading of data from the disk 10 becomes slower, the writing speed of the demodulated signal to the RAM 16 becomes slower, and the address difference decreases. Then, when the address difference reaches the specified value 6 set in the fourth digital comparator 30, the signal generation circuit 24 resets the deceleration signal.

By the way, if the address difference is difficult to converge to the reference value by setting the specified value of the address difference due to the inertia of the motor 11, the specified value of reset is set so that the acceleration / deceleration signal is released earlier than in the above example. Should be changed. However, in order to prevent both the acceleration signal and deceleration signal from being set, the deceleration signal is reset to a larger value than the specified value to set the acceleration signal, and the deceleration signal is set to a value larger than the specified value to reset the acceleration signal. It is necessary to set a large specified value to set. For example, the conceptual diagram of setting / resetting the acceleration / deceleration signal of the motor when the specified value for resetting the acceleration signal is changed from 7 to 6 and the specified value for resetting the deceleration signal is changed from 6 to 7 is shown in FIG. (A) and (b)
become that way.

Since the specified value of the address difference is set by the DIP switch or the microcomputer, it can be easily changed. Therefore, since the motor control signal generation circuit can select the specified value of the address difference in consideration of the characteristics of the motor to be controlled, it is possible to optimally control the motor so that the address difference easily converges to the reference value. .

[0019]

As described above, according to the present invention, it is possible to provide a motor control signal generation circuit for an optical disk reproducing apparatus, which can easily change the set / reset value of each acceleration / deceleration signal of the motor.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of an optical disk reproducing device.

FIG. 2 is a block diagram of a motor control signal generation circuit according to an embodiment of the present invention.

FIG. 3 is a connection diagram of a digital comparator, a buffer register, and a DIP switch according to an embodiment of the present invention.

FIG. 4 is a conceptual diagram of setting / resetting a motor acceleration / deceleration signal.

FIG. 5 is a conceptual diagram of setting / resetting a motor acceleration / deceleration signal.

FIG. 6 is a block diagram showing a configuration of a conventional motor control signal generation circuit.

FIG. 7 is a circuit diagram of a conventional motor deceleration signal set / reset circuit.

[Explanation of symbols]

10 ... Optical disc, 11 ... Motor, 12 ... Pickup, 23 ...
Buffer register, 25 ... DIP switch, 30 ... Digital comparator.

Claims (2)

[Claims] 1. A first content whose content is updated in synchronization with a clock signal extracted from a storage medium driven by a motor.
Address register, a second address register whose contents are updated in synchronism with a clock signal having a constant period, a calculating means for calculating the difference between the contents of the first and second address registers, and the above calculation. A buffer register for storing the calculation result of the means, a means for arbitrarily setting the first to fourth specified values, and a motor acceleration signal is generated when the content of the buffer register is less than or equal to the first specified value. , Means for releasing the motor acceleration signal when the content of the buffer register is greater than or equal to the second specified value, and a motor deceleration signal when the content of the buffer register is greater than or equal to the third specified value, and the content of the buffer register And a means for canceling the motor deceleration signal when is less than or equal to the fourth specified value. 2. The second specified value is set to be larger than the first specified value, the third specified value is set to be larger than the fourth specified value, and the third specified value is set to be larger than the first specified value. 4. The specified value of No. 4 is set to be large, and the third specified value is set to be larger than the second specified value.
The motor control signal generation circuit described in 1.