JPH05290502A - Motor control device - Google Patents

Abstract

PURPOSE:To provide a motor control device which dispenses with a PWM transforming circuit nor a phase compensating circuit. CONSTITUTION:A difference between values of a write address counter 7 and a read address counter 14 and a comparator circuit 20 detects whether the difference value exceeds a prescribed value or not. The output of the circuit 20 is applied to a motor driving circuit 10 through a switching circuit 9 and to a motor 11 in order so as to give a driving force to a disk 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor controller for an optical disk, and more particularly to a motor controller suitable for reproducing an optical disk on which a digitally modulated information signal is recorded.

[0002]

2. Description of the Related Art In recent years, a motor controller is an optical disk,
In particular, it is often used in compact disc playback devices.
Hereinafter, a conventional motor control device will be described.

FIG. 2 is a block diagram of the conventional motor control device. In FIG. 2, the disc 1
Is an EFM-modulated CD format information signal recorded on a concentric or spiral information track. The reproducing head 2 functions to narrow down the laser light on this information track.

EFM read by the reproducing head 2
The modulated information signal is sent to the waveform shaping circuit 3 and binary shaped. At this time, the slice level is controlled so that the ratio of the high level to the low level is just 1: 1 by utilizing the direct-current fluctuation-free property which is a characteristic of the EFM modulation. The output of the waveform shaping circuit 3 is sent to the PLL circuit 4, the D terminal of the D flip-flop circuit 5, and the shortest cycle detection circuit 6.

The PLL circuit 4 utilizes the fact that the cycle of the output of the waveform shaping circuit 3 is an integral multiple of 1T (= 1 / (4.3218 * 10 ⁶ )) and reproduces the output frequency of the least common multiple of that frequency. Outputs clock signal Spck. This recovered clock signal
Spck is a clock input terminal of the D flip-flop circuit 5, a demodulation circuit 8 and a write address counter 7 (hereinafter,
WAC7).

The D flip-flop circuit 5 synchronizes the output of the waveform shaping circuit 3 with the reproduced clock signal Spck,
It is sent to the demodulation circuit 8. The demodulation circuit 8 synchronizes the output of the D flip-flop circuit 5 with the reproduced clock signal Spck in phase and performs EF.
M demodulate. When this EFM demodulation is possible, that is, PLL
When the circuit 4 is phase-synchronized with the input signal and can be identified as an EFM-modulated signal, the demodulation enable signal Svalid is sent to the switching circuit 9. The switching circuit 9 is connected to the B terminal when the demodulatable signal Svalid is output, and is connected to the A terminal when it is not output.

When the PLL circuit 4 is not phase-synchronized with the input signal at the time of start-up, that is, when the demodulation enable signal Svalid is not output, the shortest period detection circuit 6 detects the shortest period of EFM modulation and The cycle is controlled to be exactly 3T. That is, the shortest cycle is detected from the output of the waveform shaping circuit 3, the shortest cycle detection circuit 6 detects how much the cycle has a difference of 3T, and the result is sent to the switching circuit 9. Since the demodulation enable signal Svalid is not output to the switching circuit 9, the switching circuit 9 is connected to the terminal A and applies a driving force to the disk 1 via the motor drive circuit 10 and the motor 11, so that the shortest period is just 3
Control to reach T. As a result, the cycle of the signal input to the PLL circuit 4 is driven into the range in which the PLL circuit 4 can be locked.

On the other hand, when the demodulatable signal Svalid is output, the output of the demodulation circuit 8 is written to the address on the RAM 12 designated by the WAC 7. This RAM12
Is stored in the RAM 12 in accordance with the read address designated by the read address counter 14 (hereinafter abbreviated as RAC 14) generated by the reference clock signal Sref generated by the crystal oscillation output from the reference signal generation circuit 13.
Is read out from and is sent to the decoding circuit 15.

The decoding circuit 15 decodes the read data read from the RAM 12, and the D / A conversion circuit 16
And output as a voice signal.

The address data output from the WAC 7 and the RAC 14 is sent to the subtraction circuit 17 where the difference is calculated and the difference data is output. This difference data is sent to the PWM conversion circuit 18, and this PWM conversion circuit 18 converts the difference data into a voltage level by an engaged low-pass filter (not shown). The output of the PWM conversion circuit 18 is sent to the phase compensation circuit 19 and, when the demodulatable signal Svalid is output, to the disk 1 via the motor drive circuit 10 and the motor 11 via the B terminal of the switching circuit 9. Write address and RAC output by WAC7
The rotation phase of the motor 11 is controlled so that the difference between the read addresses output by 14 becomes constant.

[0011]

However, in the above conventional configuration, the PWM conversion circuit 18 and the phase compensation circuit 19 are provided.
Therefore, there is a problem in that the circuit scale becomes large.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a motor control device that does not require a PWM conversion circuit or a phase compensation circuit.

[0013]

To achieve this object, a motor controller according to the present invention comprises a reproducing head for reading out an information signal from a disk in which an information signal containing a periodic component is recorded, and this information signal. A waveform shaping means for binary-shaping, and a rotation error detecting means for detecting a rotation error of the disk from the output of the waveform shaping means and outputting a rotation error signal.
Extracting the periodic component from the output of the waveform shaping means,
PLL means for extracting the reproduction clock signal, synchronization means for synchronizing the output of the waveform shaping means with the reproduction clock signal, and demodulation of the output of the synchronization means if possible according to a predetermined conversion rule. A demodulation means for outputting a demodulatable signal and demodulation data, a storage means for storing the demodulation data in a predetermined area, and a writing address for deciding an address for writing the demodulation data in the storage means according to the reproduction clock signal. The generation means, the reference signal generation means for outputting the reference clock signal, the read address generation means for determining the address for reading the demodulated data from the storage means in accordance with the reference clock signal, and the read address generation means are designated. If the difference between the address and the address specified by the write address generating means exceeds the specified range, the acceleration command signal or deceleration command signal A switching means for switching between the acceleration command signal or the deceleration command signal and the rotation error signal according to the demodulatable signal, and a motor for applying a driving force to the disk according to the output of the switching means. Is equipped with.

[0014]

According to the present invention, when the difference of the address data becomes larger than the predetermined value, the comparison means detects the difference and the motor is fully decelerated, and when the difference is smaller than the predetermined value. Detects this by comparison means,
By fully accelerating, the motor can be controlled within a range that does not exceed the capacity of the RAM that constitutes the storage means, so that the circuit configuration is simplified.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram of a focus control device according to an embodiment of the present invention. In FIG. 1, a disk 1, a reproducing head 2, a waveform shaping circuit 3, P
LL circuit 4, D flip-flop circuit 5, shortest period detection circuit 6, WAC 7, demodulation circuit 8, switching circuit 9, motor drive circuit 10, motor 11, RAM 12, reference signal generation circuit 13, RAC 14, decoding circuit 15, D / A conversion circuit 1
6 and the subtraction circuit 17 are the same as those in FIG.

The difference data obtained in the subtraction circuit 17 is sent to the comparison circuit 20, and when it is larger than the predetermined value a, the deceleration output having the amplitude + b is supplied to the B terminal of the switching circuit 9. On the contrary, when the value is smaller than the predetermined value -a, the acceleration output having the amplitude -b is supplied to the B terminal of the switching circuit 9. When this signal outputs the demodulatable signal Svalid, the drive force is applied to the disk 1 via the motor drive circuit 10 and the motor 11, and the internal capacity of the RAM 12 falls within a predetermined range.
The motor is controlled so that it falls within the range from a to + a. Here, the value ± a is set within a range where the RAM 12 does not overflow or underflow.

As described above, according to this embodiment, the output of the subtraction circuit 17 is compared by the comparison circuit 20, and the motor 11 is accelerated and decelerated so that the contents of the RAM 12 do not overflow or underflow, so that a stable disk is obtained. 1 can be reproduced. The comparison circuit 20 can be configured by a magnitude comparator, and the PWM conversion circuit and the phase compensation circuit, which are large in circuit scale and used in the conventional example, are unnecessary.

In the above embodiment, the shortest period is detected and the activation is performed. However, the longest period may be detected, or the frame synchronization signal is detected, and the speed control or the phase control is performed by this. Good.

[0020]

As described above, according to the present invention, by providing the comparing means for comparing the write address and the read address,
Since the rotation speed of the disk can be kept within a predetermined range so that the RAM constituting the storage means does not overflow or underflow with a simple circuit configuration, the cost can be kept low.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing the configuration of a motor control device according to an embodiment of the present invention.

FIG. 2 is a block schematic diagram showing a configuration of a motor control device in a conventional example.

[Explanation of symbols]

 1 Disk 2 Playback Head 3 Waveform Shaping Circuit 4 PLL Circuit 5 D Flip-Flop Circuit 6 Shortest Cycle Detection Circuit 7 Write Address Counter 8 Demodulation Circuit 9 Switching Circuit 10 Motor Drive Circuit 11 Motor 12 RAM 13 Reference Signal Generation Circuit 14 Read Address Counter 20 Comparison circuit

Claims (1)

[Claims] 1. A reproducing head for reading out an information signal from a disk on which an information signal containing a periodic component is recorded, a waveform shaping means for binary-shaping the information signal, and an output of the waveform shaping means for forming the disk. A rotation error detection unit that detects a rotation error and outputs a rotation error signal, and extracts the periodic component from the output of the waveform shaping unit,
PLL means for extracting a reproduction clock signal, synchronization means for synchronizing the output of the waveform shaping means with the reproduction clock signal, and demodulation of the output of the synchronization means if possible according to a predetermined conversion rule. A demodulation means for outputting a demodulatable signal and demodulation data, a storage means for storing the demodulation data in a predetermined area, and a writing address for deciding an address for writing the demodulation data in the storage means according to the reproduction clock signal. The generating means, the reference signal generating means for outputting the reference clock signal, the read address generating means for determining the address for reading the demodulated data from the storage means in accordance with the reference clock signal, and the read address generating means are designated. If the difference between the address and the address specified by the write address generating means exceeds the specified range, the acceleration command signal or deceleration Command means for outputting a command signal, switching means for switching between the acceleration command signal or the deceleration command signal and the rotation error signal according to the demodulatable signal, and a driving force is applied to the disk according to the output of the switching means. A motor control device comprising a motor.