JPH0635799A - Memory area designating system - Google Patents

Abstract

PURPOSE:To make the extension use of memory capacity effective by enabling the switching so as to select a desired storage area of a memory even when a DMA request is received from another device at the time of executing a DMA transfer, regarding a memory area designating system. CONSTITUTION:This system is provided with a CPU 1, a memory 2, plural devices 3-0,..., 3-n and a DMA controller 4. The system is provided with a memory area designating register 5 where the prescribed value for the memory access from the CPU 1 is set, memory area designating registers 6-0,..., 6-n, provided corresponding to every channel of the DMA controller 4, where each prescribed value is set, and a selection part 7 selecting the storage area of the memory 2 based on the output from these memory area designating registers 6-0,..., 6-n.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention makes it possible to expand and use the memory capacity by switching the memory between a basic area and a plurality of expansion areas, and to transfer data between the memory and a plurality of devices. The present invention relates to a memory area designating method of a memory area in a system which performs direct memory access transfer (DMA transfer).

[0002]

2. Description of the Related Art FIG. 4 is a block diagram for explaining a conventional memory area designation method. The system shown in FIG. 4 has a CPU 101, a basic storage area M ₀ and a plurality of extended storage areas M _{1 to} M. Memory (MM) 102 having _n and a plurality of devices 103-1, 103-2, direct memory access controller (DMA controller) 104, memory area designation register (MNR) 105, decoder 1
It is configured with 73.

Here, the CPU 101 controls the system.
To the memory area designation register 105.
However, it is possible to set a predetermined value. Me
The memory 102 stores programs and data.
It has a plurality of storage areas as described above. Device 103-
1, 103-2 transfer data to and from the memory 102
The device 103-1 is a basic memory of the memory 102.
Memory area M₀Device 103-
2 is an extended storage area (for example, M ₁) With
Data is transferred between them.

The DMA controller 104 includes a memory 10
2 and the respective devices 103-1 and 103-2 are controlled. The memory area designation register 105 includes a memory 102 and devices 103-1 and 103-2.
When transferring data to and from the CPU 101
A signal for selecting one of the storage areas of the memory 102 is output by setting a predetermined value from. The decoder 173 is for decoding the signal from the memory area designation register 105 to generate a signal for selecting a desired storage area in the memory 102.

With this configuration, when data transfer is performed between the memory 102 and the plurality of devices 103-1 and 103-2 by DMA transfer, the value of the memory area designation register 105 set by the CPU 101 is decoded. The memory capacity is expanded and used by switching the memory area using the signal as a select signal.

[0006]

However, in such a conventional method, as shown in FIG. 5, for example, when the DMA transfer in the cycle steal mode between the memory 102 and the device 103-1 is executed, the device 103-2 performs the DMA transfer. When the request is received [see (a) of FIG. 5], the DMA between the device 103-1 and the memory 102, and the device 103-2 and the memory 1
The operation of the CPU 101 may enter only one step during the DMA of 02 [see (b) of FIG. 5] As described above, when the operation of the CPU 101 enters only one step, the memory area designation register 105 Since rewriting cannot be performed, in this case, there is a problem that only a fixed area can be used as the memory area.

The present invention was devised in view of such a problem, and even when a DMA request is received from another device during execution of a DMA transfer, it is possible to switch to select a desired storage area of the memory. Thus, it is an object of the present invention to provide a memory area designating method capable of effectively expanding and using the memory capacity.

[0008]

FIG. 1 is a block diagram of the principle of the present invention. In FIG. 1, 1 is a CPU, and this CPU 1 controls the system. 2 is a memory (MM), and this memory 2 is a basic storage area M
_{It has 0} and a plurality of extended storage areas M _{1 to} M _n . Reference numerals 3-0, ..., 3-n are devices as data transfer partners with the memory 2.

Reference numeral 4 is a DMA controller, and this DM
The A controller 4 includes a memory 2 and a plurality of devices 3-0,
, And 3-n for controlling data transfer. Reference numeral 5 is a memory area designation register, and this memory area designation register 5 is set with a predetermined value for memory access from the CPU 1. 6-0, ...,
6-n is a memory area designating register, and the memory area designating registers 6-0, ..., 6-n are provided corresponding to every 4 channels of the DMA controller and are set to predetermined values respectively. is there.

Reference numeral 7 is a selection unit for selecting a storage area of the memory. More specifically, the selection unit 7 stores the data in the memory 2 based on the outputs from the memory area designation registers 6-0, ..., 6-n. This is for selecting an area, and this selecting unit 7
, Gates 71, 72-0, ..., 72-n and decoder 7
3 and 3. Here, the gates 71 and 7
2-0, ..., 72-n are provided corresponding to each memory area designation register 5, 6-0, ..., 6-n. The decoder 73 includes gates 71, 72-0, ...
The output from 72-n is decoded to generate a signal for selecting a desired storage area in the memory 2.

The memory area designation registers 5, 6-
Setting of a predetermined value to 0, ..., 6-n is performed through the CPU 1,
It is carried out in advance (the above is claims 1, 2 and 3).

[0012]

According to the above-mentioned memory area designating method of the present invention, as shown in FIG.
As shown in FIG. 2, switching is performed so as to select one of the storage areas of the memory 2. At that time, a predetermined value is set in the memory area designation register 5 for the memory access from the CPU 1, and the memory area designation register 6 is set. Is D
A predetermined value is set for each channel of the MA controller 4 and a predetermined value is set for each channel.
A memory storage area is selected based on the outputs from 6-0, ..., 6-n. That is, the outputs from the memory area designating registers 5, 6-0, ..., 6-n are the gates 71, 7 respectively.
It passes to the decoder 73 through 2-0, ..., 72-n. Then, the decoder 73 has gates 71, 72-0, ..., 7
The output from 2-n is decoded to select a desired storage area in the memory 2. The predetermined value designating the memory area is preset in the memory area designating registers 5, 6-0, ..., 6-n through the CPU 1.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing an embodiment of the present invention. In the block diagram shown in FIG.
0 and 3-1 are connected to each other via a bus line 8. Here, the CPU 1 controls the system, and the memory 2 has a basic storage area M ₀ and a plurality of extended storage areas M _{1 to} M _n .
3-1 is a partner of data transfer with the memory 2, for example, the device 3-0 transfers the data of the basic storage area M ₀ of the memory 2, and 3-1 is the extended storage area M _{1 of the} memory 2. The data will be transferred.

Reference numeral 4 is a DMA controller. The DMA controller 4 includes a memory 2 and each device 3-0,
3-1 controls the data transfer with the 3-1.
First, the DMA controller 4 includes a CPU 1 and a HOLT.
The signal line and the HOLT response signal (HLTA signal) line are connected. Here, the HLTA signal line is a signal line that informs the selection unit 7 that selects the storage area of the memory 2 that a DMA request is issued.

The DMA controller 4 and the memory 2 are R
It is connected via an ead / Write signal line, and is further connected to the DMA controller 4 and the devices 3-0, 3-.
1 is connected via a Read / Write signal line, a DMA response signal line from a channel provided for each device, and a DMA request signal line issued from the devices 3-0 and 3-1.

Reference numeral 5 is a memory area designation register. The memory area designation register 5 is set with a predetermined value for memory access from the CPU 1. The memory area designation registers 6-0 and 6-1 are DMA. It is provided corresponding to each channel of the controller 4, and a predetermined value is set for each. These memory area designating registers 5, 6-0, 6-1 are also connected to the bus line 8 so that a predetermined value can be set in each register 5, 6-0, 6-1 via the CPU 1. It has become.

Reference numeral 7 is a selection unit for selecting a memory storage area. The selection unit 7 is a memory area designation register 5, 6
The storage area of the memory 2 is selected based on the output from -0,6-1, and the gates 71,72-0,72-
1, a decoder 73 is provided. Here, the gates 71, 72-0, 72-1 are provided corresponding to the respective memory area designation registers 5, 6-0, 6-1. The gate 71 is controlled to be opened / closed by the HLTA signal from the DMA controller 4 to the CPU 1, and the gates 72-0 and 72-1 perform DMA from each channel of the DMA controller 4 to the devices 3-0 and 3-1.
The opening / closing control is performed by a response signal (a signal indicating that the DMA request is accepted).

Further, the decoder 73 includes gates 71 and 7
2-0, 72-1 is for decoding the output from 2-0, 72-1 to generate a signal for selecting a desired storage area in the memory 2, and the signal lines from the gates 71, 72-0, 72-1 and the memory. It is connected to the line for each area. With the configuration described above, in the diagram for explaining the operation of the embodiment of the present invention shown in FIG. 3, in period (A), CPU 1 sets memory area designation registers 5, 6-0, 6-1. At this time, the gate 71 is open. Then, when a DMA request is input from the device 3-0, the CPU 1 in one step
After the operation [period (B)], the execution of DMA is started.

Subsequently, in the period (C), the gate 72-0 which receives the DMA response signal from the channel CH0 of the DMA controller 4 opens, and D between the device 3-0 and the memory 2 is reached.
MA transfer is performed. At this time, the gates 71 and 72-1
Is closed. Then, during this period (C), this time during the DMA between the device 3-0 and the memory 2, the devices 3-1 to D
MA request comes in.

In the next period (D), DM is transmitted from the device 3-1.
Although the gate 71 is opened due to the one-step soft operation of the CPU 1 for accepting the A request, during this period (D), in addition to the DMA request from the device 3-1 described above,
A DMA request is also input from the device 3-0. Therefore, in the period (E), the device 3-1 and the memory 2 are in DMA, but the device 3-0 is waiting for the reception of DMA. Of course, the gate that is open at this time is gate 7
It is 2-1.

In this way, after the DMA between the device 3-1 and the memory 2 in the period (E) is completed, the one-step soft operation similar to the period (D) in the period (F) is performed. Then, in the next period (G), the DMA request from the device 3-0, which has generated the request in the period (D), is accepted. As in the period (H), the DMA request has two devices 3-0, 3-
When neither of 1 is output, the gate 71 is opened similarly to the period (A), and after one step of soft operation, the memory area designating register 5 is set and the desired soft operation is performed.

In this way, another DM is transferred during DMA transfer.
Even if the A request is made, the appropriate memory area can be switched, so that the expanded use of the memory capacity can be effectively made. Since the CPU 1 sets the predetermined values in the memory area designation registers 5, 6-0, 6-1 by software, the selected area of the memory 2 can be made variable.

[0023]

As described above in detail, according to the memory area designation method of the present invention, a CPU for controlling the system is provided.
And a memory having a basic storage area and a plurality of extended storage areas, a plurality of devices, and a DMA controller for controlling data transfer between the memories and the plurality of devices,
In a memory expansion method in which the memory capacity can be expanded and used by switching to select one of the memory storage areas, a memory area designation register in which a predetermined value is set for memory access from the CPU , A memory area designation register provided corresponding to each channel of the DMA controller and set with a predetermined value, and a selection unit for selecting a memory area of the memory based on outputs from these memory area designation registers. The configuration, and the selection unit generates a signal for selecting a desired storage area in the memory by decoding the gate provided corresponding to each memory area designation register and the output from each gate And a decoder for setting a predetermined value in the memory area designation register. By being done in advance through U, it can be switched in a suitable memory area even if there is another DMA request during DMA transfer. Therefore, the expanded use of the memory capacity is effective.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is a diagram illustrating an operation in one embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional example.

FIG. 5 is a diagram illustrating an operation in a conventional example.

[Explanation of symbols]

 1 CPU 2 Memory 3-0, ..., 3-n Device 4 DMA controller 5 Memory area designation register 6-0, ..., 6-n Memory area designation register 7 Selector 8 Bus line 71, 72-0, ..., 72 -N gate 73 decoder 101 CPU 102 memory 103-1, 103-2 device 104 DMA controller 105 memory area designation register 173 decoder

Claims (3)

[Claims] 1. A CPU (1) for controlling a system
, A memory (2) having a basic storage area and a plurality of extended storage areas, a plurality of devices (3-0, ..., 3-n), the memory (2) and the plurality of devices (3-0). , ..., 3-n) and a DMA controller (4) for controlling data transfer between them, and by switching to select any one of the storage areas of the memory (2), the memory capacity is increased. In a memory area designating method that can be expanded and used, a memory area designating register (5) set with a predetermined value for memory access from the CPU (1) and each channel of the DMA controller (4) Memory area designation registers (6-0, ..., 6-n) provided correspondingly and each set with a predetermined value, and these memory area designation registers (6-0, ..., 6-).
A memory area designating method, comprising: a selection unit (7) for selecting a storage area of the memory (2) based on an output from the memory unit (n). 2. The selecting unit (7) is configured to register each memory area designation register (5, 6-0, ..., 6-).
n) provided corresponding to each gate (71, 72-0,
, 72-n) and a decoder for decoding the output from each gate (71, 72-0, ..., 72-n) to generate a signal for selecting a desired storage area in the memory (2). 2. The memory area designating method according to claim 1, wherein the memory area designating method comprises: 3. The memory area designation register (5, 6-
2. The memory area designating method according to claim 1, wherein a predetermined value is set to 0, ..., 6-n) through the CPU (1) in advance.