JPS60118929A - Real time sequencing circuit - Google Patents

Abstract

PURPOSE:To attain sequentially in real time by obtaining a data sequentially in the order of arrangement from each memory. CONSTITUTION:The number of memory circuits M1-M3 is equal to the number of data to be sequenced. A switch means consists of switch circuit S1-S3 and gates G1-G6 and inputs data to a memory by switching a memory output of a pre-state and a memory output of a post-state. A comparator C compares the memory output of the pre-state or the input with each memory output. Moreover, the input of the switch means is switched into the memory output of the pre- state or the input data and the said memory output depending on the result of comparison at the comparator means C. The operation rewriting the memory is performed sequentially by the output of the switch means.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a real-time ranking circuit that can rank input data in real time.

PRIOR ART AND PROBLEMS When performing various calculations, for example, the 8th largest or smallest number (n is any integer) of a series of several bits of parallel information such as the output of an analog-to-digital converter is used. A circuit that outputs information may be required.

The real-time ranking circuit is used in such cases, and ranks input data in real time during the data flow. In order to rank such data, conventionally, the amount of data to be compared is limited, all data is temporarily stored in a storage device, and a comparison is made after a limited period of time has elapsed to determine the ranking. A method of attaching was used.

In this case, data is usually limited by time; therefore, as the amount of data increases and the limited time becomes longer, the time lag between data input and comparison judgment becomes larger, and the required storage capacity increases. There was a problem that the amount of data was large and the circuit scale was also large.

OBJECT OF THE INVENTION The present invention attempts to solve the problems of the prior art, and its purpose is to be able to rank input data in real time, and therefore to immediately display the ranked data. The object of the present invention is to provide a real-time ranking circuit that can be used and has a minimum circuit size.

Embodiment of the Invention FIG. 1 shows the structure of an embodiment of a real-time ranking circuit of the present invention. In the same figure, G.

G2,03. G,,G5. G6 is the gate, S I +s
2. s3 is a switch circuit, M, , M2 . M3 is a memory circuit with an arbitrary number of bits, and C is a comparison circuit with the same number of bits as the memory circuit.

Further, FIG. 2 is a time chart showing each line signal in the circuit ranked in the order shown in FIG. Clock 1. which controls M2°Ml, respectively. It is shown that clock 2 and clock 3 are generated sequentially with a slight delay from the master clock.

Furthermore, FIG. 3 is a flowchart explaining the order of operation of the circuit according to the ranking shown in FIG.

The operation of the real-time ranking circuit of the present invention will now be explained based on these figures. Input data is applied to one input of the comparison circuit C via the gate circuit GI in response to the clock 1. At the same time, the contents of memory circuit M3 are the same as clock 1.
The signal is read out by the gate circuit G2 and applied to the other input of the comparator circuit C via the gate circuit G2. The contents of the memory circuit M3 are 0 in the initial state, and in other cases, the previous data is held. As a result of the comparison in the comparison circuit C, if the input data is larger than the data held in the memory circuit M3, the comparison circuit C controls the switch circuit S3 to transfer the input data output from the gate circuit G1 to the memory. The input data is input to the circuit Fvfh, whereby the memory circuit M3 is rewritten with the input data at the timing of the next clock 2. On the other hand, input data is stored in memory circuit M3
When the input data is equal to or smaller than the data held in , the input data and the output of the memory circuit M3 are input to the comparator circuit C again by the clock 1.

Next, the data held in the memory circuit M3 is read out in response to the clock 2, and is applied to one input of the comparator circuit C via the gate circuit G3. At the same time, the contents of the memory circuit M2 are read out by the same clock 2, and the gate circuit G
4 and is applied to the other input of the comparator circuit C. The contents of the memory circuit M2 are 0 in the initial state, and in other cases, the previous data is held. If the comparison result in the comparison circuit C is that the data held in the memory circuit M3 is larger than the data held in the memory circuit M2, the comparison circuit C controls the switch circuit S2 to read data from the memory circuit M3. The output data is transferred to the memory circuit M.
2, thereby causing memory circuit M2 to receive clock 3
At the timing of , it is rewritten with the data held in the memory circuit M3. Further, the comparison circuit C controls the switch circuit S3 to input the data read out from the memory circuit M2 to the memory circuit M3.
It is rewritten with the data held in 2. On the other hand, when the data held in the memory circuit M3 is equal to or smaller than the data held in the memory circuit M2, the process returns to the original state and uses the clock 1 again to input the input data and output the memory circuit M3. Comparison circuit C
is man-powered.

Next, the data held in the memory circuit M2 is read out in response to the clock 3, and is applied to one input of the comparator circuit C via the gate circuit G5. At the same time, the contents of the memory circuit M are read out by the same clock 3, and the gate circuit G
6 and is applied to the other input of the comparator circuit C. The contents of the memory circuit M1 are 0 in the initial state, and in other cases, the previous data is held. As a result of the comparison in the comparison circuit C, if the data held in the memory circuit M2 is larger than the data held in the memory circuit M, the comparison circuit C controls the switch circuit S1 to transfer the data held in the memory circuit M2. The data being read from the memory circuit M
1, and thereby the memory circuit M is rewritten with the data held in the memory circuit M2 at the timing of the master clock. Furthermore, the comparator circuit C controls the switch circuit S2 to input the data being read from the memory circuit M1 to the memory circuit M2, so that the memory circuit M2 inputs the data read out from the memory circuit M1 to the memory circuit M2 at the timing of the master clock.
It is rewritten with the data held in the memory circuit M1. On the other hand, if the data held in the memory circuit M2 is equal to or smaller than the data held in the memory circuit M1, the process returns to the original state and uses the clock 1 again to combine the input data with the output of the memory circuit M3. is input to the comparison circuit C.

The memory circuit M when the series of operations is completed in this way
l, M2. ．． The output data of M3 is the first rank,
They are arranged in the order of second rank and third rank, so that the rank of each data can be known. Such operations are repeated each time data is input, so that input data is ranked in real time.

Note that although the above embodiment is shown for the case where three pieces of data are ranked, it is possible to similarly rank other pieces of data. Further, in the above embodiment, a case has been shown in which each data is arranged and output in descending order, but it is also easy to arrange and output the data in descending order. Furthermore, in the above example, only one comparison circuit is provided to compare the outputs of each memory, but it is also possible to provide a comparison circuit for each memory to perform the comparison. Needless to say.

As described in the detailed description of the invention, the real-time ranking of the present invention uses a circuit that includes a number of memories equal to the number of data to be ranked that are arranged in series, and an input or previous memory output. A switching means provided for each memory inputs the input to the memory by switching between the output and the output of the memory at a later position, and a comparison means which compares the output of each memory with the output of the input or previous memory. Depending on the comparison result, the input of the switching means is switched between the input data or the previous memory output and the memory output, and the memory is sequentially rewritten depending on the output of this switching means, thereby rewriting the array from each memory. Since the data is ranked in order, the input data can be ranked in real time. Therefore, the ranked data can be used immediately, and the circuit size can be minimized. can be done and is extremely effective.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a diagram showing the configuration of an embodiment of the real-time ranking circuit of the present invention, and FIG. 2 is a diagram showing the configuration of an embodiment of the real-time ranking circuit of the present invention. The time chart shown in FIG. 3 is a flowchart illustrating the order of operation of the circuits ranked in the order shown in FIG. c, ,G2. G3. G4. G5. Ge-gate, SI+
s2, 53---Switch circuit, Ml, M2゜M3-
1.Memory circuit, c-comparison circuit patent applicant Fujitsu Limited

Claims (1)

[Claims] A memory with a capacity equal to or greater than the number of data to be ranked that is arranged in series, and each memory that is input to the memory by switching between input or previous memory output and subsequent memory output. and comparison means for comparing the input or previous memory output with each memory output, and depending on the comparison result of the comparison means, the input of the switching means is changed to the input data or the previous memory output. and the memory output, and sequentially performs an operation for each memory to rewrite the memory according to the output of the switching means, thereby obtaining data ranked in the order of arrangement from each memory. .