JPH06350414A - Zero-cross schmitt circuit - Google Patents

Abstract

PURPOSE:To prevent erroneous shaping of an input signal even in the case of input of the signal which does not continuously pass the Schmitt levels at three points. CONSTITUTION:Three difference Schmitt signals SIGLOW, SIGMID, and SIGHIGH corresponding to Schmitt levels at three points are generated by comparing circuits 2, 3, and 4, and these signals are used to generate a zero-cross Schmitt signal SIGZSCH of an input signal 100 by RS flip flops 6 and 8 and a D flip flop 11, and a simple Schmitt signal SIGNSCH is made by a D flip flop 13. Simultaneously, a switching signal SIGDIF is made by D flip flops 12 and 13, NAND gates 14 and 15, and an AND gate 16; and when the signal 100 which does not continuously pass the Schmitt levels at three points is inputted, the same signal SIGOUT as the simple Schmitt signal SiGNSCH which is outputted instead of the zero-cross Schmitt signal SIGZSCH by the switching signal SIGDIF is outputted from a NAND gate 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a zero-cross Schmitt circuit for shaping an arbitrary signal superimposed on a bias voltage into a square wave.

[0002]

2. Description of the Related Art Conventionally, a waveform shaping circuit for shaping an arbitrary signal superimposed on a bias voltage into a square wave as described above is a circuit having a hysteris at a bias voltage point (hereinafter, referred to as
This is referred to as a simple Schmitt, and the upper and lower level voltages of the bias voltage are set as Schmitt levels, and the operation of performing Schmitt is performed when the arbitrary signal continuously passes the Schmitt levels at the two points. Although such a conventional waveform shaping circuit is excellent in noise resistance, delay and variation from the phase Schmitt point occur due to amplitude and AM modulation of the arbitrary signal, magnitude and variation of Schmitt level, and movement of bias voltage. Therefore, when waveform-shaping a signal related to measurement or control that requires accuracy,
Care must be taken in its use.

Therefore, in order to solve the above problems, a zero-cross Schmitt circuit as shown in FIG. 13 which does not have hysteresis at a bias voltage point when waveform shaping is proposed. In this zero-cross Schmitt circuit, the signal 100 superimposed on the bias voltage as shown in FIG. 14A is input to the amplifier circuit 1 and the comparison circuits 2, 3, and 4. The signal 100 is input to the inverting input terminals of the comparison circuits 2 and 3, and is input to the non-inverting input terminal of the comparison circuit 4. On the other hand, the resistors R1 and R2 form a voltage dividing circuit, and the resistor R1
A constant current flows into the resistor R1 from one end of the resistor 1, and a constant current flows out from one end of the resistor R2. A bias voltage of the signal 100 is output from the amplifier circuit 1, and this bias voltage is applied to the connection point of the resistors R1 and R2. As a result, the non-inverting input terminal of the comparator circuit 2, the non-inverting input terminal of the comparator circuit 3 and the inverting input terminal of the comparator circuit 2 are connected to the non-inverting input terminal of the comparing circuit 2 as shown in FIG.
The reference voltages (Schmitt level) of H, M (bias voltage) and L of (A) are applied. As a result, the comparison circuit 2
14B outputs a SIG _LOW square wave, which is input to the RS flip-flop 6. From the comparison circuit 3, the SIG as shown in FIG.
A square wave of _MID is output, which is directly input to the RS flip-flop 7 and also input to the RS flip-flop 6 via the inverter 5. The comparator circuit 4 outputs a SIG _HIGH square wave as shown in FIG. 14D, which is input to the RS flip-flop 7. Therefore, the RS flip-flop 6 outputs a square wave of SIG _{L & M} as shown in FIG. 14 (E), which is input to the RS flip-flop 8 and the AND gate 9. or,
The RS flip-flop 7 outputs a SIG _{H & M} square wave as shown in FIG. 14 (F), which is output to the RS flip-flop 8 and the AND gate 9. This allows RS
The flip-flop 8 outputs SIG _DATA as shown in FIG. _14G , which is the D flip-flop 1.
0 is input to the D terminal. Further, the AND gate 9 outputs SIG _CLK as shown in FIG. 14 (H), which is input to the CK terminal of the D flip-flop 10. Therefore, from the Q terminal of the D flip-flop 10, FIG.
A square wave SIG _OUT is output as shown in (I).

In the zero-cross Schmitt circuit shown in FIG. 13 described above, the bias voltage M shown in FIG. 14A and the voltages H and L above and below the bias voltage M are set as Schmitt levels. . By processing the Schmitt waveform when the signal 100 continuously passes through these three points of the Schmitt levels M, H, and L as described above, the Schmitt operation without hysteresis is performed at the point of passing the M point. . This zero-cross Schmitt circuit has the advantage of being excellent in noise resistance as well as the simple Schmitt circuit, and since it has no hysteresis, it is ideal due to the amplitude and AM modulation of the signal 100, the magnitude and variation of the Schmitt level, and the movement of the bias voltage point. There is an advantage that there is almost no delay or variation from the Schmidt point.

However, when the signal 100 does not continuously pass through the above-mentioned Schmitt levels M, H, and L and returns only after passing through only two points of the Schmidt level L and the Schmitt levels H or L above and below the Schmitt level L, the signal 100 first returns. Schmidt level M
However, even if the Schmitt level M is passed during folding back, the Schmitt level is not Schmitt as shown in FIG. 14 (I), and the Schmitt level H or L is passed.
There is a drawback that the Schmitt level M and the upper and lower levels H and L of the Schmitt level M are not Schmitted even after passing the peak of the amplitude. This is because the noise resistance is excellent and the passage of the Schmitt level M at the time of signal folding is regarded as noise. The comparison circuits 2 and 3, the RS flip-flops 7 to 8, the AND gate 9, and the D flip-flop 10 are provided.
The operating principle of the logic consisting of is that when a signal passes through three points, the Schmitt level M and the upper and lower Schmitt levels H and L, a simple Schmitt with hysteresis is created by the H and L levels and the inverse data of that data is created. This is where the zero crossing Schmidt is created by switching when passing through the point M.

FIG. 15 is a time chart showing the operation of each part when another waveform shaping target signal 100 is input to the zero-cross Schmitt circuit shown in FIG. 13 described above. In this case as well, the signal 100 is at the level H. When folded back in front, the SIG _OUT shown in FIG. 15 (I) has a missing portion.

[0007]

There are two types of conventional waveform shaping circuits: a simple Schmitt circuit and a zero-cross Schmitt circuit.
There is an example, but there was a problem as shown below. (1) In the simple Schmitt circuit, when the arbitrary signal superimposed on a certain bias voltage is shaped into a square wave, the principle of Schmitt at two points of the upper and lower levels of the bias voltage has a hysteresis with respect to the bias voltage. As a result, there are delays and variations from the ideal Schmitt point due to signal amplitude and AM modulation, Schmitt level magnitude and variations, and bias voltage point movements. Precautions must be taken for measurement and control required for accuracy. There was a drawback that it was not easy to use.

(2) In the zero-cross Schmitt circuit, when shaping an arbitrary signal superimposed on a bias voltage into a square wave, the bias voltage M and the voltages H and L at the upper and lower levels are continuously passed. Instead, when the bias voltage M and one of the upper and lower levels of the voltage H or L are passed through only two points in total, the first bias voltage M
However, there is a drawback in that the Schmitt level voltage H or L is not passed, the peak of the amplitude is reached, and then the Schmitt level is not Schmitt even if the bias voltage M and the upper and lower levels of the voltage H and L are continuously passed. However, there is a drawback in that accurate waveform shaping cannot be performed.

Therefore, the present invention eliminates the above-mentioned drawbacks, there is no delay or variation from the ideal Schmidt point, and erroneous shaping does not occur even if a signal that does not continuously pass through the Schmitt levels at three points is input. It is intended to provide a zero-cross Schmidt circuit.

[0010]

A zero-cross Schmitt circuit according to the present invention comprises a Schmitt level M corresponding to a bias voltage of an input signal and Schmitt level creating circuits for creating Schmitt levels H and L above and below the Schmitt level M. , A three-difference Schmitt signal generation circuit for generating three-difference first, second, and third Schmitt signals obtained by Schmitt the input signals by using these Schmitt levels M, H, and L, respectively. , A zero-cross Schmitt signal creating circuit that creates a zero-cross Schmidt signal from the second and third Schmidt signals, and the first Schmitt signal from the first, second, and third Schmitt signals and the zero-cross Schmitt signal. A switching signal generating circuit for generating a switching signal indicating a portion different from the zero-cross Schmidt signal; When the input signal is folded back before the Schmitt level H or L, the waveform shaping signal equivalent to that when the first Schmitt signal is output instead of outputting the zero-cross Schmidt signal as the waveform shaping signal is switched. And a waveform shaping signal output selection circuit created from the signal, the zero-crossing Schmitt signal, and the first Schmitt signal.

[0011]

In the zero-cross Schmitt circuit of the present invention, the Schmitt level creating circuit creates the Schmitt level M corresponding to the bias voltage of the input signal and the Schmitt levels H and L above and below the Schmitt level M. The three-difference Schmitt signal creation circuit creates three-difference first, second, and third Schmitt signals obtained by Schmitt the input signals using the Schmitt levels M, H, and L, respectively.
The zero-cross Schmidt signal generation circuit is composed of the first, second, and
A zero crossing Schmidt signal is created from the third Schmitt signal. The switching signal generation circuit generates a switching signal indicating a different portion between the first Schmitt signal and the zero-cross Schmitt signal from the first, second and third Schmitt signals and the zero-cross Schmitt signal. The waveform shaping signal output selection circuit is equivalent to the case of outputting the first Schmitt signal instead of outputting the zero-cross Schmitt signal as the waveform shaping signal when the input signal is folded back before the Schmitt level H or L. The waveform shaping signal is generated from the switching signal, the zero-cross Schmitt signal, and the first Schmitt signal.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the zero-cross Schmitt circuit of the present invention. 1 is an amplifier circuit, 2 to
4 is a comparison circuit, 5 and 17 are inverters, 6 and 7 and 8 are R
S flip-flops, 9, 14, 15, 18, 19, 2
0 is a NAND gate and 16 is an AND gate.

Next, the operation of this embodiment will be described. The signal 10 superimposed on the bias voltage as shown in FIG.
0 is input to the amplifier circuit 1 and the comparison circuits 2, 3, and 4. The signal 100 is input to the inverting input terminals of the comparison circuits 2 and 3,
It is input to the non-inverting input terminal of the comparison circuit 4. On the other hand, the resistors R1 and R2 form a voltage dividing circuit, and a constant current flows into the resistor R1 from one end of the resistor R1 and a constant current flows out from one end of the resistor R2. In addition, the amplifier circuit 1 is the signal 1
00 is amplified and applied to the connection point of the resistors R1 and R2. As a result, the non-inverting input terminal of the comparison circuit 2, the non-inverting input terminal of the comparison circuit 3, and the inverting input terminal of the comparison circuit 2 are respectively set to H, M (bias voltage), and L as shown in FIG. A reference voltage is applied.

As a result, the square wave S as shown in FIG. 2B, which is a Schmitt waveform of level L, is output from the comparison circuit 2.
IG _LOW is output, and this is input to the RS flip-flop 6. From the comparison circuit 3, a square wave SIG which is a Schmitt waveform at the bias voltage point M as shown in FIG.
_{The MID} is output and directly input to the RS flip-flop 7 and also input to the RS flip-flop 6 via the inverter 5. From the comparison circuit 4, a square wave S having a Schmitt waveform of level H as shown in FIG.
IG _HIGH is output, and this is input to the RS flip-flop 7. Therefore, from the RS flip-flop 6, information on the bias voltage point M and the Schmitt level point L below the information.
Square wave SI as shown in FIG.
G _{L & M} is output and input to the RS flip-flop 8 and the NAND gate 9. Further, the RS flip-flop 7 outputs a square wave SIG _{H & M} as shown in FIG. 2 (F) including both the information from the bias point M and the information of the Schmitt level point H above the RS flip-flop 8 and the RS flip-flop 8. It is output to the NAND gate 9. As a result, the RS flip-flop 8 outputs a square wave SIG _DATA , which is an inverse information waveform of the simple Schmitt waveform, as shown in FIG. 2G, and this is input to the D terminal of the D flip-flop 11. In addition, a square wave SIG as shown in FIG. 2 (H) containing both zero-cross Schmitt timing information and simple Schmidt timing information from the NAND gate 9.
_CLK is output, and this is CK of D flip-flop 11.
It is input to the terminals and the CK terminals of the D flip-flops 12 and 13. Therefore, from the Q terminal of the D flip-flop 11, a square wave SIG _ZSCH corresponding to the zero-cross Schmitt waveform of the conventional circuit as shown in FIG. 2 (I) is output to the D terminal of the D flip-flop 12 and the NAND gate 18 Is output to.

On the other hand, from the Q terminal of the D flip-flop 12, the square wave SIG _ZSCH is delayed by the timing of the simple Schmitt and the square wave SIG as shown in FIG.
_ZSCH1 is output and input to the NAND gate 14. At this time, from Q'terminal of the D flip-flop 12 a square wave SIG' _ZSCH1 the opposite polarity is output from the square wave SIG _ZSCH1 as shown in FIG. 2 (J), which is input to the NAND gate 15. The square wave SIG _MID output from the comparison circuit 3 is input to the D terminal of the D flip-flop 13 and the NAND gate 19. This gives D
Square wave SIG _MID from the Q terminal of the flip-flop 13.
2 corresponding to the conventional simple Schmidt waveform synchronized with
With square wave SIG _NSCH as shown in (K) is output, from Q'terminal is output square wave SIG' _NSCH, square wave SIG _NSCH are input to the NAND gate 14, a square wave SIG' _NSCH is Nandoketo 15 Entered in. The output signals of the NAND gates 14 and 15 are input to the AND gate 16, and the AND gate 16 outputs a square wave SIG _DIF as shown in FIG. This square wave SIG _DIF
Shows almost the waveform which the square wave SIG _ZSCH originally has as shown in FIG. 2 (I).
The hatched portion of the square wave SIG _ZSCH shown in (I) and the high level portion of the square wave SIG _DIF shown in FIG. This square wave SIG
_{The DIF} is directly input to the NAND gate 19, the polarity of which is inverted by the inverter 17, and the _DIF is input to the NAND gate 18. As a result, FIG.
A square wave SIG _ZSCH2 as shown in (M) is output to the NAND gate 20, and a square wave SIG _NSCH as shown in FIG. 2 (N) is output to the NAND gate 20 from the NAND gate 18. Finally, the NAND gate 20 outputs a square wave SIG _OUT (waveform shaping signal) as shown in FIG. 2 (O), which is generated by dividing the cases of zero-cross Schmitt and simple Schmitt. This square wave SIG _OUT is a square wave SI
At the low level part of G _DIF, it matches with the zero-cross Schmitt square wave SIG _ZSCH, and at the high level part of the square wave SIG _DIF , it becomes the same waveform as the simple Schmitt square wave SIG _MID of FIG. 2 (C). ing.

FIG. 3 is a diagram showing a time chart of a square wave SIG appearing in each part of the circuit of FIG. 1 when the waveform of the signal 100 input to FIG. 1 is different from the above. Also in this case, the signal 100 shown in FIG.
On the other hand, the waveform shaping signal SIG as shown in FIG.
_OUT is obtained from NAND gate 20.

FIG. 4 is a diagram showing a time chart of the square wave SIG appearing in each part of the circuit of FIG. 1 when the input signal 100 shown in FIG. 1 contains noise. in this case,
FIG. 4I corresponding to a conventional zero-cross Schmidt waveform.
The square wave SIG _ZSCH shown in FIG.
It is the same as _OUT, and it is understood that it is not affected by the noise of the signal 100, and it is understood that the noise resistance of this example is equivalent to that of the conventional zero-cross Schmitt circuit.

FIG. 5 shows the reverse rotation detection position of each circuit when the zero-cross Schmitt circuit of this embodiment, the conventional zero-cross Schmitt circuit, and the conventional simple Schmitt circuit are used to detect the reverse rotation of a capstan motor or the like in a magnetic recording / reproducing apparatus. It is the figure which compared. 5A and 5B show signal waveforms 100FGA and 100F output from speed detectors A and B for detecting the rotation speed and the like of the capstan motor.
GB indicates GB, M indicates a Schmitt level at a bias voltage point, H indicates a Schmitt level above the bias voltage, and L indicates a level below the bias voltage. FIG. 5C shows a waveform shaping signal FGA when the signal 100FGA is shaped by a simple Schmitt circuit, and FIG. 5D shows a waveform shaping signal FGB when the signal 100FGB is shaped by a simple Schmitt circuit. Shows. FIG. 5E shows a signal F / R obtained by detecting the forward rotation and the reverse rotation of the motor using the waveform shaping signals FGA and FGB. In this detection signal F / R, the point where the level changes from low level to high level indicates the detection point at which the motor has rotated from normal rotation to reverse rotation.

FIG. 5F shows a waveform shaping signal FGA when the signal 100FGA is shaped by a conventional zero-cross Schmitt circuit, and FIG. 5G shows the signal 100FG.
The waveform shaping signal FGB when waveform shaping of B by the said zero cross Schmitt circuit is shown. FIG. 5 (H) shows a signal F / R obtained by detecting the forward rotation and the reverse rotation of the motor using the waveform shaping signals FGA and FGB. This detection signal F /
In R, the point where the motor changes from low level to high level indicates the detection point at which the motor has rotated from normal rotation to reverse rotation. Figure 5 (I)
Shows a waveform shaping signal FGA when the signal 100FGA is shaped by the zero-cross Schmitt circuit of the present embodiment, and FIG. 5 (J) shows a waveform shaping when the signal 100FGB is shaped by the zero-cross Schmitt circuit of the present embodiment. The signal FGB is shown. FIG. 5 (K) shows a signal F / R obtained by detecting the forward rotation and the reverse rotation of the motor using the waveform shaping signals FGA and FGB. In this detection signal F / R, the point where the level changes from low level to high level indicates the detection point at which the motor has rotated from normal rotation to reverse rotation. By the way, the original position where the motor is rotated from the normal rotation to the reverse rotation is the point indicated by 0 in FIGS. 5 (L) to 5 (N), but in the simple Schmitt circuit, FIG.
Reverse rotation detection is performed with a delay as indicated by the arrow (L), and reverse rotation detection is performed with the conventional zero-cross Schmitt circuit after a delay as indicated by the arrow in FIG. 5 (M). In the circuit, reverse rotation detection is performed with a delay by the amount shown by the arrow in FIG. Therefore, it can be seen that the detection accuracy is highest when the zero-cross Schmitt circuit of this embodiment is used.

FIG. 6 is similar to FIG. 5, but the speed detection signals 100FGA and 100FG input to each waveform shaping circuit are input.
In the example showing the case where the waveforms of B are different, it can be seen that in this case also, the detection accuracy is highest when the zero-cross Schmitt circuit of this embodiment is used. 7 is similar to FIG. 5, but the speed detection signal 100F input to each waveform shaping circuit is
In another example showing a case where the waveforms of GA and 100FGB are different, it can be seen that the detection accuracy is highest when the zero-cross Schmitt circuit of this embodiment is used also in this example. Figure 8
5 is similar to that of FIG. 5, but shows another example in which the waveforms of the speed detection signals 100FGA and 100FGB input to the respective waveform shaping circuits are different. In this case also, the zero-cross Schmitt circuit of this embodiment is used. It can be seen that the detection accuracy is highest when there is.

According to the present embodiment, it is possible to eliminate the delay and the variation from the ideal Schmitt point due to the amplitude and AM modulation of the target signal 100 to be subjected to waveform shaping, the magnitude and variation of the Schmitt level, the movement of the bias voltage point and the like. Can
Highly accurate waveform shaping can be performed without sacrificing noise resistance. As a result, good results can be obtained by using this example for measurement, control, etc. that require accuracy. Moreover, even if the signal 100 is folded back before passing the Schmitt level H or L as in a simple Schmitt circuit,
Schmitt is not prevented, and the waveform shaping error can be significantly reduced.

FIG. 9 is a block diagram showing the main part of another embodiment of the present invention. In this example, FG _L , FG _M , FG _B
The three-difference Schmidt waveform of the RS flip-flop circuit 6,
Input to 7 and the waveform FG _{ML including} both the information of the bias voltage point and the information of the Schmitt level point below it, and the information of the bias voltage point and the information of the Schmitt level point above it Obtain two signals of waveform FG _MH . Then F
The G _ML and FG _MH is input to the RS flip-flop circuit 8 to obtain a simple Schmitt waveform FG _N, likewise FG _ML and FG _MH
Is input to the NAND gate 9 to obtain a waveform FG _{CLK including} both the zero-cross Schmitt timing and the simple Schmitt timing information. Then, the inverse information F of the FG _N
Obtain the same FG _Z and conventional zero-cross Schmidt waveform _G'N and FG _CLK (the falling) is input to D flip-flop 11.

In order to clarify the difference between the zero-cross Schmidt and the simple Schmidt, FG _Z and FG _CLK are set to D-.
Input to the flip-flop 12 to obtain a waveform FG _ZN obtained by shifting the zero crossing Schmitt to the timing of the simple Schmitt, and input this FG _ZN and the FG _N to the combination circuit of the AND gate 16 and the NAND gates 14 and 15. , A waveform FG _DIF showing that the comparison result is different at a high level is obtained from the AND gate 16. This FG _DIF is a control signal for shaping the low level portion by zero crossing Schmitt and shaping the high level portion by simple Schmitt. Therefore, three signals of FG _N , FG _Z and FG _DIF are NAND gate 18, It is input to the circuit configured by the combination circuit of 19 and 20 and the inverter 17, and the case-separated waveform FG _OUT of the zero cross Schmitt waveform and the simple Schmitt waveform is output as a waveform shaping signal.
After all, FG _OUT , which is the final waveform shaping signal output from the NAND gate 20, is the square wave FG _Z output from the Q terminal of the D flip-flop 11 corresponding to the conventional zero cross Schmitt, and the zero cross Schmitt and the simple Schmitt. The square wave FG _N output from the RS flip-flop 8 whose difference is clarified is generated by FG _DIF in different cases. The operation of each unit of the above circuit is as shown in the time chart shown in FIG.
Further, FIG. 11 is a time chart showing the operation of the circuit shown in FIG. 9 when the input signal 100 has a small noise n, and the finally obtained waveform shaping signal FG _OUT shows the influence of noise. I understand that I have not received it.

FIG. 12 shows waveforms when the same signal is shaped by the conventional simple Schmitt circuit, the conventional zero cross Schmitt circuit, the zero cross Schmitt circuit of the embodiment shown in FIG. 1 and the zero cross Schmitt circuit shown in FIG. It is the figure which compared the shaping signal. FIG. 11A shows a signal 100 before waveform shaping, and noise n is placed on the signal. A waveform-shaped signal obtained by shaping this signal with a simple Schmitt circuit is as shown in FIG. 11 (B), and a signal with a conventional zero-cross Schmitt circuit is shaped as shown in FIG. 11 (C). The waveform-shaped signal shown in the zero-cross Schmidt circuit is shown in Fig. 11.
As shown in FIG. 11D, the signal whose waveform has been shaped by the zero-cross Schmitt circuit shown in FIG. 9 becomes as shown in FIG. 11E. When the waveform is shaped by the zero-cross Schmitt circuit shown in FIG. 1, the accuracy is high, but the influence of noise appears at the portion a as shown in FIG. 11D. But,
When the waveform is shaped by the zero-cross Schmidt circuit shown in FIG. 9, there is an advantage in that it is not affected by noise, although the accuracy is somewhat deteriorated as shown in FIG.

According to the present embodiment, even if the signal to be subjected to waveform shaping contains small noise, the waveform shaping can be performed without being affected by the influence unlike the embodiment shown in FIG. The noise property is improved as compared with the previous embodiment shown in FIG. Other effects are similar to those of the previous embodiment.

[0026]

As described above, according to the zero-cross Schmitt circuit of the present invention, there is no delay or variation from the ideal Schmidt point, and erroneous shaping is performed even if a signal which does not continuously pass the Schmitt level of three points is input. Can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a zero-cross Schmitt circuit of the present invention.

FIG. 2 is a time chart showing a waveform shaping operation of the circuit shown in FIG.

3 is a diagram showing a time chart of a square wave SIG appearing in each part of the circuit of FIG. 1 when the waveform of the signal 100 input to FIG. 1 is different from the above.

4 is a diagram showing a time chart of a square wave SIG appearing in each part of the circuit of FIG. 1 when noise is included in the input signal 100 shown in FIG.

FIG. 5 compares the reverse rotation detection position of each circuit when the zero-cross Schmitt circuit of the present embodiment, the conventional zero-cross Schmitt circuit, and the conventional simple Schmitt circuit are used for reverse rotation detection of a capstan motor or the like in a magnetic recording / reproducing apparatus. The figure.

6 is a diagram showing another example in which the waveform of the speed detection signal 100 input to the waveform shaping circuit shown in FIG. 5 is different.

7 is a diagram showing still another example in which the waveform of the speed detection signal 100 input to the waveform shaping circuit shown in FIG. 5 is different.

8 is a diagram showing still another example in which the waveform of the speed detection signal 100 input to the waveform shaping circuit shown in FIG. 5 is different.

FIG. 9 is a block diagram showing a main part of another embodiment of the present invention.

10 is a time chart showing a waveform shaping operation of the circuit shown in FIG.

11 is another time chart showing the waveform shaping operation of the circuit shown in FIG.

FIG. 12 compares waveform-shaping signals when the same signal is shaped by the conventional simple Schmitt circuit, the conventional zero-cross Schmitt circuit, the zero-cross Schmitt circuit shown in FIG. 1 and the zero-cross Schmitt circuit shown in FIG. Fig.

FIG. 13 is a block diagram showing an example of a conventional zero-cross Schmitt circuit.

14 is a time chart showing a waveform shaping operation of the circuit shown in FIG.

15 is another time chart showing the waveform shaping operation of the circuit shown in FIG.

[Explanation of symbols]

1 ... Bias voltage extraction circuit 2, 3, 4 ... Comparison circuit 5, 17 ... Inverter 6, 7, 8 ... RS
Flip-flops 9, 14, 15, 18, 19, 20 ... NAND gates 11, 12, 13 ... D flip-flops 16 ... AND gates

Claims (2)

[Claims] 1. A Schmitt level creating circuit for creating a Schmitt level M corresponding to a bias voltage of an input signal and Schmitt levels H and L above and below the Schmitt level M, and these Schmitt levels M, H and L are used. A three-difference Schmidt signal creating circuit for creating three-difference first, second, and third Schmidt signals obtained by Schmitt the input signals, and a zero-cross Schmidt from the first, second, and third Schmidt signals. A zero-cross Schmitt signal generation circuit that generates a signal, and a switching signal that indicates a different portion between the first Schmitt signal and the zero-cross Schmitt signal from the first, second, and third Schmitt signals and the zero-cross Schmitt signal. And a switching signal generating circuit for generating the input signal before the Schmitt level H or L. When folded back, the same waveform shaping signal as when the first Schmidt signal is output instead of outputting the zero crossing Schmitt signal as the waveform shaping signal, the switching signal, the zero crossing Schmitt signal, and the first Schmitt signal. A zero crossing Schmitt circuit comprising a waveform shaping signal output selection circuit created from 2. The waveform shaping signal output selection circuit outputs a fourth Schmitt signal including both information of the first and third Schmitt signals, instead of outputting the zero-cross Schmitt signal as a waveform shaping signal. A waveform shaping signal equivalent to the case is created from the switching signal, the zero-crossing Schmitt signal, and a fifth Schmitt signal including all the information of the first, second, and third Schmitt signals. The zero-cross Schmitt circuit according to claim 1.