JPH039720B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a device for generating clock signals and rotate signals used to detect the rotational position of a stepping motor.

Prior Art In the prior art, a control unit (ECU) that controls a stepping motor is provided with terminals for taking out a clock signal indicating the number of steps of the stepping motor and a rotation signal that determines the rotation direction of the stepping motor. The clock signal and rotate signal are taken out from these terminals and input to a detector equipped with an internal counter.
The clock signal is counted up or down based on the rotate signal, and the counted value is used as the rotational position of the stepping motor.

However, extracting the above-mentioned clock signal and rotate signal from the control unit is not versatile for detecting the position of a stepping motor. It was impossible to detect the position of the ping motor.

Purpose The purpose of the present invention is to solve the above-mentioned technical problem,
It is an object of the present invention to provide a stepping motor position detection method that can more easily create a clock signal and a rotate signal with less signal wiring and a simple configuration.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. As shown in FIG. 1, the stepping motor M is connected through drive signal lines l1 to l4 to an emission control unit E which controls exhaust gas up to the gasoline engine. The embodiment of the present invention is configured to directly extract the signals flowing through the drive signal lines l1 to l4, create a clock signal and a rotate signal from the signals, and detect the rotational position of the stepping motor M.

FIG. 2 is a logic circuit diagram of one embodiment of the present invention. Input terminal P1 is connected to EX via NOT gate 1.
- Connected to input terminal 2 of OR gate 2 and terminal CK of flip-flop 9. Input terminal P2 is
It is connected to input terminal b of EX-OR gate 2 and terminal D of flip-flop 9 via NOT gate 8. The output terminal C of EX-OR gate 2 is
- connected to input terminal a of OR gate 6, and
via a NOT gate 3, an integrating circuit 4 consisting of a resistor R and a capacitor C, and a NOT gate 5.
Connected to input terminal b of EX-OR gate 6.
The NOT gate 3, the integrating circuit 4, and the NOT gate 5 constitute a delay circuit 7. and,
Further, the EX-OR gates 2 and 6 and the delay circuit 7 constitute a one shot pulse generation circuit. The output terminal Q of the flip-flop 9 is connected to the rotate output terminal P4. The output terminal C of the EX-OR gate 6 is connected to the clock output terminal P3. The reason why the NOT gates 3 and 5 are connected to both ends of the integrating circuit 4 consisting of a resistor R and a capacitor C is as follows. i.e. EX
This is to reliably delay the output of the -OR gate 2 and generate a clock signal more accurately from the output terminal P3. This flip-flop 9 has its terminal CK
and a so-called phase determination circuit that detects which of the signals input to terminal D rises first.

The operation of the logic circuit diagram shown in FIG. 2 will be described below based on the timing chart shown in FIG.
Among the drive signals for the stepping motor M, for example, a one-phase drive signal φ1 is applied to the input terminal P1 (FIG. 3 1). One-phase drive signal φ1 is input to input terminal P2.
For example, a two-phase drive signal φ2 having a phase difference of 90° is applied (FIG. 3, 2). In addition, in FIGS. 3 1 and 2, a change in waveform can be seen from the middle, which indicates that the stepping motor has shifted from left rotation to right rotation. These drive signals φ1 and φ2
are EX− through NOT gates 1 and 8, respectively.
The signal Q1 is inputted to the OR gate 2 (FIGS. 3 and 3), and the signal Q1 shown in FIG. 3 is sent out from the output terminal C of the EX-OR gate 2. The signal Q1 becomes the signal Q2 shown in FIG. 36 by the delay circuit 7,
It is applied to the output terminal b of the EX-OR gate 6.
The EX-OR gate 6 sends out a continuous one-shot pulse signal Q3 shown in FIG. 3 to the output terminal C based on the signal Q1 applied to the input terminal a and the signal Q2 applied to the input terminal b. This signal Q3 is sent to the clock output terminal P3 and is used as a clock signal.

Next, in explaining the method for creating the rotate signal, first a brief explanation of the operation of the flip-flop 9 will be given. The flip-flop 9 is called a D-flip-flop, and when the pulse input to the terminal CK rises, it stores the pulse level input to the terminal D from the rising time to the next rising time, and stores the stored value at the terminal. This is to determine the phase of the signal output from Q, that is, the signal input to terminal CK and terminal D. That is, a signal representing the level of the signal applied to the terminal D from the NOT gate 8 at the time when the signal applied from the NOT gate 1 to the terminal CK rises and changes its level is derived from the terminal Q. In such a flip-flop 9, the output signal φ of the NOT gate 1 is connected to the terminal CK.
1' is input, and the output terminal φ2' of the NOT gate 8 is input to the terminal D, so that the signal Q4 shown in FIG. 3 is sent out from the terminal a. This signal Q4 is taken out from the rotate output terminal P4 as a rotate signal. Therefore, the clock signal Q3 is taken out from the clock output terminal P3, and the rotate signal Q4 is taken out from the rotate output terminal P4, and the rotational position of the stepping motor is detected based on these signals. FIG. 4 is a logic circuit diagram showing another embodiment of the present invention. Components that are the same as those shown in FIG. 2 are given the same reference numerals.
Input terminal P5 is connected to EX- via NOT gate 1.
It is connected to input terminal a of OR gate 2 and terminal D of flip-flop 11. The input terminal P6 is
It is connected to input terminal b of EX-OR gate 2 and terminal D of flip-flop 10 via NOT gate 8. The output terminal C of EX-OR gate 2 is
It is connected to the input terminal a of the EX-OR gate 6 and the input of the NOT gate 3. The output of the NOT gate 3 is connected to the input terminal b of the EX-OR gate 6 via an integrating circuit 4 consisting of a resistor R and a capacitor C and a NOT gate 5. The output terminal C of the EX-OR gate 6 is connected to the flip-flops 10, 11, 1
2 and the clock output terminal P7. Output terminal Q of flip-flop 10
is connected to the input terminal a of the EX-OR gate 13. Output terminal Q of flip-flop 11 is connected to terminal D of flip-flop 12. The output terminal Q of the flip-flop 12 is connected to the output terminal b of the EX-OR gate 13. Output terminal C of EX-OR gate 13 is rotate output terminal P8
connected to. Here, the NOT gate 3, the integrating circuit 4, and the NOT gate 5 constitute a one-shot pulse generating circuit 7 similar to that shown in FIG.
A phase determination circuit 14 is configured by the OR gate 13. The phase determination circuit 14 is a flip-flop 1
0, 11, 12 are in phase with each other or each other
It has means for outputting two outputs with a phase difference of 180°, and means for exclusive ORing the two outputs in an EX-OR gate 13 and outputting the result. Note that flip-flops 10, 11, and 12 are equivalent to the D-flip-flop described in FIG.

The operation of the circuit shown in FIG. 4 will be explained below based on the timing chart shown in FIG. Among the stepping motor drive signals, for example, a one-phase drive signal φ1 is applied to the input terminal P5 (FIG. 3, 1). For example, a two-phase drive signal φ2 having a phase difference of 90 degrees from the one-phase drive signal φ1 is applied to the input terminal P6 (FIG. 3, 2). These drive signals φ1 and φ2 are input to the EX-OR gate 2 via NOT gates 1 and 8, respectively (FIGS. 3 3 and 3 4), and EX
A signal Q1 shown in FIG. 3 is sent out from the output terminal C of the -OR gate 2. The signal Q1 becomes the signal Q2 shown in FIG. 3 by the delay circuit 7, and EX-OR
It is applied to input terminal b of gate 6. EX-OR
The gate 6 sends out a continuous one-shot pulse signal Q3 shown in FIG. 3 to the output terminal C in response to the signal Q1 applied to the input terminal a and the signal Q2 applied to the input terminal b. This signal Q3 is sent to the clock output terminal P7 and is used as a clock signal.

On the other hand, in flip-flop 10, terminal D is connected to
The output terminal φ2' of NOT gate 8 is input, and the terminal
Clock signal Q3 is slightly delayed from CK.
is input, the signal Q5 shown in FIG. 3 is output from the output terminal Q. Furthermore, in the flip-flop 11, the output signal φ1' of the NOT gate 1 is inputted to the terminal D, and the clock signal Q3 is inputted to the terminal CK with a slight timing delay, so that the output terminal Q outputs the signal Q6 shown in FIG. is output. Furthermore, the flip-flop 12 has a terminal
Since the clock signal Q3 is input to CK and the signal Q6 is input to the terminal D with a slight timing delay, the signal Q7 shown in FIG. 3 is output from the output terminal Q. where FIG. 3 9 and 11
As is clear from the above, the outputs of the flip-flops 10 and 11 have a phase difference of 180° when the stepping motor rotates to the left, and are in phase with each other when the stepping motor rotates to the right. These two outputs are exclusive ORed in EX-OR gate 13 and are shown in FIG.
The signal Q8 shown in 2 becomes the rotate output terminal P.
8. This signal Q8 is used as a rotate signal. Therefore, the rotational position of the stepping motor is detected based on the clock signal and rotate signal output from terminals P7 and P8, respectively.

In addition, in the above explanation, input terminals P1, P
NOT gates 1 and 8 were inserted in the next stage of 2, P5, and P6 for input waveform shaping and input/level conversion, but it is also possible to configure them with transistors instead. It does not need to be provided.

Effects As described above, according to the present invention, the signal of the drive signal line that drives the stepping motor is extracted,
A clock signal and a rotation signal for detecting the rotational direction of the stepping motor can be easily generated directly from the signal, and the rotational direction and rotational position of the stepping motor can be easily detected.

In addition, based on two drive signals of the stepping motor that have a phase difference of 90° from each other,
A clock signal is created by the exclusive OR of the exclusive OR signal of the two drive signals and the delayed signal of the exclusive OR signal, and the rotate signal is generated by (a) receiving the two drive signals and or (b) determining the level of one and the other drive signal at the rising or falling point of the clock signal. Signals representing each level are derived from the first and second means 10 and 11 respectively, the output of the second means 11 is delayed by one period of the clock signal and derived from the third means 12, and the output of the second means 11 is delayed by one period of the clock signal and is derived from the third means 12. Since the outputs of the three means 12 are taken out by exclusive ORing, the stepping motor position can be detected accurately without deteriorating the accuracy due to the minimum number of signal wiring and simple circuit configuration. be able to.

[Brief explanation of the drawing]

Fig. 1 is a connection diagram between the stepping motor M and the emission control unit E, Fig. 2 is a logic circuit diagram of an embodiment of the present invention, and Fig. 3 is a diagram of the circuit of Figs. 2 and 4. A timing chart for explaining the operation, and FIG. 4 is a logic circuit diagram of another embodiment of the present invention. 1, 3, 5, 8...NOT gate, 2, 6, 1
3...EX-OR gate, 9, 10, 11, 12
...Flip-flop, C...Capacitor, P
1, P2, P5, P6...Input terminal, P3, P7
...Clock output terminal, P4, P8... Rotate output terminal, R... Resistor.

Claims (1)

[Claims] 1. Creating a clock signal corresponding to the number of moving steps of the stepping motor used to detect the rotational position of the stepping motor, and a rotation signal that determines the rotational direction of the stepping motor. In the device, the clock signal is based on two drive signals having a phase difference of 90 degrees from each other among the drive signals of the stepping motor, and an exclusive OR signal of the two drive signals and an exclusive OR signal of the two drive signals. The rotated signal is extracted by exclusive OR with a delayed signal, and the rotated signal is extracted from a phase determining means that derives a signal representing the level of one drive signal at the time of rising or falling of the other drive signal. Stepping motor position detection device. 2. In an apparatus for creating a clock signal corresponding to the number of movement steps of the stepping motor used to detect the rotational position of the stepping motor, and a rotate signal for determining the rotational direction of the stepping motor, The signal is based on two drive signals having a phase difference of 90 degrees from each other among the drive signals of the stepping motor, and is an exclusive OR signal of the two drive signals and a delayed signal of the exclusive OR signal. A first means 10 for deriving a signal representing the level of one of the drive signals at the rising or falling point of the clock signal; a second means 11 for deriving a signal representing the level of the other drive signal, and an output of the second means 11 for one period of the clock signal;
A stepping motor position characterized in that it is extracted from a phase determining means having a third means 12 for deriving a delayed output, and a means 13 for taking an exclusive OR of the outputs of the first means 10 and the third means 12. Detection device.