SU1406712A1 - Synchronous detector - Google Patents

Abstract

This invention relates to automation. The purpose of the invention is to improve the detection accuracy. The detector contains the formaker 1 of the reference voltage, the key 2, the storage device 3, the counters 4 and 5, the decoders 6, 7 and 8, the EL-OR 9, the EL OR 10, the comparator II, NOT NO 12, threshold voltage source 13 and 1K trigger 14. When 2 input signals are received on the key, the level of which is lower than the source voltage threshold 13, information is stored in the storage device 3 according to the command generated by the decoder 7. When signals are detected with a level below the threshold voltage, the errors in determining the moment of formating the pulse Records that are caused by distortions of the reference voltage and non-stationary values of the phase shifts of the input and reference signals do not have a significant effect on the error of the output voltage of the detector. The goal is achieved by the introduction of counters 4 and 5, decoders 6, 7 and 8, E-OR 9, OR S and NOT 12, comparator AND, source 13 and 1K-trigger 14. 2 Il.

Description

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The invention relates to automation and can be used for synchronous demodulation of amplitude modulated signals.

The purpose of the invention is to improve the detection accuracy.

FIG. 1 shows a structural electrical circuit for a synchronic detector; in fig. 2 - time diagrams.

The synchronous detector contains the driver 1 of the reference voltage, the key 2, the storage device 3, the first and second counters 4 and 5, the first, second and third decoders 6, 7 and 8, the element AND-OR 9, the element OR 10, the comparator 11, element 12, source 13 threshold voltage 1K-trigger 14.

The synchronous detector works as follows: W. IM Image.

Shaper 1 receives a reference voltage (Fig. 2a), at the output of which a pulse form signal 20 is formed (Fig. 2c). The input of the key 2 receives the input signal (Fig. 26). The positive half-waves of the input signal are fixed with the help of a comparator 11, at the output of which a pulse-shaped signal is formed (Fig. 2d). The signal from the output of the comparator 11 through the element AND-OR 9 is fed to the control input of the operation of the first counter 4, which starts the counting of pulses of the clock frequency, 11th August to the other input of the counter. The output signals of the first counter 4 30 are fed to the first decoder 6, at the output of which a recording pulse generated at the time of maximum amplitude of the unsupported input signal is generated. The write pulse acts on the first input of the element OR 10, which controls the switch 2, which commutes the input voltage of the synchronous detector to the memory input.

With positive envelope values, the write pulse is formed at time dO time, which coincides with the maximum positive value of the carrier. At negative values of the envelope, the phase of the carrier changes by 180 °, and the input signal in this case is out of phase with the reference signal. In this case, the command for generating the write pulse arrives at the input of the first counter 4 from the output of the comparator 11, represented in inverse form (Fig. 2e), i.e., coincides in phase with the negative half-wave of the input signal.

Information about the phase of the reference voltage is fed from the output of driver 1 to the control input of the second counter 5, which starts the counting of clock pulses.

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1K flip-flop 14 at a time, for example, equal to a quarter of the reference frequency period (Fig. 2e). The inputs I and K of the 1K flip-flop 14 receive signals from the comparator 11, presented in direct and inverse forms, respectively. When the sign of the phases of the input signal and the reference voltage coincides, the synchronization pulse from the output of the third decoder 8 (Fig. 2e) 1K-trigger 14 generates a control signal (Fig. 2h), which, acting on the AND-OR element 9, is connected to the control input the first counter 4 of the comparator signal, presented in direct form, i.e., coinciding in phase with the positive half-period of the input signal. If the sign of the phases of the input and reference voltages does not coincide, the 1K-trigger 14 generates a control signal (FIG. 2i), which, acting on the AND-OR element 9, connects the KOMtiapaTQpa signal through the HE element 12 to the control input of the first counter 4. and presented in inverse form, i.e. coinciding in phase with a negative half-cycle of the input signal. In this case, the key control (Fig. 2k) is carried out with both a positive and negative sign of the envelope of the input signal.

With input signals whose level is below the threshold voltage (Fig. 26), which is determined by the source of the threshold voltage, information is recorded in the memory device according to a command generated at the output of the second decoder 7 (Fig. 2g). The output signal of the synchronous detector is shown in FIG. 2l.

When detecting signals with the level: 1x of the threshold voltage, the error in determining the moment of formation of the pulse, due to distortions of the reference voltage and non-stationary values of the phase shifts of the input and reference signals, does not significantly affect the error of the output voltage of the synchronous detector.

Claims (1)

Invention Formula A synchronous detector containing a voltage driver, a key whose input is the input of a synchronous detector, a memory device whose output is an output of the synchronous detector, characterized in that, to increase the accuracy of the detection, two counters are inserted into it, the decoder, the element AND-OR, the element OR, the com.parator, the element NOT, the source of the threshold voltage supplied to the counting input of the second and 1K trigger, and the input of the synchronous counter 5. In the process of counting to you the detector connect ene com- to the first input of the third decoder 8 is formed im g Arathor, the second input of which is connected to the pulse arriving at the input sinhronizatsiiistochnikom threshold voltage, and vy5 five 0 0 ABOUT five five 0 1K flip-flop 14 at a time, for example, equal to a quarter of the reference frequency period (Fig. 2e). The inputs I and K of the 1K flip-flop 14 receive signals from the comparator 11, presented in direct and inverse forms, respectively. When the sign of the phases of the input signal and the reference voltage coincides, the synchronization pulse from the output of the third decoder 8 (Fig. 2e) 1K-trigger 14 generates a control signal (Fig. 2h), which, acting on the AND-OR element 9, is connected to the control input the first counter 4 of the comparator signal, presented in direct form, i.e., coinciding in phase with the positive half-period of the input signal. If the sign of the phases of the input and reference voltages does not coincide, the 1K-trigger 14 generates a control signal (FIG. 2i), which, acting on the AND-OR element 9, connects the KOMtiapaTQpa signal through the HE element 12 to the control input of the first counter 4. and presented in inverse form, i.e. coinciding in phase with a negative half-cycle of the input signal. In this case, the key control (Fig. 2k) is carried out with both a positive and negative sign of the envelope of the input signal. With input signals whose level is below the threshold voltage (Fig. 26), which is determined by the source of the threshold voltage, information is recorded in the memory device according to a command generated at the output of the second decoder 7 (Fig. 2g). The output signal of the synchronous detector is shown in FIG. 2l. When detecting signals with the level: 1x of the threshold voltage, the error in determining the moment of formation of the pulse, due to distortions of the reference voltage and non-stationary values of the phase shifts of the input and reference signals, does not significantly affect the error of the output voltage of the synchronous detector. Invention Formula A synchronous detector containing a voltage driver, a key whose input is the input of a synchronous detector, a memory device whose output is an output of the synchronous detector, characterized in that, to increase the accuracy of the detection, two counters are inserted into it, the decoder, the AND-OR element, the OR element, the com.parator, the NOT element, the source of the threshold voltage and the 1K trigger, and the input of the synchronous detector is connected to the first input of the composer, the second input of which is connected to the source of the thresholds voltage, and the output of the comparator is connected to the first input of the AND-OR element, 1-input of the 1K-flip-flop and input of the NO element, the output of which is connected to the K-input of the 1K-flip-flop and the fourth input of the AND-OR element, the output of which is connected to the input control of the first counter, and the outputs of the first counter are connected to the inputs of the first decoder, the output of which through the OR element is connected to the control of the usable input of the key, the output of which is connected to the input of the storage device, and the counting inputs of the first and second counters are the input clock synchronous detector, the control input of the second counter is connected to the output of the reference voltage driver, the low-order outputs of the second counter are connected to the inputs of the second defroster, the output of which is connected to another input of the OR element, and the high-voltage outputs are connected to the inputs of the third decoder, the output of which is connected to the synchronization input of the 1K-flip-flop, the direct and inverse outputs of which are connected to the second and third inputs of the AND-OR element, respectively. e. Well LJL 3 tz: L Ljl l Vtinop