SU1336214A1 - Device for detecting digital signals reproduced from magnetic medium - Google Patents

Abstract

The invention is intended to increase the reliability of reproducible digital signals. The device contains an integrator 1, a subtractor 2, an analog comparator 5, a driver 6 clock pulses, O-flip-flop 7 and a low-pass filter 8. The introduction of digital comparators 10 and 11, the register 12 of the reference number, the keys 9, 13 and 16, the elements NOT 14 and 17, the sources 15 and 18 of the reference voltage, the element OR 19, and the counters 3 and 4 of the symbols "1 and" O, respectively, allows eliminate detection errors when playing long sequences from "O or" 1, followed by long "O or" 1. 2 Il. "(L with so O5

Description

The invention relates to a technique of digital magnetic recording and can be used, in particular, in digital video recording for detecting digital signals recorded in a non-zero way.

The purpose of the invention is to increase the reliability of reproducible information by eliminating detection errors, which arise from the reproduction of long sequences from "O or" 1, followed by long "O or" 1.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 - voltage plots that describe the operation of the device.

The device contains an integrator 1, the output of which is connected to the first input of the reader 2, with the first input of the counter 3 characters “1 and the second input of the counter 4 characters“ O. The output of the subtractor 2 is connected to the first input of the analog comparator 5, the second input of which is connected to the common bus. The input of the integrator 1 is connected to the input of the clock clock pulse generator, whose input is connected to the first input of the D-flip-flop 7, with the second input of the 3 characters counter “1 and the second input of the 4 characters counter“ O. The output of analog comparator 5 is connected to the second input of D-flip-flop 7 and to the input of low-pass filter 8, the output of which is connected to the first input of the third key 9. The output of the 3 characters counter “1 is connected to the first input of the first digital comparator 10, the output of the characters 4 “O is connected to the first input of the second digital comparator 11, the second input of the first digital comparator 10 and the second input of the second digital comparator 11 are connected to the output of the register 12 of the reference number. The first output of the first digital comparator 10 is connected to the third input of the 3 characters counter “1, and the first output of the second digital comparator 11 to the third input of the 4 characters counter“ O. The second output of the first digital comparator 10 is connected to the first input of the first switch 13 and to the input of the first circuit 14, the second input of the first switch 13 is connected to the output of the first source 15 of the reference voltage. The second output of the second digital comparator 11 is connected to the first input of the second key 16 and to the input of the second circuit NOT 17, and the second input of the second key 16 is connected to the output of the second source 18 of the reference voltage. The output of the first circuit NOT 14 is connected to the first input of the circuit OR 19, the output of the second circuit NOT 17 is connected to the second input of the circuit OR 19. The output of the latter is connected to the second input of the third key 9. The outputs of the first 13, second 16 and third 9 keys are connected to the second input subtractor 2.

The device works as follows.

The signal reproduced from the magnetic carrier is fed to the input of the integrator 1 and

input shaper 6 clock pulses. From the output of the integrator 1, the signal is fed to the first input of the subtractor 2, to the first input of the counter 3 characters "1 and to the first input of the counter 4 si. Waves" O. The clock pulses from the output of the clock pulse generator 6 are fed to the second input of the counter 3 characters "I, to the second input of the counter 4 characters" O and to the first input of the D-flip-flop 7. The output signal from the subtractor 2 is fed to the first input of the analog comparator 5, from the output of which it is fed to the second input of the D-flip-flop 7 and to the input of the filter 8, from the output of which it is fed to the first input of the third key 9.

If reproduced with magnetic

Q of the signal carrier, the number of the next “1 or” O does not exceed the value set in the register 12 of the reference number, then the first 13 and second 16 keys are closed by low potentials supplied to their first inputs from the second outputs of the first

5 digital comparator 10 and the second digital comparator 11, respectively. The third key 9 is opened by high potential, which is fed to its second input from digital comparators 10 and 11 through the circuits NOT 14 and 17

„And OR scheme 19.

If in the signal reproduced from the magnetic carrier the number of the following items “1 exceeds the value set in the register 12 of the reference number, then a high potential is formed at the second output of the first digital comparator 10, opening the first key 13, and through the first circuit is NOT 14 and the OR circuit 19, the second input of the third key 9 is supplied with a low potential closing it. In this case, the negative voltage from the output of the first source 15 of the reference voltage (Uom, Fig. 2c) goes through the first open key 13 to the second input of the subtractor 2. At its output, a positive voltage is obtained, which is fed to the analog comparator, excluding

5, thereby its false alarms, arising due to the fall of the flat top of the pulses corresponding to the long combinations of " 1 (Fig. 2).

If in the signal reproduced from the magnetic carrier the number of the following is additional

0 "o exceeds the value set in the register 12 of the reference number, then a high potential is formed at the second output of the second digital comparator 11, opening the second key 16, and through the second circuit

| - NOT 17 and the OR 19 circuit to the second input of the third key 9 is supplied with a low potential covering it. The positive voltage from the output of the second source 18 of the reference voltage (Uont, 2c) is

It goes through the open second key 16 to the second input of the subtractor 2. A negative voltage is obtained at its output, which is fed to the analog comparator, eliminating its false alarms due to the falling flat top of the pulses corresponding to the long combinations from "O. The level of the reference voltage must be sufficient to transfer the analog comparator 5 to the opposite state when exposed to unfavorable combinations, and must also be above the noise level of the 3-V channel to prevent false positives of the comparator 5.

After the termination of the same type of combinations, the counters 3 and 4 are reset, and the output of the digital comparators 10 and 11 forms a low potential, which leads to closing the keys 13 and 16 and opening the key 9. At the same time, the second input of the subtractor 2 receives voltage from the output of the filter 8, emitting a low frequency component. Since this voltage is zero at the moment when the key is closed, then under the action of unfavorable code combinations, the false positives of the analog comparator do not occur (Fig. 2d).

The selection of the threshold length of monotonous sequences (i.e., the reference number in register 12) is made taking into account the ACC of the playback channel so that within the monotone sequence less than the reference number, it is possible to confidently detect the conditions "O or" 1 by a conventional comparator ( in counters 3 and 4). In practice, this means a decrease in the flat top of the pulse of the currents, i.e., with “the reference length of the sequence, the signal at the output of the integrator 1 exceeds the noise level.

Counters 3 and 4 can be performed as described in 21.

g, U

Introducing new devices for character counters "1 and" O, two digital comparators, a reference number register, three keys, two NOT schemes, an OR circuit and two sources of reference voltages eliminates detection errors when playing back uncomfortable code combinations known device. This significantly improves the accuracy of the recording and the quality of the reproduced image.

Claims (1)

Invention Formula A device for detecting digital signals reproduced from a magnetic carrier, containing a series-connected integrator and subtractor, the output of which is connected to the first input of an analog comparator, the second input of which is connected to the common bus, and the output to the input of a low-pass filter, D-flip-flop, first input which is connected to the output of the comparator, and the second - to the output of the clock pulse generator, the input of which is connected to the integrator input, characterized in that, in order to increase the reliability of reproducible information by eliminating detection errors, the counters of the characters "1 and" O, the first and second digital comparators, the reference number register, the first, second and third keys, the first and second elements are NOT, the OR element, the first and second sources of reference voltages are entered into it. the first inputs of the character counter “1 and the character counter“ O are connected to the integrator output, the second inputs - with the output of the clock generator, and the outputs of the character counters “1 and the characters“ O - with the first inputs of the first and second digital comparatives, respectively ores, the second inputs of which are connected to the output of the register of the reference number, the first outputs to the third inputs of the character counter “I and the character counter“ O, the second outputs, respectively, with the first inputs of the first and second keys, the second input of the first key is connected to the output of the first the source of the reference voltage, and the second key - with the output of the second source of the reference voltage; To the inputs of the OR element, the output of which is connected to the control input of the third key, the input of which is connected to the output of the low-pass filter, and the outputs of the first, second and third keys are connected to the second input of the subtractor.  op.1 2 . OiuuffoK no