SU720504A1 - Device for sampling data from memory units - Google Patents

Description

one

Isoreoretation refers to the field of computer technology and can be used in devices for sampling data pulses and sync pulses (SI) when reading information from cyclic-action memory devices (memories), such as magnetic disk drives.

A device for retrieving information from memory units is known, comprising control units, the inputs of which are connected to the inputs of the first and second inverters and the outputs of the first and second AND-NES elements, one of the inputs of which are connected to the outputs of the control units and the inputs of the third and fourth inverters, the outputs of which are connected to one of the inputs of the third and fourth elements of the NAND, whose outputs are connected to the corresponding inputs of the trigger, and the other inputs of the third and fourth elements of the NAND are connected to the input busbar and to other inputs m of the first and second elements AND-NOT, the corresponding inputs of which are connected to the inputs of the trigger 1.

However, the known device can only be used in cases where

it is strictly determined that the first pulse arriving at the input of the device is a sync pulse. If this condition is not met, and it is not known whether the first pulse is a sync pulse or a data pulse, it is impossible to use such a device for separating data pulses and sync pulses.

The aim of the invention is to increase the speed of the device.

The goal is achieved by the fact that a device for retrieving information from memory blocks, containing control blocks, the outputs of which are connected to the inputs of the first and second inverters and the outputs of the first and second AND-NES elements, one of the inputs of which are connected to the outputs of the control blocks and the inputs of the third and fourth inverters, the outputs of which are connected to the outputs of the control units and the inputs of the third and fourth inverters, the outputs of which are connected to one of the inputs of the third and fourth elements AND-NOT, the outputs of which are connected The other inputs of the third and fourth elements AND-NOT are connected to the input bus and to the other inputs of the first and second elements AND-NOT, the corresponding inputs of which are connected to the inputs of the Trigger, are entered for the state of the trigger inputs, counters, additional triggers and a switch, one of the inputs of which is connected to the outputs of the first and second inverters and with the corresponding inputs of the meters connected via the state analysis blocks to the additional triggers whose outputs are connected us with other inputs of the switch. FIG. 1 is a functional block diagram of the device; in fig. 2 - time diagram of the device. The device contains the elements AND-NOT 1 4, the switch 5, which consists of elements AND 6 - 9 and elements OR 10, 11, inverters 12 - 15, trigger 16, additional triggers 17, 18, control units 19, 20, counters 21, 22, blocks of analysis of counters 23, 24. It is known, in accordance with the method of recording information in memory on magnetic disks, that in the pulse sequence read from the track of a magnetic disk there is service information, which is characteristic code combinations. For example, in a combination called an address marker, there is no additional p sync pulses, and the information in this area is represented by units (data pulses). The address marker is the only combination in which sync pulses may be missing. In a combination called a space, there are additional zeros. This condition must be met. These combinations are repeated in each of the recordings located on the magnetic disk track. This device uses the specified code combinations to separate the data and clock pulses. Let the first pulse read is a data pulse. In the initial state, the AND-NE 3 element is allowed by two inputs (Figs. 2–3, 5), and the first read pulse from the output of this element passes as a data pulse through the inverter 14 to the counting input of the counter 22, to the input of the installation in O of the counter 21 and to the second inputs of the And 6 - 9 elements. In addition, the first read pulse is fed to the input of the control unit 19 (Fig. 2 - 2). From its output comes a negative strobe signal (Fig. 2 - 3), which is a prohibitive signal for the element AND-HE 3 and at the same time allowing for the element AND-NOT 1. The second pulse received at the input of the device, if it is located in the strobe zone the signal generated by control unit 19 will be a sync pulse. This pulse passes through the element AND-NOT 1 (Figures 2-4) and changes the state of the trigger 16 (Figures 2-5, 6). Selected sync pulse from the output of the element AND-HE 4 (Fig. 2-7) through the inverter 15 is fed to the counting input of the counter 21, to the input of the installation in O of the counter 22 and to the second inputs of the elements AND-HE 7, 8. In addition, this pulse enters the input of the control unit 20. A negative strobe signal is removed from its output, which is prohibiting an AND-NO element 4 and allowing an AND-NOT element 2 (Figures 2-8). The next data pulse, if present, passes through the AND-HE 2 element, changes the state of the trigger 16, and passes to the output of the AND-HE element 3, etc. If there is no data pulse after the clock pulse, i.e. If the position is recorded as logical O, then during the entire time that the negative gate signal of the control unit 20 exists, the state of the trigger 16 does not change, and the next input pulse passes to the output of the AND-HE element 4 as a sync pulse. If there is no sync pulse after the data pulse, i.e., when the address marker is read, then during the entire time the negative gate signal of the control unit 19 exists, the trigger state 16 does not change and the next input pulse passes to the output of the AND-HE element 3 as a data pulse. Counters 21 and 22 continuously count the inverted signals arriving at them, respectively, from the outputs of blocks 14 and 15, i.e., counting zeros. If one of the counters counts more than the number of zeros, this means that the incoming sequence at its input is not a SI and can only be identified as data. The state analysis blocks of counters 23 and 24 are set to state + 1. Their output signals switch over triggers 18 and 19, respectively, which allow data pulses to pass through AND 7 and OR 10 elements, and sync pulses through AND 9 and OR 11 elements. The input pulses of each of the counters are applied to reset the counter included in the opposite branch in order to eliminate the counting of signals of zero positions that are not further. Using the device will allow you to select information recorded in the memory from an arbitrary pulse. th sequence and thereby reduce the average access time to the memory cyclic type doubled.

Claims (1)

Invention Formula A device for sampling and formation of memory blocks containing control units, the outputs of which are connected to the inputs of the first and second inverters and to the outputs of the first and second AND-NES elements, one of the inputs of which are connected to the outputs of the control units and the inputs of the third and fourth inverters, the outputs of which are connected to one of the inputs of the third and fourth elements of the NAND, whose outputs are connected to the corresponding inputs of the trigger, and the other inputs of the third and fourth elements of the NAND are connected to the input bus and to the other inputs of the first first and second AND-NO elements, the corresponding inputs which are connected to the trigger inputs, characterized in that, in order to increase the speed of the device, it contains meter state analysis blocks, counters, additional triggers and a switch, one of the inputs of which is connected to the outputs of the first and second inverters and to the corresponding meter inputs connected through the state analysis blocks of counters to additional triggers whose outputs are connected to other inputs of the switch. 0 Sources of information taken into account during the examination 1. USSR Author's Certificate No. 514338, cl. G And C 7/00, 1976. FIG. 1 Data