JPH06350364A - Automatic gain control circuit - Google Patents

Automatic gain control circuit

Info

Publication number
JPH06350364A
JPH06350364A JP13447693A JP13447693A JPH06350364A JP H06350364 A JPH06350364 A JP H06350364A JP 13447693 A JP13447693 A JP 13447693A JP 13447693 A JP13447693 A JP 13447693A JP H06350364 A JPH06350364 A JP H06350364A
Authority
JP
Japan
Prior art keywords
level
difference
output
amplifier
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13447693A
Other languages
Japanese (ja)
Other versions
JP3029361B2 (en
Inventor
Toshimichi Naoi
利道 直井
Haruhiro Shiino
玄博 椎野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP13447693A priority Critical patent/JP3029361B2/en
Publication of JPH06350364A publication Critical patent/JPH06350364A/en
Application granted granted Critical
Publication of JP3029361B2 publication Critical patent/JP3029361B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To allow a control circuit to cope with a large level fluctuation by providing a loop filter generating a steady-state fluctuation component corresponding to a steady-state fluctuation of an input analog signal level in a pre- stage of an integration device in a feedback loop so as to improve the tracking performance against a steady-state level fluctuation. CONSTITUTION:An analog signal received from an input terminal 10 is inputted to a level calculation means 3 via an A/D converter 2 to calculate an average power of the received signal. Then a logarithmic transformation means 8 transforms the power in a dB and a difference device 4 obtains a difference DELTAm between the signal subjected to dB transformation and a reference level. A loop filter 9 multiplies a constant beta2 by the difference DELTAm and obtains a DELTAM being the sum of an alpha0 being the integration of the result and a beta1XDELTAm. Then an integration device 5 integrates an output DELTAM from the filter 9 and its output Mn is converted into an analog signal by a D/A converter and it is converted into a control signal Gn by a response function (G)7. The gain is controlled by the signal Gn so that an output level of the amplifier 1 is made constant.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はディジタル通信の受信機
等に使用される自動利得制御回路に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic gain control circuit used in a digital communication receiver or the like.

【0002】[0002]

【従来の技術】図2は従来の自動利得制御回路の一例を
示すブロック図である。
2. Description of the Related Art FIG. 2 is a block diagram showing an example of a conventional automatic gain control circuit.

【0003】この自動利得制御回路は増幅器の利得を制
御することにより、該増幅器の出力レベルを一定に保持
するものである。すなわち、図2において、入力された
アナログ信号を増幅器1で増幅し、AD変換器2でディ
ジタル信号に変換し、レベル計算手段3で増幅器1の出
力の平均パワーを計算する。次いで、差分器4で前記平
均パワーとあらかじめ設定された基準レベルとの差を計
算し、これを積分回路5で積分した後DA変換器6でア
ナログ信号に変換する。このアナログ信号をレスポンス
関数7を通して増幅器1に供給し、その入力信号のレベ
ルが変動しても出力信号のレベルが一定になる様に増幅
器1の利得を制御する。
This automatic gain control circuit holds the output level of the amplifier constant by controlling the gain of the amplifier. That is, in FIG. 2, the input analog signal is amplified by the amplifier 1, converted into a digital signal by the AD converter 2, and the level calculating means 3 calculates the average power of the output of the amplifier 1. Then, the difference device 4 calculates the difference between the average power and a preset reference level, the integration circuit 5 integrates the difference, and the DA converter 6 converts the difference into an analog signal. This analog signal is supplied to the amplifier 1 through the response function 7, and the gain of the amplifier 1 is controlled so that the level of the output signal becomes constant even if the level of the input signal changes.

【0004】[0004]

【発明が解決しようとする課題】ところで、ディジタル
移動通信における移動局の受信機では、その受信信号の
レベルがフェージングにより激しく変動し、また移動局
が基地局に近付くに従って、或は遠ざかるに従ってその
受信信号のレベルがほぼ直線的に変動する(以下、この
変動を定常的な変動という)。このため、移動局の受信
機に使用する自動利得制御回路は、前記フェージングに
よる受信信号レベルの変動の下においても安定に動作
し、かつ、前記定常的な変動に対して十分に追従できる
ことが要求される。
By the way, in a receiver of a mobile station in digital mobile communication, the level of the received signal fluctuates drastically due to fading, and as the mobile station approaches or moves away from the base station, its reception is performed. The signal level fluctuates almost linearly (hereinafter, this fluctuation is called steady fluctuation). Therefore, it is required that the automatic gain control circuit used for the receiver of the mobile station operates stably even under the fluctuation of the received signal level due to the fading and can sufficiently follow the steady fluctuation. To be done.

【0005】しかしながら、上記構成による従来の自動
利得制御回路では、フェージングによる受信信号の変動
の下で安定に動作するように、レスポンス関数7を設定
すると定常的な変動に対する追従性が低下し、定常的な
変動に十分追従できるようにレスポンス関数7を設定す
るとフェージングによる受信信号の変動の下での動作が
不安定になるという問題点があった。
However, in the conventional automatic gain control circuit having the above configuration, if the response function 7 is set so as to operate stably under the fluctuation of the received signal due to fading, the followability to the steady fluctuation is lowered, and If the response function 7 is set so as to be able to sufficiently follow the dynamic fluctuation, there is a problem that the operation becomes unstable under the fluctuation of the received signal due to fading.

【0006】また、前述の移動局の受信機では、フェー
ジングにより受信信号のレベルが広い範囲で変動するた
め、受信機に使用する自動利得制御回路の動作範囲もそ
れに応じて広く設定する必要がある。
Further, in the above-mentioned receiver of the mobile station, the level of the received signal fluctuates in a wide range due to fading, so that the operating range of the automatic gain control circuit used in the receiver must be set wide accordingly. .

【0007】しかしながら、上記構成による従来の自動
利得制御回路の動作範囲を広く設定するためには、AD
変換器2、レベル計算手段3その他のディジタル部分を
桁数の大きなデータを取り扱えるように設定する必要が
あるため、使用するデバイスが大きくなり、価格も高く
なるという問題点があった。
However, in order to set a wide operating range of the conventional automatic gain control circuit having the above-mentioned configuration, AD
Since it is necessary to set the converter 2, the level calculation means 3, and other digital parts so as to handle data having a large number of digits, there is a problem that the device to be used becomes large and the cost becomes high.

【0008】本発明は上記の各問題点を解決するために
なされたものであって、帰還ループにループフィルタを
設けることにより激しい受信信号のレベル変動の下でも
安定に動作し、定常的な変動にも十分追従できるように
すると共に、対数変換手段を設けることにより広い範囲
でレベル変動する受信信号にも十分対応できるようにし
た優れた自動利得制御回路を提供することを目的とす
る。
The present invention has been made in order to solve the above problems, and by providing a loop filter in the feedback loop, the feedback loop operates stably even under drastic fluctuations in the level of the received signal, and steady fluctuations occur. It is an object of the present invention to provide an excellent automatic gain control circuit which is capable of sufficiently following the above, and is sufficiently adapted to a received signal whose level fluctuates in a wide range by providing a logarithmic conversion means.

【0009】[0009]

【課題を解決するための手段】本発明は上記目的を達成
するため、入力信号を増幅する増幅器と、前記増幅器の
出力の平均レベルを計算するレベル計算手段と、前記平
均レベルとあらかじめ設定した基準レベルとの差を計算
する差分器と、前記差の値を積分する積分器とを有し、
前記積分器の出力に基づいて前記増幅器の出力レベルが
一定になるようにその利得を制御する自動利得制御回路
において、前記レベル計算手段で計算した平均レベルを
対数変換して前記差分器へ出力する対数変換手段と、前
記差分器で計算した差の値に、前記差の値を積分した値
を加算して前記積分器へ出力するループフィルタとを設
けたものである。
In order to achieve the above object, the present invention provides an amplifier for amplifying an input signal, level calculation means for calculating an average level of the output of the amplifier, and the average level and a preset reference. A difference device for calculating the difference with the level, and an integrator for integrating the value of the difference,
An automatic gain control circuit that controls the gain of the amplifier based on the output of the integrator so that the output level of the amplifier is constant. The average level calculated by the level calculating means is logarithmically converted and output to the differencer. A logarithmic conversion unit and a loop filter for adding a value obtained by integrating the difference value to the difference value calculated by the difference unit and outputting the added value to the integrator are provided.

【0010】[0010]

【作用】前記ループフィルタで入力信号の定常的な変動
に対応する成分を生成しこれを前記積分器へ出力してい
るので、前記定常的な変動に追従することができる。ま
た、前記対数変換手段を設けたことによりレベル変動の
大きい入力信号にも対応することができる。
Since the loop filter generates the component corresponding to the steady fluctuation of the input signal and outputs it to the integrator, it is possible to follow the steady fluctuation. Further, by providing the logarithmic conversion means, it is possible to cope with an input signal having a large level fluctuation.

【0011】[0011]

【実施例】図1は本発明の実施例を示すブロック図であ
る。
FIG. 1 is a block diagram showing an embodiment of the present invention.

【0012】本実施例は図2に示す従来の自動利得制御
回路のレベル計算手段3と差分器4との間に対数変換手
段8を挿入し、差分器4と積分器5との間にループフィ
ルタ9を挿入したものであって、増幅器1、AD変換器
2、レベル計算手段3、差分器4、積分器5、DA変換
器6およびレスポンス関数7は図2において同一符号を
付したものと同様なものである。なお、レベル計算手段
3から積分器5に至るディジタル信号を取り扱う部分は
1個のDSP(Digital SignalProc
essor)で実現することができる。
In this embodiment, a logarithmic conversion means 8 is inserted between the level calculation means 3 and the difference unit 4 of the conventional automatic gain control circuit shown in FIG. 2, and a loop is provided between the difference unit 4 and the integrator 5. A filter 9 is inserted, and the amplifier 1, the AD converter 2, the level calculating means 3, the difference unit 4, the integrator 5, the DA converter 6 and the response function 7 have the same reference numerals in FIG. It is similar. The portion handling the digital signal from the level calculation means 3 to the integrator 5 is a single DSP (Digital Signal Proc).
can be implemented as an essay).

【0013】次に、本実施例の動作を図1に基づいて説
明する。
Next, the operation of this embodiment will be described with reference to FIG.

【0014】入力端子10から入力されたアナログ信号
は増幅器1で増幅され、AD変換器2でディジタル信号
に変換される。レベル計算手段3は前記ディジタル信号
を用いて受信信号の平均パワーを(1)式により計算す
る。
An analog signal input from the input terminal 10 is amplified by the amplifier 1 and converted into a digital signal by the AD converter 2. The level calculating means 3 calculates the average power of the received signal using the digital signal according to the equation (1).

【0015】[0015]

【数1】 [Equation 1]

【0016】次いで、対数変換手段8で前記RCV−P
OWを(2)式によりdB変換する。
Next, the RCV-P is converted by the logarithmic conversion means 8.
OW is converted to dB by the equation (2).

【0017】 LD = 10 log10(RCV−POW) (2) このdB変換により、PCV−POWの値が大きくなっ
てもLD は一定の値以下に抑えられるので、受信レベル
が大きくなっても差分器4からDA変換器6に至るディ
ジタル部分がオーバーフローを起こす様なことはない。
L D = 10 log 10 (RCV-POW) (2) By this dB conversion, L D can be suppressed below a certain value even if the value of PCV-POW becomes large, so the reception level becomes large. However, the digital portion from the difference unit 4 to the DA converter 6 does not overflow.

【0018】次いで、差分器4で前記dB変換した信号
D とあらかじめ設定された基準レベルLrとの差Δm
を(3)式により求める。
Next, the difference Δm between the signal L D, which has been dB-converted by the differentiator 4, and a preset reference level Lr.
Is calculated by the equation (3).

【0019】 Δm = LD −Lr (3) 増幅器1の出力レベルはこの基準レベルLrによって決
まってくる。
[0019] Δm = L D -Lr (3) the output level of the amplifier 1 will come determined by the reference level Lr.

【0020】次いで、ループフィルタ9で前記Δmに対
して(4)式、(5)式で表わされる計算を実行する。
Next, the loop filter 9 executes the calculations represented by the equations (4) and (5) for the Δm.

【0021】 αn = αn-1 + β2 Δm (4) ΔM = αn + β1 Δm (5) ただし、β1 ,β2 は定数である。Α n = α n-1 + β 2 Δm (4) ΔM = α n + β 1 Δm (5) However, β 1 and β 2 are constants.

【0022】すなわち、ループフィルタ9は、差分器4
から出力された差Δmに定数β2 を乗算し、これを積分
することにより得たαn と、前記差Δmに定数β1 を乗
算することにより得たβ1 Δmとを加算して(5)式に
表わされるΔMを算出するものである。
That is, the loop filter 9 includes the differentiator 4
The difference Δm output from the above is multiplied by a constant β 2 , and α n obtained by integrating this is added to β 1 Δm obtained by multiplying the difference Δm by a constant β 1 (5 ) Is used to calculate ΔM.

【0023】ここで、定数β1 の値は、増幅器1に入力
されるアナログ信号のレベルがフェージング等の影響を
受けて激しく変動する場合にも、増幅器1の出力がその
変動の影響を大きく受けることなく安定に所定の値に収
束するように設定する。しかし、この様にして定数β1
の値を設定した場合、増幅器1に入力されるアナログ信
号のレベルの定常的な変動に対する追従性が低下し、増
幅器1の出力レベルを一定に制御することが困難にな
る。そこで、本実施例では、差分器4から出力される差
Δmに定数β2 を乗算し、これを積分することにより定
常的な変動に比例した成分αn を生成し、積分器5へ出
力して増幅器1の利得を制御し、増幅器1の出力におけ
る定常的な変動を小さくするものである。定数β2 は増
幅器1の出力における定常的な変動が最も小さくなるよ
うに設定される。
Here, the value of the constant β 1 is greatly affected by the fluctuation of the output of the amplifier 1 even when the level of the analog signal input to the amplifier 1 is greatly changed due to the influence of fading or the like. It is set so that it converges stably to a predetermined value without However, in this way the constant β 1
If the value of is set, the followability to the steady fluctuation of the level of the analog signal input to the amplifier 1 is deteriorated, and it becomes difficult to control the output level of the amplifier 1 to be constant. Therefore, in the present embodiment, the difference Δm output from the differentiator 4 is multiplied by a constant β 2 and integrated to generate a component α n proportional to a steady fluctuation, and the component α n is output to the integrator 5. The gain of the amplifier 1 is controlled to reduce steady fluctuations in the output of the amplifier 1. The constant β 2 is set so that the steady fluctuation in the output of the amplifier 1 is minimized.

【0024】なお、図2に示す従来の自動利得制御回路
では、増幅器1の出力の収束時における安定性や収束の
迅速性の調整は、レスポンス関数(f)7のハードウェ
アを変更することにより行う必要があったので、その実
行は簡単ではなかった。しかし、本実施例では上述の収
束時の安定性や収束の迅速性を図1のループフィルタ9
の定数β1 の値を変更することにより調整するものであ
る。従って、このループフィルタ9を含むディジタル部
分をDSPで実現すれば定数β2 の値を容易に変更する
ことが可能になり、上述の収束時の安定性や収束時の迅
速性の調整も容易になる。
In the conventional automatic gain control circuit shown in FIG. 2, the stability of the output of the amplifier 1 at the time of convergence and the speed of convergence are adjusted by changing the hardware of the response function (f) 7. It wasn't easy to do because I had to do it. However, in the present embodiment, the loop filter 9 shown in FIG.
It is adjusted by changing the value of the constant β 1 of. Therefore, if the digital portion including the loop filter 9 is realized by a DSP, the value of the constant β 2 can be easily changed, and the above-mentioned stability at the time of convergence and swiftness at the time of convergence can be easily adjusted. Become.

【0025】次いで、積分器5でループフィルタ9から
の出力ΔMを積分する。積分器5の出力Mn は(6)式
で表わされる。
Next, the integrator 5 integrates the output ΔM from the loop filter 9. The output M n of the integrator 5 is expressed by equation (6).

【0026】 Mn = Mn-1 + ΔM (6) 積分器5の出力Mn をDA変換器6でアナログ信号に変
換し、レスポンス関数(G)7で制御信号Gn に変換
し、この制御信号Gn により増幅器1の出力レベルが一
定になるように、その利得を制御する。レスポンス関数
としては、例えば(7)式で表わされる線形式を用い
る。
M n = M n-1 + ΔM (6) The output M n of the integrator 5 is converted into an analog signal by the DA converter 6, and converted into a control signal G n by the response function (G) 7. The gain is controlled by the control signal G n so that the output level of the amplifier 1 becomes constant. As the response function, for example, the linear form represented by the equation (7) is used.

【0027】 Gn = aMn+b (7) ただし、a,bは定数である。G n = aM n + b (7) where a and b are constants.

【0028】なお、ループフィルタ9の定数β1 ,β2
を乗ずる位置は、上記実施例に限定されるものではな
く、これと同じ効果を与えるならば、他の位置で、
β1 ,β2を乗じても良い。
The constants β 1 and β 2 of the loop filter 9 are
The position for multiplying by is not limited to the above-mentioned embodiment, and if the same effect is given, at other positions,
It may be multiplied by β 1 and β 2 .

【0029】[0029]

【発明の効果】以上、詳細に説明したように本発明によ
れば、入力アナログ信号レベルの定常的な変動に対応す
る定常的な変動成分を生成するループフィルタを、帰還
ループの積分器の前段に設けたので、前記定常的な変動
に追従し、これを補償することが可能になる。従って、
本発明は受信信号レベルが定常的に変動する移動局の受
信機に使用する自動利得制御回路等に適している。
As described above in detail, according to the present invention, the loop filter for generating the steady fluctuation component corresponding to the steady fluctuation of the input analog signal level is provided at the front stage of the integrator of the feedback loop. Since it is provided in the above, it becomes possible to follow the above-mentioned steady fluctuation and compensate for this. Therefore,
INDUSTRIAL APPLICABILITY The present invention is suitable for an automatic gain control circuit or the like used in a receiver of a mobile station whose received signal level constantly fluctuates.

【0030】また、帰還ループのディジタル部分の前段
に入力信号の値を対数変換する対数変換手段を設けたの
で、レベル変動の大きな入力アナログ信号を取り扱うこ
とができる。
Further, since the logarithmic conversion means for logarithmically converting the value of the input signal is provided in the preceding stage of the digital portion of the feedback loop, it is possible to handle an input analog signal having a large level fluctuation.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例を示すブロック図である。FIG. 1 is a block diagram showing an embodiment of the present invention.

【図2】従来の自動利得制御回路を示すブロック図であ
る。
FIG. 2 is a block diagram showing a conventional automatic gain control circuit.

【符号の説明】[Explanation of symbols]

1 増幅器 2 AD変換器 3 レベル計算手段 4 差分器 5 積分器 6 DA変換器 7 レスポンス関数 8 対数変換手段 9 ループフィルタ DESCRIPTION OF SYMBOLS 1 amplifier 2 AD converter 3 level calculation means 4 difference device 5 integrator 6 DA converter 7 response function 8 logarithmic conversion means 9 loop filter

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 入力信号を増幅する増幅器と、前記増幅
器の出力の平均レベルを計算するレベル計算手段と、前
記平均レベルとあらかじめ設定した基準レベルとの差を
計算する差分器と、前記差の値を積分する積分器とを有
し、前記積分器の出力に基づいて前記増幅器の出力レベ
ルが一定になるようにその利得を制御する自動利得制御
回路において、 前記レベル計算手段で計算した平均レベルを対数変換し
て前記差分器へ出力する対数変換手段と、 前記差分器で計算した差の値に、前記差の値を積分した
値を加算して前記積分器へ出力するループフィルタとを
設けたことを特徴とする自動利得制御回路。
1. An amplifier for amplifying an input signal, level calculating means for calculating an average level of the output of the amplifier, a differencer for calculating a difference between the average level and a preset reference level, and a difference calculator for calculating the difference. An automatic gain control circuit having an integrator that integrates a value, and controlling the gain of the amplifier based on the output of the integrator so that the output level of the amplifier is constant, the average level calculated by the level calculation means A logarithmic conversion means for logarithmically converting and outputting the logarithmic difference to the difference unit, and a loop filter for adding to the difference value calculated by the differencer a value obtained by integrating the difference value and outputting the added value to the integrator. An automatic gain control circuit characterized by the above.
JP13447693A 1993-06-04 1993-06-04 Automatic gain control circuit Expired - Lifetime JP3029361B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13447693A JP3029361B2 (en) 1993-06-04 1993-06-04 Automatic gain control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13447693A JP3029361B2 (en) 1993-06-04 1993-06-04 Automatic gain control circuit

Publications (2)

Publication Number Publication Date
JPH06350364A true JPH06350364A (en) 1994-12-22
JP3029361B2 JP3029361B2 (en) 2000-04-04

Family

ID=15129221

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JP13447693A Expired - Lifetime JP3029361B2 (en) 1993-06-04 1993-06-04 Automatic gain control circuit

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103558897A (en) * 2013-11-18 2014-02-05 梁淮宁 Virtual-gain-bridge-based automatic gain control method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103558897A (en) * 2013-11-18 2014-02-05 梁淮宁 Virtual-gain-bridge-based automatic gain control method

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JP3029361B2 (en) 2000-04-04

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