JPH06350093A - Manufacture of nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a nonvolatile semiconductor memory which forms an oxide film enabling the charge holding characteristic to be improved on the sides of a floating gate. CONSTITUTION:A silicon oxide 16 covering over a silicon substrate 10, which contains the top and sides of a control gate electrode 14 and the sides of a suspended gate electrode 13, is formed by thermal oxidation or chemical vapor phase epitaxy. And it is subjected to rapid nitriding within 60 seconds by infrared lamp heating in an NH3 atmosphere over a substrate temperature range of 800 deg. to 1100 deg.C to convert a silicon oxide 16 to silicon nitride oxide 16'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device, and more particularly to a method for manufacturing an oxide film thereof.

[0002]

2. Description of the Related Art In considering the reliability of a non-volatile semiconductor memory device, deterioration of charge retention characteristics accumulated in a memory cell is a serious problem. The deterioration of the charge retention characteristic mainly depends on the following two factors. One is the quality of the oxide film that covers the floating gate electrode, and the other is the internal quality of the semiconductor memory device.
And the existence of mobile ions such as Na, K, and Li that enter from the outside. If there is a region of poor film quality such as a pinhole in the oxide film, the charge accumulated in the floating gate electrode is discharged through the region to the outside of the floating gate electrode, deteriorating the charge retention characteristic. In addition, the movable ions are attracted to the vicinity of the floating gate electrode by the electric field due to the electric charge accumulated in the floating gate electrode, and cancel the electric field due to the accumulated electric charge. As a result, the threshold voltage of the memory cell is lowered.

Further, in the electrically erasable non-volatile semiconductor memory device (EEPROM), when the oxide film quality is poor, an interface state is generated or a carrier trap is generated during the writing and erasing operations, and the threshold voltage is changed. Will cause

Further, when the energy barrier of the oxide film is lowered by the carrier trap, the threshold voltage may fluctuate during the read operation. FIG. 5 is a diagram showing a cross-sectional structure of a memory cell of a nonvolatile semiconductor device. In the figure, 20 is a silicon substrate, and 21 is an impurity diffused region formed on the silicon substrate to serve as a source or a drain. Reference numeral 22 is a first oxide film formed on the silicon substrate 20, and 23 is a floating gate electrode formed on the first oxide film. 24 is a second oxide film formed on the floating gate electrode 23, and 25 is a control gate electrode formed on the second oxide film. Reference numeral 26 is a third oxide film formed on the entire surface of the silicon substrate 20, and 27 is a BPSG film formed as a planarizing material on the third oxide film. Reference numeral 28 denotes a BPSG film 27 and an oxide film so that the surface of the impurity diffusion region 21 at a predetermined place is exposed.
Reference numeral 26 is a contact hole opened, and reference numeral 29 is an aluminum wiring layer formed continuously from the upper surface of the BPSG film to the contact hole.

In the memory cell having the above structure, it is considered that there are four discharge paths of the charges accumulated in the floating gate electrode 23 to the outside of the floating gate electrode. The first emission path is from the floating gate electrode 23 through the first oxide film 22 to the silicon substrate 20.
To the control gate electrode 25 from the floating gate electrode 23 through the second oxide film 24, and the third emission path is the floating gate electrode.
23 is a path from the end of the floating gate electrode 23 to the third oxide film 26 or the first oxide film 22 to the silicon substrate 20, and the fourth release path is from the end of the floating gate electrode 23 to the third oxide film. 26 or a path through the second oxide film 24 to the control gate electrode 25.

In the first emission path, the silicon substrate 20 is a single crystal and has a small surface roughness. Therefore, the first oxide film 22 formed on the substrate is dense and has good film quality. Therefore, it is considered that there is almost no charge emitted from the floating gate electrode 23 through the first emission path. In addition, the second oxide film 24 in the second release path is generally formed by a laminated film of a silicon oxide film and a silicon nitride film, and it has been confirmed that the oxide film of this structure is difficult for charges to pass through. It is considered that almost no electric charge is emitted from the floating gate electrode 23 by the second emission path. Also, the third,
In the fourth emission path, the insulating films 22 and 24 adjacent to the ends of the floating gate electrode 23 may be damaged by RIE (Reactive Ion Etching) when the gate electrodes 23 and 25 are processed and formed. Yes, because the floating gate electrode 23 is composed of polycrystalline silicon, there is a crystal grain boundary, or due to the fact that the dopant introduced for low resistance is deposited on the crystal surface, The film quality of the oxide film 26 formed on the side surface of the floating gate electrode 23 is not good. Therefore, it is considered that the charge is easily discharged from the floating gate electrode 23 to the silicon substrate 20 or the control gate electrode 25 by the third and fourth discharge paths. In addition, the RI
The deterioration of the oxide film quality due to damage by E is caused by EEPRO
It is considered that this is a cause of the threshold voltage fluctuation during the write / erase operation of M.

Mobile ions that enter the memory cell at the time of manufacturing can be gettered by phosphorus contained in the BPSG film 27 which is an insulating film in the device. Since the PSG film also contains phosphorus, it may be used instead of the BPSG film 27. In addition, mobile ions penetrating from the outside of the nonvolatile semiconductor memory device can be gettered to the passivation film by forming a passivation film (not shown) with a PSG film. Therefore, since the mobile ions cannot neutralize the charges stored in the floating gate electrode 23, the deterioration of the charge retention characteristics is prevented.

[0008]

By the way, as the capacity of a non-volatile semiconductor memory device is increased, the transistor element forming a memory cell becomes finer and higher in density, and becomes a source or a drain. The transistor characteristics as designed cannot be obtained due to the influence of the short channel effect that occurs when the impurities implanted into the region diffuse to the channel region. Therefore, in order to reduce the diffusion of impurities and suppress the short channel effect, it is inevitable to manufacture a semiconductor memory device having a large capacity in a low temperature process. The reliability of the oxide film formed in that case is low.

Further, as the transistor element becomes finer and thinner, the insulating film made of the BPSG film and the PSG film is made thinner, and the wiring interval is reduced, so that the PSG passivation film formed on the sidewall of the wiring layer is formed. The gettering effect decreases due to the thinning.

As described above, as the memory cells constituting the non-volatile semiconductor memory device are further miniaturized and thinned, the reliability of the oxide film and the gettering effect are deteriorated and the charge retention characteristics are deteriorated. It is considered that the charge retention characteristic is deteriorated due to charge neutralization of mobile ions due to charge release from the third and fourth release paths and a reduction in gettering effect.

The present invention has been made in view of the above circumstances, and an object thereof is to manufacture a non-volatile semiconductor memory device in which an oxide film capable of improving charge retention characteristics is formed on a side surface of a floating gate. Is to provide a method.

[0012]

A method of manufacturing a nonvolatile semiconductor memory device according to the present invention comprises a step of forming a silicon oxide film covering a side surface of a floating gate electrode and a control gate electrode wiring layer, and a step of nitriding the silicon oxide film. And a heat treatment in an atmosphere to form a silicon oxynitride film.

[0013]

The silicon oxynitride film has a larger insulation resistance than the silicon oxide film, and has a higher effect of preventing invasion of mobile ions, and the dangling bond of the oxide film damaged by RIE is nitrided or nitrided and reoxidized. Since the termination is performed, the charge retention characteristic of the floating gate electrode is improved, and in the EEPROM, the threshold voltage fluctuation during writing and erasing operations is further suppressed.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. 1A to 1D are cross-sectional views showing manufacturing steps when the present invention is applied to manufacture of a nonvolatile semiconductor memory device using a P-type single crystal silicon substrate.

The first embodiment of the method of manufacturing a nonvolatile semiconductor memory device according to the present invention is performed as follows. First, a first silicon oxide film 11 having a film thickness of 20 nm is formed on a P-type silicon substrate 10 shown in FIG. Then, on the silicon oxide film 11, polycrystalline silicon to be a floating gate electrode is deposited to a film thickness of 200 nm. And
A second silicon oxide film 12 is formed on the polycrystalline silicon 30
It is formed to a film thickness of nm. Next, a laminated film of polycrystalline silicon and silicide, which will serve as a control gate electrode, is deposited to a film thickness of 500 nm. Then, the floating gate electrode is etched by photolithography from the laminated film to the first oxide film 11 in the region other than the gate electrode formation region.
A laminated gate structure including 13 and the control gate electrode 14 is formed. As a result, the state shown in FIG.

Next, as shown in FIG. 1B, N-type impurities, such as arsenic or phosphorus, are ion-implanted into the regions of the silicon substrate 10 serving as the source and the drain by using the above-described laminated gate structure as a mask. A diffusion region 15 is formed. Next, the top and side surfaces of the gate electrode 14 and the gate electrode 13
The silicon oxide film 16 covering the substrate 10 including the side surfaces of the substrate is heated in an oxidizing atmosphere at a substrate temperature of 800 ° C.
A thermal oxide film is formed at a temperature of 950 ° C. and a thickness of 20 nm. Alternatively, the silicon oxide film 16 is formed by using TEOS gas or TEOS gas and N ₂ gas at a temperature of 600 ° C.
A CVD oxide film having a film thickness of 20 nm is formed in the range of 750 ° C. by the chemical vapor deposition method. Then, the substrate temperature is 800 ° C. to 110 ° C. in an NH ₃ atmosphere using infrared lamp heating.
Rapid nitriding within 60 seconds within the range of 0 ° C. is performed to change the silicon oxide film 16 into a silicon oxynitride film 16 ′.
(C) state.

Next, although not shown, B or BF ₂ is selectively ion-implanted into a region to be a P-type diffusion layer. The reason why the ion implantation is performed after the silicon oxide film 16 is formed is that B has a large diffusion coefficient, so that the short channel effect becomes remarkable before the formation of the silicon oxide film 16.

Next, as shown in FIG. 1D, a BPSG film 17 containing phosphorus is deposited on the silicon oxynitride film 16 'and flattened by reflow. Then, the BPSG film 17 is exposed so that the surface of the impurity diffusion region 15 at a predetermined place is exposed.
A contact hole 18 is formed by opening the silicon oxynitride film 16 '. Then, an Al alloy is deposited on the entire surface by, for example, sputter deposition to a thickness of 800 nm, and the wiring layer 19 is formed by patterning, leaving the contact hole 18 continuous to the upper surface of the BPSG film 17.

Since the silicon oxynitride film 16 'formed by the rapid nitriding has nitrogen atoms bonded to the dangling bonds of silicon atoms and oxygen atoms in the silicon oxide film 16, the trap density is reduced. , The insulation resistance is high. In addition, the insulating film 2 adjacent to the end of the floating gate electrode
The damage due to RIE of 2 and 24 is also due to the breakage of SiO ₂ bonds, so that the unbonded hands can be terminated by rapid nitriding. Therefore, it becomes difficult for the charges stored in the floating gate electrode 13 to pass through the silicon oxynitride film 16 ′ that covers the side surface of the floating gate electrode 13, and the charge retention characteristics are improved. Further, since the trap densities of the silicon oxynitride film 16 'and the insulating films 22 and 24 at the ends of the floating gate electrodes are lower than that of the silicon oxide film, the threshold voltage at the time of writing, erasing and reading operations of the EEPROM is Fluctuations can be suppressed. Further, the silicon oxynitride film is closer to the characteristics of the silicon nitride film as compared with the silicon oxide film, and the invasion of mobile ions such as Na ⁺ into the floating gate electrode 13 is suppressed, so that the charge retention characteristic is improved. There is.

Next, a method of manufacturing a nonvolatile semiconductor memory device according to the second embodiment of the present invention will be described. This embodiment is different from the first embodiment in that the silicon oxynitride film 16 'is reoxidized, and the other points are the same as those in the first embodiment. The reoxidation is performed by rapid nitriding of the silicon oxide film 16 to form a silicon oxynitride film 16 ', and then further rapid oxidation in which the substrate temperature is kept at 800 to 1100 ° C. for 60 seconds in an oxygen atmosphere.

In the silicon oxynitride film 16 'before reoxidation, many dangling bonds of silicon atoms and oxygen atoms are present near the contact interface with the polycrystalline silicon forming the floating gate electrode 13. is doing. Then, when the re-oxidation is performed, the nitrogen taken into the oxynitride film 16 'comes to be distributed mainly in the vicinity of the contact interface, and the nitrogen atom is bonded to the dangling bond. As a result, the trap density of the silicon oxynitride film 16 'is lower than that before reoxidation, and the charge retention characteristic is further improved.

Next explained is a method of manufacturing a nonvolatile semiconductor memory device according to the third embodiment of the invention. This embodiment is different from the first embodiment in the method of manufacturing the silicon oxynitride film 16 ', and the other points are the same as those in the first embodiment.
In the first embodiment, the silicon oxynitride film 16 'is formed by rapidly nitriding the silicon oxide film 16 once formed, but in this embodiment, the substrate temperature is set to 80 in an N ₂ O atmosphere.
The silicon oxynitride film 16 'is formed by rapid nitriding oxidation so that the temperature of 0 to 1100 ° C continues for 300 seconds or more.
Is formed.

In the third embodiment, a silicon oxynitride film having a trap density smaller than that of the silicon oxide film can be manufactured by a process shorter than those in the first and second embodiments.
FIG. 2 shows comparison between the charge retention characteristics of the memory cells of the nonvolatile semiconductor memory device manufactured by the conventional technique and the memory cells of the nonvolatile semiconductor memory device manufactured by the present invention. Specifically, data is written in each memory cell, and the change over time in the threshold voltage of the memory cell when the memory cell is left in an atmosphere of 300 ° C. is examined. In other words, the writing of the above-mentioned data is to accumulate charges in the floating gate electrode. Since the threshold voltage of the memory cell is higher as the amount of accumulated charges is larger, the threshold voltage changes with time. It can be said that the smaller the number, the better the charge retention characteristics.

In the figure, 30 is the threshold voltage of the memory cell according to the prior art, 31 is the threshold voltage of the memory cell in the case of rapid nitriding in the first embodiment, and 32 is reoxidation in the second embodiment. The threshold voltage of the memory cell in the above case, 33 is the threshold voltage of the memory cell in the case of rapid nitriding and oxidation in the third embodiment. As is clear from this figure, the change in the threshold voltage with respect to the threshold voltage of the memory cell at the time of data writing is not affected by the change of the threshold voltage of the memory cell at the time of data writing in any of the memory cells according to the first to third embodiments. It is smaller than the conventional memory cell. Therefore, it is understood that the charge retention characteristics of the memory cell embodying the present invention are superior to the conventional ones.

FIG. 3 shows a comparison of the endurance characteristics of the memory cells of the electrically written / erased non-volatile semiconductor memory device manufactured according to the prior art and the electrically programmed / erased nonvolatile semiconductor memory device manufactured according to the present invention. It was done. The endurance characteristic is a change in threshold voltage when writing and erasing are repeatedly performed on a memory cell. FIG. 3 shows the endurance characteristics of a memory cell of the type in which the threshold voltage in the written state is set to a positive value and the threshold voltage in the erased state is set to a negative value, and the NAND type EEPROM and FLOTOX type are shown. E
It corresponds to the characteristics of EPROM. These types of EEP
The ROM has a thickness of the oxide film 22 of about 10 nm,
By applying an electric field of about 12 MV / cm, Fo
wler-Nordheim Current is passed to erase. In the endurance characteristic, the difference between the positive threshold voltage and the negative threshold voltage is called a window, and the phenomenon that this difference becomes smaller as the number of write / erase times increases is called window narrowing.

A band diagram for explaining this phenomenon is shown in FIG. FIG. 4 (a) shows the flow of the Fowler-Nordheim current in the absence of electron traps in the oxide film, and FIG. 4 (b) shows the Fowler-Nordh current in the condition where electron traps occur in the oxide film.
eim Shows the current flow. When writing and erasing are repeated, electron traps are generated in the tunnel oxide film 22. In such a state, the Fowler-Nordheim current is reduced, so that sufficient erasing is not performed and window narrowing occurs. Since the data in the memory cell is inverted when the window narrowing becomes large, it is important to form an oxide film in which the window narrowing does not become large.

Characteristic 40 in FIG. 3 is the endurance characteristic of the memory cell according to the prior art, 41 is the endurance characteristic of the memory cell when rapid nitriding is performed in the first embodiment of the present invention, and 42 is the present invention. 43 shows the endurance characteristics of the memory cell when reoxidized in the second embodiment, and 43 shows the endurance characteristics of the memory cell when subjected to rapid nitriding oxidation in the third embodiment of the present invention. As is clear from this figure, the window narrowing is smaller in the memory cells of the first, second and third embodiments than in the memory cells of the prior art. This is because the nitrogen atoms are bonded to the dangling bonds existing in the regions of the third oxide films 23 and 25 which have undergone the blunting, so that electron traps are less likely to occur. Therefore, it can be seen that the endurance characteristic of the memory cell in which the present invention is implemented is superior to the conventional one.

In the above description, the NAND type EEPROM is used.
Fowler-Nordh like M and FLOTOX type EEPROM
I used a memory cell that used eim current for programming and erasing.
The same applies to writing in a NOR type EEPROM or the like using hot electron injection and erasing using a Fowler-Nordheim current.

Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications and applications are possible. For example, the first
In the above example, an NH ₃ atmosphere is used for rapid nitriding.
N ₂ O atmosphere may be used. Although an infrared lamp is used for heating for the rapid nitriding, a rapid heating / cooling furnace may be used. Further, the nitriding, re-oxidizing, or nitriding / oxidizing temperature may be a temperature other than those in the above-described embodiments. For example, when silicide is used for the control gate electrode, the silicide layer may be peeled off due to stress due to rapid heating and quenching. In such a case, the temperature may be 800 ° C or lower. Further, although the P-type single crystal silicon substrate is used in the above embodiment,
An N-type single crystal silicon substrate may be used, in which case P-type impurities such as boron may be ion-implanted to make the semiconductor main surface P-type, or P-type impurities such as boron may be ion-implanted into the source and drain regions. Then, the P-type diffusion layer may be formed. Further, in the above-mentioned embodiment, the laminated film of polycrystalline silicon and silicide is used for the second gate electrode, but the gate electrode may be formed of only polycrystalline silicon or only of silicide. Further, instead of the second silicon oxide film, an insulating film having a laminated structure of a silicon oxide film and a silicon nitride film may be used.

Although the silicon oxide film 16 has been described as being formed using TEOS gas or TEOS gas and N ₂ gas, the present invention is not limited to this.
A film may be formed in the range of 750 ° C. to 900 ° C. by using H ₂ + N ₂ O, or SiH ₄ + N ₂ O or SiH
₄ + NO may be used to form a film in the range of 650 ° C to 850 ° C. Further, the formation of the silicon oxide film by the CVD method can be performed by using various gas species and temperatures other than the above. Further, the film thickness of the silicon oxide film 16 is not limited to 20 nm, and the lower limit is 6 nm in terms of charge loss, and ion implantation of the diffusion layer may be performed after film formation. In that case, ions are implanted. Since the upper limit of the easy film thickness is about 30 nm, it may be in the range of 6 nm to 30 nm.

[0031]

As described above, according to the present invention, it is possible to provide a method of manufacturing a nonvolatile semiconductor memory device in which an oxide film capable of improving the charge retention characteristic is formed on the side surface of the floating gate.

[Brief description of drawings]

FIG. 1 is a sectional view showing a manufacturing process of a nonvolatile semiconductor memory device in accordance with a first embodiment of the present invention.

FIG. 2 is a charge retention characteristic diagram of a memory cell.

FIG. 3 is a diagram showing the endurance characteristics of memory cells of an electrically programmable erasing type nonvolatile semiconductor memory device manufactured according to the prior art and the present invention in comparison.

FIG. 4 is a band diagram for explaining a window narrowing phenomenon.

FIG. 5 is a cross-sectional view of a conventional nonvolatile semiconductor device.

[Explanation of symbols]

10 ... Silicon substrate, 11, 12, 15 ... Oxide film, 13 ... Floating gate electrode, 14 ... Control gate electrode, 16 '... Silicon oxynitride film, 17 ... BPSG film.

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[Procedure amendment]

[Submission date] July 19, 1993

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 4

[Correction method] Change

[Correction content]

[Figure 4]

Claims (5)

[Claims] 1. A step of forming a stacked gate structure comprising a floating gate electrode and a control gate electrode on a semiconductor substrate, a step of coating the stacked gate structure with a silicon oxide film, and a step of covering the silicon oxide film in a nitriding atmosphere. And a step of heat-treating the silicon nitride oxide film to form a silicon oxynitride film. 2. The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, further comprising the step of reoxidizing the silicon oxynitride film in an oxidizing atmosphere. 3. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the silicon oxide film is a thermal oxide film formed in an oxidizing atmosphere. 4. The silicon oxide film is an oxide film formed by a chemical vapor deposition method.
Alternatively, the method for manufacturing the non-volatile semiconductor memory device according to the second aspect. 5. A method of manufacturing a non-volatile semiconductor device, comprising the step of forming a silicon oxynitride film covering the side surface of the floating gate electrode and the control gate electrode wiring layer by heat treatment in a nitriding and oxidizing atmosphere. .