JPH06350047A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPH06350047A
JPH06350047A JP5133743A JP13374393A JPH06350047A JP H06350047 A JPH06350047 A JP H06350047A JP 5133743 A JP5133743 A JP 5133743A JP 13374393 A JP13374393 A JP 13374393A JP H06350047 A JPH06350047 A JP H06350047A
Authority
JP
Japan
Prior art keywords
substrate
substrate electrode
electrode
shape
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5133743A
Other languages
Japanese (ja)
Inventor
Tomohiro Horiuchi
智博 堀内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP5133743A priority Critical patent/JPH06350047A/en
Publication of JPH06350047A publication Critical patent/JPH06350047A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To increase cell capacitance without increasing the cell area. CONSTITUTION:In a laminated substrate electrode 1 which forms a memory capacitor, its top face is so shaped that the outer periphery may be longer despite of the same area as in the prior art. This can increase the side face area of the substrate electrode, thereby increasing the memory cell capacitance Cs.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体メモリ装置に関
し、特にメモリ容量部を形成する基板電極の形状に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to the shape of a substrate electrode forming a memory capacitor portion.

【0002】[0002]

【従来の技術】従来のスタック型半導体メモリ装置を示
す図5を参照すると、この装置は、基板電極1と、容量
絶縁膜2と、容量電極3と、リード電極4と、N型拡散
層5と、半導体基板6とを備え、メモリ容量部分は、基
板電極1と容量電極3との間に形成される。
2. Description of the Related Art Referring to FIG. 5 showing a conventional stack type semiconductor memory device, this device has a substrate electrode 1, a capacitance insulating film 2, a capacitance electrode 3, a lead electrode 4, and an N type diffusion layer 5. And the semiconductor substrate 6, and the memory capacitance portion is formed between the substrate electrode 1 and the capacitance electrode 3.

【0003】図5に示す基板電極1は、図7の斜視図に
示すような2本の四角柱の組み合わせ形状をしており、
基板電極1の上面即ち図7の寸法A×Bの部分は、四角
形となっている。
The substrate electrode 1 shown in FIG. 5 has a combined shape of two square poles as shown in the perspective view of FIG.
The upper surface of the substrate electrode 1, that is, the portion of dimension A × B in FIG. 7 is a quadrangle.

【0004】従来のスタックや半導体メモリ装置では、
図6の平面図に示すように、図7に示す形状の基板電極
1が、半導体基板6の主表面に規則的に多数配列されて
いる。
In conventional stacks and semiconductor memory devices,
As shown in the plan view of FIG. 6, a large number of substrate electrodes 1 having the shape shown in FIG. 7 are regularly arranged on the main surface of the semiconductor substrate 6.

【0005】[0005]

【発明が解決しようとする課題】前述した従来の半導体
メモリ装置の基板電極1の形状では、デバイスの特性及
び信頼性を向上させる為にメモリ容量部の容量を大きく
する際に、容量絶縁膜2の膜厚を一定とした場合、基板
電極1の上面面積(図7の寸法A×B)を大きくする
か、もしくは基板電極1の側面の高さ(図7の寸法C)
を高くしなければならないが、前者の構成ではチップ面
積が大きくなるという欠点があり、また後者の構成では
基板電極1形成後の段差が大きくなる為、製造条件が厳
しくなるという欠点があった。
With the shape of the substrate electrode 1 of the conventional semiconductor memory device described above, the capacitance insulating film 2 is used when the capacitance of the memory capacitance portion is increased in order to improve the characteristics and reliability of the device. If the film thickness is constant, the upper surface area of the substrate electrode 1 (dimension A × B in FIG. 7) is increased, or the side surface height of the substrate electrode 1 (dimension C in FIG. 7)
However, the former configuration has a drawback that the chip area is large, and the latter configuration has a drawback that the manufacturing conditions are strict because the step difference after forming the substrate electrode 1 is large.

【0006】[0006]

【課題を解決するための手段】本発明の半導体メモリ装
置の構成は、2n角形の上部形状を有する基板電極を備
えていることを特徴とする。
The structure of a semiconductor memory device of the present invention is characterized in that it is provided with a substrate electrode having a 2n square upper shape.

【0007】[0007]

【実施例】本発明の第1の実施例の基板電極の配置を示
す図1の平面図、この基板電極の形状を示す図2の斜視
図を参照すると、この実施例は、基板電極1の上部の向
かい合う1組の側面を同一方向に屈折させる(ここでは
矢羽根状)ことにより、基板電極1の上面面積は一定で
も側面面積は、大きくなる。この上面は、六角形を有す
る。
1 is a plan view showing the arrangement of substrate electrodes according to the first embodiment of the present invention, and FIG. 2 is a perspective view showing the shape of the substrate electrodes. By refracting the pair of upper side surfaces facing each other in the same direction (here, in the shape of an arrow blade), the side surface area is large even if the upper surface area of the substrate electrode 1 is constant. The upper surface has a hexagonal shape.

【0008】また、図1に示すように、基板電極1は規
則的に配置される為、この形状にしてもチップ面積は一
定である。尚図5については、共通するため、説明を省
く。
Further, as shown in FIG. 1, since the substrate electrodes 1 are regularly arranged, the chip area is constant even with this shape. Note that the description of FIG. 5 is omitted because it is common.

【0009】本発明の第2の実施例の基板電極の配置を
示す図3の平面図、この基板電極の形状を示す図4の斜
視図を参照すると、この実施例は、中折れ矢羽根状とも
いうべき八角形の基板電極1上部の形状を有し、これは
向かい合う2組の側面をそれぞれ同一方向に屈折させる
ことにより、基板電極1の上面面積は一定でも、側面面
積は図2よりも大きくなる。
Referring to the plan view of FIG. 3 showing the arrangement of the substrate electrodes of the second embodiment of the present invention, and the perspective view of FIG. 4 showing the shape of the substrate electrodes, this embodiment shows a center bent arrow blade shape. It has an octagonal shape of the upper part of the substrate electrode 1, and by refracting two sets of facing side faces in the same direction, the side face area is smaller than that of FIG. growing.

【0010】また、図3に示すように、基板電極1は、
規則的に配置される為、チップ面積は一定である。従っ
て、第2の実施例は、第1の実施例以上の効果が得られ
る。また、第1の実施例においては、向かい合う1組の
側面を同一方向に屈折させているのに対し、第2の実施
例においては向かい合う2組の側面を同一方向に屈折さ
せているため、第1の実施例より側面面積を大きくする
ことが可能である。
Further, as shown in FIG. 3, the substrate electrode 1 is
Since they are arranged regularly, the chip area is constant. Therefore, the second embodiment can obtain the effects more than those of the first embodiment. Further, in the first embodiment, one pair of side surfaces facing each other is refracted in the same direction, whereas in the second embodiment, two pairs of side surfaces facing each other are refracted in the same direction. The side surface area can be increased as compared with the first embodiment.

【0011】このように、基板電極1の上面形状は、2
n(nは3以上の整数)角形であれば、図1,図3に示
すような全体のチップ面積を増加させずに、側面面積を
増加できる。
Thus, the top surface shape of the substrate electrode 1 is 2
If it is an n (n is an integer of 3 or more) polygon, the side surface area can be increased without increasing the entire chip area as shown in FIGS.

【0012】[0012]

【発明の効果】以上説明したように、本発明は、基板電
極の側面面積を大きくし、かつ基板電極を規則的に配置
させるので、チップ面積,基板電極の上面面積及び高さ
を増加させることなく、メモリセル容量部の容量を大き
くできるという効果を有する。
As described above, according to the present invention, since the side surface area of the substrate electrode is increased and the substrate electrodes are regularly arranged, the chip area, the upper surface area and the height of the substrate electrode can be increased. This has the effect of increasing the capacity of the memory cell capacity section.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例の基板電極の配置を示す
平面図である。
FIG. 1 is a plan view showing an arrangement of substrate electrodes according to a first embodiment of the present invention.

【図2】本発明の第1の実施例の基板電極の形状を示す
斜視図である。
FIG. 2 is a perspective view showing the shape of a substrate electrode according to the first embodiment of the present invention.

【図3】本発明の第2の実施例の基板電極の配置を示す
平面図である。
FIG. 3 is a plan view showing an arrangement of substrate electrodes according to a second embodiment of the present invention.

【図4】本発明の第2の実施例の基板電極の形状を示す
斜視図である。
FIG. 4 is a perspective view showing a shape of a substrate electrode according to a second embodiment of the present invention.

【図5】メモリセルの構成を示す断面図である。FIG. 5 is a cross-sectional view showing the structure of a memory cell.

【図6】従来の基板電極の配置を示す平面図である。FIG. 6 is a plan view showing an arrangement of conventional substrate electrodes.

【図7】従来の基板電極の形状を示す斜視図である。FIG. 7 is a perspective view showing the shape of a conventional substrate electrode.

【符号の説明】[Explanation of symbols]

1 基板電極 2 容量絶縁膜 3 容量電極 4 ゲート電極 5 N型拡散層 6 半導体基板 1 substrate electrode 2 capacitance insulating film 3 capacitance electrode 4 gate electrode 5 N type diffusion layer 6 semiconductor substrate

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上の基板電極上に絶縁膜を介
して容量電極を積層することにより、メモリ容量部が形
成される半導体メモリ装置において、前記基板電極が、
2n(nは3以上の整数)角形の上部形状を有すること
を特徴とする半導体メモリ装置。
1. In a semiconductor memory device in which a memory capacitor portion is formed by laminating a capacitor electrode on a substrate electrode on a semiconductor substrate with an insulating film interposed therebetween, the substrate electrode comprises:
A semiconductor memory device having a 2n (n is an integer of 3 or more) rectangular upper shape.
JP5133743A 1993-06-04 1993-06-04 Semiconductor memory device Pending JPH06350047A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5133743A JPH06350047A (en) 1993-06-04 1993-06-04 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5133743A JPH06350047A (en) 1993-06-04 1993-06-04 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPH06350047A true JPH06350047A (en) 1994-12-22

Family

ID=15111891

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5133743A Pending JPH06350047A (en) 1993-06-04 1993-06-04 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPH06350047A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11220205A (en) * 1998-01-30 1999-08-10 Sharp Corp Semiconductor laser element and manufacture thereof
US7217313B2 (en) 2002-05-30 2007-05-15 Tokyo Electron Limited Dehumidification system and dehumidification method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11220205A (en) * 1998-01-30 1999-08-10 Sharp Corp Semiconductor laser element and manufacture thereof
US7217313B2 (en) 2002-05-30 2007-05-15 Tokyo Electron Limited Dehumidification system and dehumidification method

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